FULL ADDER
Mindanao State University - Iligan Institute of Technology
Abstract— Presented in this paper is comparison of a 0 0 1 1 0
conventional full adder circuit and an improved circuit. 0 1 0 1 0
The improved adder circuit consists of 10 transistors 0 1 1 0 1
reducing the area utilization. It operates at 1.2V and has 1 0 0 1 0
average power consumption of 2.94uW. 1 0 1 0 1
1 1 0 0 1
Index Terms— Binary Full Adder 1 1 1 1 1
I. INTRODUCTION In a binary adder circuit, A B and Cin act as input bits
with SUM and CARRY that act as outputs
Full adder circuit is the core of many digital and analog
circuits. It is a critical module for operation of complex SUM = (A ⊕ B) ⊕ Cin (1)
arithmetic operation such as addition. Improving the Cout = ( A.B ) +(Cin. (A ⊕ B)) (2)
performance of the adder is important. The main aim of
designing arithmetic circuit is to reduce power consumption
and increase the speed.
Several papers have investigated different approaches in
realizing full adders using CMOS technology while most tend
to use the conventional structure.
The objective of this work is to improve the conventional
full adder. Performance criteria considered for design
comparison include the area, delay, and power consumption as A. Conventional Full Adder Architecture
it is considered the main aim in designing arithmetic circuits.
The goal of a binary full adder is to implement the
following truth table for each bit.
Table 1. Truth Table for 1-bit adder
A B Cin Su Cout
m
0 0 0 0 0
The improved adder consists of 10 transistors. The
structure is designed for low power combinational circuits.
This approach diminishes power utilization, delay of the
circuit and while keeping up a logic circuit with less
complexity.
II. RESULTS AND DISCUSSIONS
A. Conventional Full Adder
Figure 1. Conventional CMOS Full Adder
The conventional full adder design consists of 28
transistors. The structure poses several disadvantages – the
presence of series of transistors causes the adder to have poor
driving capability, and it occupies more area due to a number
of transistors.
B. Improved Full Adder (a)
(b)
Figure 3: Propagation Delay and Power Consumption of
Figure 2: Improved Full Adder Circuit Conventional Full Adder (a) Pre-Sim (b) Post-Sim
Figure 3 shows the simulation output of the conventional
adder. The results are summarized in Table 2. The propagation
delay of signal Sum with respect to Cin, tPHL is 3.733 ns and
tPLH is 4.06 ns while for the signal Cout, t PHL is 1.43 ns and t PLH
is 2.09 ns.
Table 2. Propagation delay for Conventional
PRE-SIM POST-SIM
tPHL tPLH tPHL tPLH
Sum 3.733 ns 4.06 ns 4.16ns 4.7ns
Cout 1.43 ns 2.09 ns 1.82ns 2.57n
(b)
Figure 5: Propagation Delay and Power Consumption of
Improved Full Adder (a) Pre-Sim (b) Post-Sim
Figure 5 shows the simulation output of the improved
adder. Although the adder itself consists of 10T transistor, a
Figure 4. Conventional Adder Layout buffer was used in the Sum and Carry output to restore the
signal to its original level – vdd for logic high and gnd for
Figure 4 shows the conventional adder layout. The logic low. The propation delay from Low to High t PLH and
dimension for the layout is 19.15μm x 8.70μm. High to low logic tPHL as well as the power consumption, was
measured.
B. Improved Full Adder The simulation results are summarized in Table 3. The
propagation delay of signal Sum with respect to Cin, t PHL is
268 ps and tPLH is 388 ps while for the signal Cout, tPHL is 267
ps and tPLH is 1.46 ns
Table 3. Propagation Delay for Improved
PRE-SIM POST-SIM
tPHL tPLH tPHL tPLH
Sum 467ps 664ps 268 ps 388 ps
(a) Cout 476ps 3.2n 267 ps 1.46 ns
Transistors Consumption
[1] 45nm 16T 1.91.mW
[2] 65nm - 17.92mW
[3] - 10T 5.60mW
[3] CMOS 28T 13.2mW
This work 65nm 10T 2.94uW
III. CONCLUSION
Figure 6. 10T Adder Layout The aim of this work was the power reduction in the full
adder circuit. A 10T Adder is used. Techniques like transistor
Figure 6 shows the improved adder layout. The dimension size optimization and addition of buffer at the output stage,
for the layout of the 10T adder is 8.21 μm x 4.835 μm. reduce the power consumption and achieve full swing.
The average power consumption of the 10T adder is
C. Comparison 2.94uW with layout area dimension of 8.21 μm x 4.835 μm.
Table 4. Table of Comparison The results are obtained with spice simulation tools.
PRE- POST-
SIM SIM
Adder Average Power No. of Layout REFERENCES
Type Consumption Tran- Dimension
sistors
Conventional 46u 30.7u 28 19.15u x 8.70u
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Table 4 shows the comparison of the two adders in terms Aensiweb.Net, 2017.
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[2] S. Gao, H. Jiang, Z. Wang, W. J.-2018 I. International,
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and undefined 2018, “Low voltage low power full
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circuit and the power consumption.
From the result shown in Table 2 and Table 3, the 10T
[3] M. Devadas “Design Topologies For Low Power CMOS
adder implemented with buffer at the output has a lesser
Full Adder,” no. 3, pp. 4–7, 2017.
propagation delay compared to the conventional adder.
For the area utilization, the 10T adder uses lesser space
compared to the conventional adder.
Work Technology No of Power
