EX.NO.

CHARACTERISTICS OF PN DIODE
DATE:

AIM:
i) To plot the V- I characteristics of silicon PN junction diode.
ii) To find the static and dynamic resistance in both forward bias and reverse
bias condition.

APPARATUS REQUIRED:

Serial No. Apparatus Specification Quantity

1 Regulated Power supply 0-30V 1
2 Resistor 1K Ohm 1
3 Voltmeter 0-30V, 0-1V Each 1
4 Ammeter 0-30mA, 0-1mA Each 1
5 PN Diode IN4001 1
6 Connecting wires
7 Bread Board 1

THEORY- PN JUNCTION DIODE:

A PN junction diode has two terminals the P region of the diode is called ‘anode’ and N region
called ‘cathode’. It is an unilateral diode i.e. the diode can conduct only in one direction. (only on
forward biasing).

FORWARD BIAS:

On forward biasing, initially no current flows due to barrier potential. As the applied potential
exceeds the barrier potential the charge carriers gain sufficient energy to cross the potential barrier
and hence enter the other region. The holes, which are majority carriers in the P-region, become
minority carriers on entering the N-regions, and electrons, which are the majority carriers in the
PN JUNCTION DIODE - FORWARD BIAS:
R
+ -
A SYMBOL PN DIODE
1K ohm C
(0 - 30)mA
CATHODE - K
RPS A
(0-30)V +
IN4001
V
- K IN4001
-
(0 - 1)V ANODE - A

REVERSE BIAS:
R
+ -
A
1K ohm
(0 - 1)mA

RPS K
(0-30)V +
IN4001
V
-
A -
(0 - 30)V

MODEL GRAPH:
IF (mA)
IF (mA)

ΔIF
ΔVR
ΔIF
VR (Volt) ΔVR ΔVF VF (Volt)
ΔIR
VR (Volt) ΔIR ΔVF VF (Volt)
(mA)
IIRR (mA)
N-region become minority carriers on entering the P-region. This injection of Minority carriers
results in the current flow, opposite to the direction of electron movement.
In the forward bias, the anode terminal is connected to positive terminal of the battery supply.
Under forward bias condition, the supplied positive potential repels the holes in the P region.
Hence the holes move towards the junction.
REVERSE BIAS:

On reverse biasing, the majority charge carriers are attracted towards the terminals due to the
applied potential resulting in the widening of the depletion region. Since the charge carriers are
pushed towards the terminals no current flows in the device due to majority charge carriers. There
will be some current in the device due to the thermally generated minority carriers. The generation
of such carriers is independent of the applied potential and hence the current is constant for all
increasing reverse potential. This current is referred to as Reverse Saturation Current (I O) and it
increases with temperature.
When the applied reverse voltage is increased beyond the certain limit, it results in breakdown.
During breakdown, the diode current increases tremendously. In the reverse bias the anode of the
diode is connected to the negative terminal of the battery, and cathode is connected to the
positive terminal on the battery supply. Under the reverse bias condition, the holes of the P-region
move towards the negative terminal of the battery for large applied reverse bias voltage,
breakdown of junction occurs, leading to large reverse current.

Formula- PN DIODE:
Forward bias :
i. Static resistance RF= VF/IF Ω
ii. Dynamic resistance ΔRF= ΔVF/ΔIF Ω
Reverse bias :
i. Static resistance RR= VR/IR Ω
ii. Dynamic resistance ΔRR= ΔVR/ΔIR Ω
Where,
VF =Forward Voltage IF = Forward current
VR =Reverse Voltage IR = Reverse current
TABULATION:
Forward Bias Reverse Bias
Voltage in Volts Current in mA Voltage in Volts Current in mA
VF IF VR IR

CALCULATION:
PROCEDURE
FORWARD BIAS:

1. Connect the circuit as per the circuit diagram.

2. By varying the RPS get the different voltage in the voltmeter VF and notedown the
corresponding current value IF in the ammeter.
3. Plot the graph between voltage Versus Current.
4. Measure the dynamic resistance and cut in voltage from the graph.

REVERSE BIAS:

1. Connect the circuit as per the circuit diagram.

2. By varying the RPS get the different voltage in the voltmeter V R and notedown the
corresponding current value IR in the ammeter.
3. Plot the graph between voltage Versus Current.
4. Measure the dynamic resistance from the graph.

RESULT:
i. Thus the V- I characteristics of silicon PN junction diode was plotted.
ii. Forward bias
Static resistance RF
Dynamic resistance ΔRF
Cut in voltage
Reverse bias
Static resistance RR
Dynamic resistance ΔRR
EX.NO. CHARACTERISTICS OF ZENER DIODE
DATE:

AIM:
i) To plot the V- I characteristics of Zener diode.
ii) To find the static and dynamic resistance in both forward bias and reverse
bias condition.

APPARATUS REQUIRED:

Serial No. Apparatus Specification Quantity

1 Regulated Power supply 0-30V 1
2 Resistor 1K Ohm 1
3 Voltmeter 0-30V, 0-1V Each 1
4 Ammeter 0-30mA 1
5 Zener Diode FZ 9.1V 1
6 Connecting wires
7 Bread Board 1

THEORY-ZENER DIODE:
Zener diode is a semiconductor device, which operates in the breakdown region. It is specified
by its breakdown voltage and power dissipation capability, which ranges from 3V to 100V and
few milliwatts to 50 W respectively. Zener diode can be used as a constant voltage source
particularly when there is change in load voltage due to change in input supply. During the
reverse bias, there is a sharp increase in the current after reaching the breakdown voltage. This
is due to zener breakdown and avalanche breakdown.

Zener breakdown:
When reverse bias is increased under the influence of high electric field, the electrons are
pulled up from the covalent bonds. This causes sharp increase in the reverse current. This is
called zener breakdown.
 ZENER DIODE - FORWARD BIAS

SYMBOL ZENER
DIODE

CATHODE - K
FZ 9.1

6.6V

ANODE - A

REVERSE BIAS:

MODEL GRAPH:
IF (mA)

ΔIF
ΔVR
VR (Volt) ΔIR ΔVF VF (Volt)
IR (mA)
 Avalanche Breakdown
When the reverse bias voltage is applied across the zener diode the minority carriers in the
technical region, gets accelerated and affair sufficient kinetic energy. These minority carriers
disrupt covalent bonds and create new electrons by collision. This phenomenon cumulatively
generates an avalanche of charge carriers in the short time, thereby causing a sharp increase in
the reverse current.
Formula - ZENER DIODE:
Forward bias :
iii. Static resistance RF= VF/IF Ω
iv. Dynamic resistance ΔRF= ΔVF/ΔIF Ω
Reverse bias :
iii. Static resistance RR= VR/IR Ω
iv. Dynamic resistance ΔRR= ΔVR/ΔIR Ω
Where,
VF =Forward Voltage IF = Forward current
VR =Reverse Voltage IR = Reverse current

PROCEDURE - ZENER DIODE:

FORWARD BIAS:
1. Connect the circuit as per the circuit diagram.
2. By varying the RPS get the different voltage in the voltmeter VF and notedown the
corresponding current value IF in the ammeter.
3. Plot the graph between voltage Versus Current.
4. Measure the dynamic resistance from the graph.

REVERSE BIAS:
1. Connect the circuit as per the circuit diagram.
2. By varying the RPS get the different voltage in the voltmeter V R and notedown the
corresponding current value IR in the ammeter.
3. Plot the graph between voltage Versus Current.
 4. Measure the dynamic resistance and breakdown voltage from the graph.
TABULATION:
Forward Bias Reverse Bias
Voltage in Volts Current in mA Voltage in Volts Current in mA
VF IF VR IR

CALCULATION :
RESULT:
i. Thus the V- I characteristics of ZENER diode was plotted.
ii. Forward bias
Static resistance RF
Dynamic resistance ΔRF
Reverse bias
Static resistance RR
Dynamic resistance ΔRR
Breakdown voltage
Circuit diagram of Full wave rectifier with filter:

T1 BC107
D1 1N4007

R2 230
C1 100u
R1 1k

R3 1k
+

Z1 1N2804
TR1 V VM1

N2
N1
N3

D2 1N4007

Model graph:

Load Regulation:

Vout

RL (Ω)
Tabular column:
Without filter With filter
Input signal Output signal
Amplitude(V) Time period Amplitude(V) Time period

Load regulation:
S.no Load resistance Out put voltage (V)
Ex. no:
Date:

POWER SUPPLY CIRCUIT - FULL WAVE RECTIFIER WITH SIMPLE CAPACITOR FILTER

Aim:
To measure the DC voltage under load and ripple factor and Compare with calculated values.
Plot the Load regulation characteristics using Zener diode.

Apparatus required:

SI NO APPARATUS RANGE QUANDITY

1 Transformer (220/12V) 1
2 p-n diode 1N4001 2
3 Resistors (1K ,220 ) 1
4 Capacitor 100µF 1
5 zener diode FZ5.1 1
6 Transistor SL 100 1
7 DRB 1

Formula Used:

Dc voltage under load = 2Vm/π

IRMS = Im/√2 , IDC=2 Im/π , Im=Vm/RL

Ripple Factor = √ [IRMS / IDC ] 2-1

Where Im is the peak current

Ripple Factor = √ [(Im/√2) / (2*Im /л)] 2-1

Where Im is the peak current

Theory:
The full wave rectifier conducts for both the positive and negative half cycles of the input ac supply. In
order to rectify both the half cycles of the ac input, two diodes are used in this circuit. The diodes feed a
common load RL with the help of a centre tapped transformer. The ac voltage is applied through a suitable
power transformer with proper turn’s ratio. The rectifier’s dc output is obtained across the load.
The dc load current for the full wave rectifier is twice that of the half wave rectifier. The lowest ripple
factor is twice that of the full wave rectifier. The efficiency of full wave rectification is twice that of half wave
rectification. The ripple factor also for the full wave rectifier is less compared to the half wave rectifier.
Procedure:
Connections are given as per the circuit diagram wiyhout filter.
Note the amplitude and time period of the input signal at the secondary winding of the transformer and rectified
output.Repeat the same steps with the filter and measure V dc. Calculate the ripple factor. Decade resistance box
is connected as load. The load is varied from minimum value to maximum value.The output voltage is noted at
the each variation and draw load regulation.

Result:
Thus the full wave rectifier was constructed and its input and output waveforms are drawn.
The ripple factor of capacitive filter is calculated as

Ripple factor= and load regulation characteristics were obtained.

EX.NO : CHARACTERISTICS OF COMMON EMITTER TRANSISTOR
DATE:

AIM:
To determine the input and output characteristics of Bipolar Junction Transistor (BJT) in
common emitter configuration.
APPARATUS REQUIRED:
Serial No. Apparatus Specification Quantity
1 Regulated Power supply 0-30V 2
2 Resistor 1K Ohm 2
3 Voltmeter 0-30V, 0-1V Each 1
4 Ammeter 0-1mA 2
5 Transistor BC107 (NPN) 1
6 Connecting wires
7 Bread Board 1
THEORY
A transistor, in a common-emitter configuration, has two important characteristics namely
input characteristics and output characteristics.
INPUT CHARACTERISTICS
These curve give the relation between the base current (IB) and the base-to-emitter voltage
(VBE) for a constant collector-to-emitter voltage(VCE).
First of all, we adjust the collector-to-emitter voltage to 1 volt. Then we increase the base-
to-emitter voltage in small suitable steps and record the corresponding values of base current at
each step. If we plot a graph with base-to-emitter voltage along the vertical axis. We shall obtain a
curve marked VBE=1V as shown in the model graph. A similar procedure may be used to obtain
characteristics at different values of collector-emitter voltage.
The input characteristics give us the information about the following important points.
1) There exists a threshold or knee voltage(VK) below which the base current is very small. The
value of Knee voltage is 0.5V for Si and 0.1V for Ge transistors.
CIRCUIT DIAGRAM:

C
R1 B R2
A NPN A
1K Ohm + - - + 1K ohm

(0 - 1)mA BC107 (0 - 5mA)

E

+
RPS1 + (0 - 30V)
0-30V
V
V RPS2
(0 - 1V) -
- 0-30V
-
-

INPUT CHARACTERISTICS:
SYMBOL
C
VCE = 2V

VCE = 6V
VCE = 0V

VCE = 4V

NPN E
IB(mA)

BC107
DC107
PIN DIAGRAM
ΔIB

B C
ΔVBE
E
0.4 0.5 0.6 VBE(V)
2) Beyond the Knee, the base current(IB) increases with the increase in base-to-emitter voltage
(VBE) for a constant collector-to-emitter voltage(VCE).However, it may be noted that the value of
base current does not increases as rapidly as that of the input characteristic of a common-base
transistor.It means that input characteristic resistance of a transistor in common-emitter transistor
configuration is higher as compared to the common-base configuration.
3) As the collector-to-emitter voltage(VCE) is increased above 1V, the curve shifts down wards.
It occurs because of the fact, that as VCE is increased, the depletion width in the base-region
increases. The reduction in the effective base width, in turn reduces the base current.
4) The input characteristics may be used to determine the value of common emitter transistor
a.c input resistance(Ri). Its value is given by the ratio of change in base-to-emitter voltage to the
resulting change in base current to a constant collector-to-emiter voltage mathematically, the a.c
input resistance.
Input resistance Ri = Ω
It may be noted that the input characteristics is not linear in the lower region of the
curve. Therefore, the input resistance varies with the location of the operating point. The value of
a.c input resistance ranges from 600Ω to 4000Ω.

OUTPUT CHARACTERISTICS
These curve give the relation between the collector current(IC) and collector base
current(IB).To begin with,the base current(IB)to 40µA value. Then increase the collector-to-emitter
voltage(VCE)in a number of steps and record the corresponding values of collector current(IC) at
each step. If we plot a graph with collector-to-emitter voltage(VCE) along the horizontal axis and
collector current (IC) along the vertical axis, we shall obtain a curve marked IB=40µA as shown in the
model graph. Similar procedure may be used to obtain characteristics t IB=8µA, 120µA and so on.
The output characteristics give us the information about the following important points.
1) The output characteristics may be divided into three important regions namely saturation
region, active region and cut-off region. The shaded areas show the cut-off region and saturation
regions, while the active region is the region between the saturation and cut-off region.
2) As the collector-to-emitter voltage(VCE) is increased above zero, the collector current(IC)
increases rapidly to saturation value, depending upon the value of base current. It may be noted that
collector current(IC) reaches to a saturation value when VCE is about 1V.
TABULATION - INPUT CHARACTERISTICS

VCE1 = VCE2 =
S.No
VBE (V) IB (mA) VBE (V) IB (mA)

OUTPUT CHARACTERISTICS:

Saturation Region

Active Region
IC (mA)

IB = 4mA

IB = 3mA

IB = 2mA

IB = 1mA
ΔIC

ΔVCE
IB = 0mA

VCE (V)
Cut off Region
3) When the collector-to-emitter voltage(VCE) is increased further, the collector current(IC)
slightly increases. This increase in collector current(IC) is due to the fact that increased value of
collector-to-emitter voltage(VCE) reduces the base current and hence the collector current increases.
This phenomenon is called early effect.
4) When the base current is zero, a small collector current exists. This is called leakage current.
However for all practical purposes the collector current(IC) is zero, when the base current (IB) is
zero. Under this condition, the transistor is said to be cut-off.
5) The characteristics may be used to determine the common-emitter transistor a.c output
resistance. Its value at any given operating point ‘Q’ is given by the ratio of change in collector-to-
emitter voltage to the resulting change in collector current for a constant base current.
Mathematically, the a.c output resistance,

Ro = Ω
The characteristic may be used to determine the small signal common-emitter current gain
beta(βo) of a transistor.

Βo =

Formula :
Hybrid Input Impedance ,hie = VBE/ IB ,VCE= Constant
Hybrid output admittance, hOe =( IC/ VCE ),IB = Constant
Hybrid forward current gain, hfe =( IC/ IB ), VCE= Constant
Hybrid reverse voltage gain, hre =( VBE/ VCE ),IB = Constant

PROCEDURE:
INPUT CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram.
2. By adjusting the RPS (2) set the collector to emitter voltage VCE to a particular voltage.
3. Now vary the base to emitter voltage VBE by adjusting the RPS(1) and note down the
corresponding variation in the base current IB
4. Repeat steps 1 to 3 for various values of VCE
TABULATION - OUTPUT CHARACTERISTICS

IB1 = IB2 =
S.No
VCE (V) IC (mA) VCE (V) IC (mA)

CALCULATION:
OUTPUT CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram.
2. By adjusting the RPS (1) set the base to emitter voltage VBE to a particular voltage and note
down the corresponding IB value.
3. Now vary the collector to emitter voltage VCE voltage by adjusting the RPS(2) and note down
the corresponding variation in the collector current Ic
4. Repeat steps 1 to 3 for various values of VBE.
5. Plot the graph for the input and output characteristics from tabulation and find out the
input resistance, output resistance and current gain.

RESULT:
Thus the input and output characteristics of BJT under CE configuration was determined
and their parameters were listed below.
1. Hybrid Input Impedance
2. Hybrid output admittance
3. Hybrid forward current gain
4. Hybrid reverse voltage gain
EX.No. CHARACTERISTICS OF MOSFET
DATE :
AIM:
To determine the Drain and Transfer characteristics of MOSFET.
APPARATUS REQUIRED:
Serial No. Apparatus Specification Quantity
1 Regulated Power supply (0-30)V 2
2 Resistor 1K Ω 2
3 Voltmeter (0-30)V 2
4 Ammeter (0-1) mA 1
5 MOSFET IRF Z44N 1
6 Connecting wires
7 Bread Board 1

THEORY –MOSFET:
MOSFET is the common term for the Insulated Gate Field Effect Transistor (IGFE1) There are two basic
forms of MOSFET
(i) Enhancement MOSFET
(ii) Depletion MOSFET.

PRINCIPLE:
By applying a transverse electric field across an insulator, deposited on the semiconducting material, the
thickness and hence the resistance of a conduction channel of a semiconducting material can be controlled.
In a depletion layer MOSFET, the controlling electric field seduces the number of majority carriers available
for conduction, whereas in the enhancement MOSFET application of electric field causes an increase in the
majority carrier density it lit conducting legions of the transistor.
CIRCUIT DIAGRAM

SYMBOL :

DRAIN CHARACTERISTICS :
MODEL GRAPH:
PROCEDURE:
DRAIN CHARACTERISTICS
1. Connect the circuit as per the circuit diagram.
2. Keep VGS =0 and note IDSS value.
3. Make VGS =1 and vary the VDS value and note down the corresponding ID values by
increasing the drain-to-source voltage (VDS).
4. Repeat step 3 for various values of VGS.
5. Plot the graph between drain current ID and source drain voltage (VDS).

TRANSFER CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram.
2. From the same circuit, to obtain the transfer characteristic keep drain to source voltage
VDS=5 as constant and decrease the VGS constantly to get the transfer characteristics.
3. Note down the corresponding drain current ID.
4. Plot the graph between source to gate voltage VGS and drain current ID.

RESULT:
Thus the Drain and Transfer characteristics of MOSFET was determined.
 TABULATION :

VGS = VGS =
VDS (V) ID (mA) VDS (V) ID (mA)

TRANSFER CHARACTERISTICS :
MODEL GRAPH: TABULATION :

VDS =
VGS (V) ID (mA)
. Frequency Response of CE amplifier

Model Graph:

f1 f2 f (Hz)

Tabular Column:
Keep the input voltage constant (Vin) =

Frequency (Hz) Output voltage (volts) Gain=20log(V0/Vin) db

Ex. no:
Date:

. FREQUENCY RESPONSE OF CE AMPLIFIER

Aim:
To design and construct BJT Common Emitter Amplifier using fixed bias . To measure the gain and to
plot the frequency response and to determine the Gain Bandwidth product (GBW) and bias resistance to locate
Q-point at center of load line.
Apparatus Required:

S.No. Name Range Quantity

1. Transistor BC 107 1
2. Resistor 5.1kΩ, 3MΩ 1,1
3. Capacitor 0.01µF 2
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Bread Board and 1
Connecting wires

Theory:

In order to operate the transistor in the desired region, we have to apply an external dc voltage of correct
polarity and magnitude to the two junctions of the transistor. This is called biasing of the transistor. When
we bias a transistor, we establish certain current and voltage conditions for the transistor. These conditions are
called operating conditions or dc operating point or quiescent point. This point must be stable for proper
operation of transistor. An important and common type of biasing is called Fixed Biasing. The circuit is very
simple and uses only few components. But the circuit does not check the collector current
which increases with the rise in temperature.

Design :
Choose β = 250, VCC = 12V, IC = 1 mA
By applying KVL to output side,
V CC – I CR C – V CE = 0
V CC = I C R C – V CE
Assume equal drops across RC and VCE
VRC = VCE = 6V, ICRC = 6V
RC = 6V/10-3 = 6KΩ
Choosing a standard value for RC as 5.1 KΩ
By applying KVL to the input side,
V CC – I BR B – V BE = 0
IB = IC/β = 1mA/250 = 4µA
RB = (VCC – VBE) / IB
= (12 – 0.7)/4x10-6
= 2.825M Ω
≈ 3M Ω

Design of input capacitor:

F = 1/2πhieC
Take F = 1000Hz and hie = 1.6 KΩ
C1 = 1/ (2π X 1.6 KΩ X 100) = 0.09µF≈ 0.01µ F
Procedure:
1) Connect the circuit as per the circuit diagram
2) Set Vin = 0.2V in the signal generator. Keeping input voltage constant, vary the frequency from
100Hz to 1MHz in regular steps.
3) Note down the corresponding output voltage.
4) Plot the graph: Gain in dB Vs Frequency in Hz.
5) Calculate the Bandwidth from the Frequency response graph

Result::

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and
the frequency response curve is plotted.

The bandwidth is found to be -------

The bias resistance -------
Gain Bandwidth product -----
Circuit diagram of common source amplifier

Model graph:

f1 f2 f (Hz)

TABULAR COLUMN:

Frequency (Hz) Output voltage (volts) Gain=20log(V0/Vin) db

Ex. no:
Date:
COMMON SOURCE AMPLIFIER

Aim:
To design a common source amplifier and to measure the gain, input resistance and output
resistance with and without Bootstrapping.

Apparatus required:
S.No. Name Range Quantity
1. FET BFW10 1
2. Resistor 4.7KΩ, 2.7KΩ, 1MΩ 1,1,1
3. Capacitor 10µ F 1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Connecting wires & 1
Breadboard

Theory:
Source follower is similar to the emitter follower (the output source voltage follow the gate input voltage), the
circuit has a voltage gain of less than unity, no phase reversal, high input impedance, low output impedance.
Here the Bootstrapping is used to increase the input resistance by connecting a resistance in between gate and
source terminals. The gate resister is required to develop the necessary bias for the gate.
Here input is applied between gate and source & output between source and Drain. Here Vs = VG + VGS. When
a signal is applied to JFET gate via Cin,VG varies with the signal. As VGS is fairly constant and Vs varies with
Vi. Here output voltage follows the change in the signal voltage applied to the gate, the circuit is also called as
Source follower.

The biasing network consists of R1 and R2 lower the input resistor of the gate in source followers. The
technique of Boot Strapping of this is used to resolve the high input resistance. Assuming the resistance of
external capacitance between the gate and source too negligible at the lowest operating frequency and the gain to
the near unit the potential and its upper end, thus the circuit resists its words, practically zero voltage exists
across R3 and so it takes an current. Hence R3 is isolated from the input and R1, R2 input to amplifier passes
through the gate only.

When a small ac signal is coupled into the gate it produces variations in gate source voltage. This
produces a sinusoidal drain current. Since an ac current flows through the drain resistor. An amplified
ac voltage is obtained at the output. An increase in gate source voltage produces more drain current,
which means that the drain voltage is decreasing. Since the positive half cycle of input voltage
produces the negative half cycle of output voltage, we get phase inversion in a CS amplifier.
Bias design:

VDD = 12 V, IDSS = 9.5mA, ID = 1mA, VP = -4V, Ci = 1µF

VGS = ID RS , ID = IDSS{1-(VGS/VP)}2
RS = 2.7KΩ
, Voltage drop across RS = 2.7V
VRD + VDS = VDD-VRS
= 12-2.7=9.3V.
Assume equal drops across VRD & VDS
VRD = VDS = 4.65V
RD = VRD/ID = 4.65KΩ
Instead of 4.65KΩ, we can select standard value = 4.7KΩ
FET input is always reverse bias. So choose the value of resistance RG very large with in
the range of 1MΩ to 10MΩ

Procedure:

1. Connect the circuit as shown in the circuit diagram

2. Set Vs= 1mv in AFO
3. Keeping the input voltage constant, vary the frequency from 100 Hz to1MHz in regular
steps and note down the corresponding output voltage.
4. Plot the graph: gain Vs Frequency
5. Calculate the bandwidth from the Graph

Result:
Thus a common drain amplifier is designed and the gain, input resistance and output
Resistance is calculated using the measured parameters.
Circuit Diagram of Common collector amplifier

Model graph:

TABULAR COLUMN:

Keep the input voltage constant (Vin) =

Frequency (Hz) Output voltage (volts) Gain=20log(V0/Vin)

db
Ex. no:
Date:

FREQUENCY RESPONSE OF CC AMPLIFIER

Aim:
To design and construct BJT Common Collector Amplifier using voltage divider bias(self-bias).
To measure the gain and to plot the frequency response & to determination of Gain Bandwidth Product
Apparatus Required:

S.No. Name Range Quantity

1. Transistor BC 107 1
2. Resistor 6KΩ, 8KΩ, 10KΩ 1
3. Capacitor 0.01µF, 47µF 1,1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Bread Board and 1
Connecting wires

Design:

Since voltage amplification is done in the transistor amplifier circuit, we assume equal drops across VCE and
Emitter Resistance RE. VRE = 6V. The quiescent current of 1mA is assumed. We assume a standard supply of
Vcc = 12V
Drop across RE is assumed to be VRE =6V
Drop across VCE is VCC –VRE =6V
We know that ICQ =IE=IC
Now RE = VRE = 6 = 6KΩ
IE 1X 10-3

Design of R1 & R2:

Drop across RE is 6V
Drop across VBE is 0.6V
Drop across the resistance R2 is VR2 = VBE + VRE =6.6V
Assume R2 =10KΩ
VR2= VCC*R2
R1 + R2

6.6 V= 12 X 10 X 103
R1 + 10 X 103
R1 = 8 KΩ (3.3 K + 4.7 K)
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set Vin = 1mV using AFO.
3. Keeping the input voltage constant, vary the frequency from 100 Hz to 1 MHz in regular
steps and note down the corresponding output voltage.
4. Plot the graph gain Vs frequency.
5. Calculate bandwidth from the graph.

Result :
Thus a BJT Common Collector Amplifier is designed and implemented and the frequency
response curve is plotted.
Bandwidth =
MODEL GRAPH:

TABULAR COLUMN:

Amplitude Time period Distortion

INPUT
OUTPUT
Ex. no:
Date:
CASCODE AMPLIFIER
Aim:
To construct a cascode (class B amplifier) amplifier and observe the waveforms
Apparatus required:

S.No. Name Range Quantity

1. Transistor CL100, BC558 1,1
2. Resistor 4.7kΩ,15kΩ 47KΩ,1KΩ 2,1
3. Capacitor 100µF 2
4. Diode IN4007 2
5. Signal Generator (0-3)MHz 1
6. CRO 30MHz 1
7. Regulated power supply (0-30)V 1
8. Bread Board 1

Formula:

Maximum power output = (Pac)max=Vcc2/2RL

Efficiency,η = Pac/Pdc
Pac=Vm2/2RL
Pdc=2Vcc x Im
π
Im = Vm/RL = Vcc/RL

THEORY:
A power amplifier is said to be Class B amplifier if the Q-point and the input signal are selected such that the
output signal is obtained only for one half cycle for a full input cycle. The Q-point is selected on the X-axis.
Hence, the transistor remains in the active region only for the positive half of the input signal.
There are two types of Class B power amplifiers: Push Pull amplifier and complementary symmetry amplifier. In
the complementary symmetry amplifier, one n-p-n and another p-n-p transistor is used. The matched pair of
transistor are used in the common collector configuration. In the positive half cycle of the input signal, the n-p-n
transistor is driven into active region and starts conducting and in negative half cycle, the p-n-p transistor is
driven into conduction. However there is a period between the crossing of the half cycles of the input signals, for
which none of the transistor is active and output, is zero
It is a type of push-pull CLASS-B amplifier, which employs one PNP, and one NPN transistor and requires no
transformers. This type of amplifier use complementary symmetry. When the signal voltage is positive NPN
transistor will conduct, while PNP transistor is cut off.' When the signal voltage is negative T 2 conducts and T1 is
cut off.
Load Current IL= Ic1 - Ic2
Advantage of this amplifier is transformer less operation, saves on weight and cost and balanced Push- pull input
signals are not required. Disadvantages are the needs of both positive and negative of supply voltages.
PROCEDURE:
1. Connections are given as per the circuit diagram without diodes.
2. Observe the waveforms and note the amplitude and time period of the input signal and distorted
waveforms.
3. Connections are made with diodes.
4. Observe the waveforms and note the amplitude and time period of the input signal and output signal.
5. Draw the waveforms and calculate the maximum output power and efficiency.

RESULT:
Thus the Class B complementary symmetry power amplifier was constructed to observe cross-over
distortion and the circuit was modified to avoid the distortion. The following parameters were calculated:
a)Maximum output power=
b)Efficiency=
Circuit Diagram – Differential Amplifier

TABULAR COLUMN:
Common mode Difference mode
V1 (VOLTS) V2 (VOLTS) Vout V1 (VOLTS) V2 (VOLTS) Vout
(VOLTS) (VOLTS)
Ex. no:
Date:
DIFFERENTIAL AMPLIFIER

Aim :
To construct the Differential Amplifier in Common mode and Differential mode, and to find the common mode
rejection ratio (CMRR).

Apparatus required :

S.No. Name Range Quantity

1. Transistor BC 107 1
2. Resistor 1KΩ, 470Ω 2,1
3. Function Generator (0-3)MHz 1
4. CRO 30MHz 1
5. Regulated power supply (0-30)V 1
6. Connecting wires & 1
Breadboard

Formula:
C.M.R.R = Ad/Ac
C.M.R.R in dB = 20 log Ad/Ac
Ad = Differential mode gain ,
Ad=Vo/Vd, Where Vd=Vin =V1-V2
Ac = Common mode gain ,
Ac=Vo/Vc, Where Vc=Vin =V1+V2
2
Theory:
The Differential amplifier amplifies the difference between two input voltage signals. Hence it is called
differential amplifier.V1 and V2 are input voltages, Vo is proportional to difference between two input signals.
If we apply two input voltages equal in all respects then in ideal case output should be zero. But output voltage
depends on the average common level of the inputs. Such an average level of two input signals is called common
mode signal.Higher the value of C.M.R.R, better the performance of the differential amplifier. To improve
C.M.R.R we have to increase differential mode gain and decrease common mode gain.

Procedure :
1. Connections are given as per the circuit diagram
2. Set Vi=5mV and note down Vo in both differential mode & common mode
3. Calculate the gain for both the modes
4. Calculate C.M.R.R

Result :
Thus a differential amplifier is constructed in both common mode and differential mode
and the corresponding gains are obtained and the CMRR is calculated.
1. Common mode gain =
2. Differential mode gain =
3. CMRR =
Circuit Diagram:
Ex. no:
Date:
CLASS - A AMPLIFIER
Aim:
To design and construct a Class – A power amplifier. To observe the output waveform
and to measure the maximum power output and to determine the efficiency
Apparatus required:
S.No. Name Range Quantity
1. Transistor BC 107 1
2. Resistor 1KΩ,4.7KΩ,61KΩ,10KΩ 1,1,1,1
3. Capacitors 1µf,100µf 1,1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power supply (0-30)V 1
7. Connecting wires & 1
Breadboard

Formula:
Maximum power output =Po=Vo2/RL

Efficiency,η = Pac/Pdc
Pac=Vm2/2RL
Vm=Vpp/2
Pdc=VccxIcQ
IcQ= β x IBQ
IBQ = Vcc-VBE
RB

Theory:
The Class A amplifier is the most common and simplest form of power amplifier that uses the switching
transistor in the standard common emitter circuit configuration. The transistor is always biased "ON" so that it
conducts during one complete cycle of the input signal wave form producing minimum distortion and maximum
amplitude to the output. This means that the Class A Amplifier configuration is the ideal operating mode,
because there can be no crossover or switch-off distortion to the output waveform even during the negative half
of the cycle. Class A power amplifier output stages may use a single power transistor or pairs of transistors
connected together to share the high load current. Then the transistor switches "ON" it sinks the output current
through the Collector resulting in an inevitable voltage drop across the Emitter resistance thereby limiting the
negative output capability. The efficiency of this type of circuit is very low (less than 30%) and delivers small
power outputs for a large drain on the DC power supply. A Class A amplifier stage passes the same load current
even when no input signal is applied so large heat sinks are needed for the output transistors.
Bias design:
Since voltage amplification is done in the transistor amplifier circuit, We as equal drops
across VCE & load resistance RE. The quiescent current of 1mA is assumed, we assume a
standard supply of 12V.
Drop across RE is assumed to be 1V,the drop across VCE with a supply of 12V is given by 12-1V=11V
It is equal to 11/2=5.5V
Now the voltage across the resistance RE is 5.5V
VCE = 5.5V
VC = 5.5V
IC = 1mA
RC = 5.5V/1mA = 5.5KΩ
Instead of using 5.5KΩ , We can use a standard value of 4.7KΩ.
It is assumed that RBB / (βdc+1) = RE / 10
Hence RBB / (βdc+1) is neglected when compared RE.
Hence VBB = IERE+VBE
Hence VBE is neglected when compared to IERE
Hence IE = VBB / RE.
DESIGN OF R1 & R2:
Voltage drop across RE = VRE = 1V
Drop across VBE = 0.7V
Drop across the resistance R2 = VBE +VRE = VR2
VR2=1.7V ; R2 is assumed to be 10KΩ
VCCR2 / (R1 + R2 ) = VR2
10*12KΩ/(R1+10KΩ)=1.7V
R1=61KΩ

Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set VS=10mV using AFO.
3. Keeping the input voltage constant, vary the frequency from few 100Hz to 1MHz in regular steps
& note down the correspondingly output voltage.
4. Plot the graph: gain Vs frequency.
5. Calculate bandwidth from the graph.

Result:
The class-A amplifier is designed, constructed and the output waveform is observed. The Maximum power
output and the efficiency are determined.