1644 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.

5, MAY 2010

Zero-Voltage and Zero-Current-Switching PWM

Combined Three-Level DC/DC Converter
Fuxin Liu, Member, IEEE, Jiajia Yan, and Xinbo Ruan, Senior Member, IEEE

Abstract—This paper proposes a zero-voltage and zero- the converter should be designed to output the required voltage
current-switching (ZVZCS) PWM combined three-level (TL) at low line, but the duty cycle will be very small at high line,
dc/dc converter, which is a combination of a ZVZCS PWM TL resulting in a low efficiency.
converter with a ZVZCS PWM full-bridge converter. The pro-
posed converter has the following advantages: all power switches To reduce the filter requirement, various converters have been
suffer only half of the input voltage; the voltage across the output proposed in [8]–[12]. The secondary rectified voltage is a TL
filter is very close to the output voltage, which can reduce the waveform having a low high-frequency content across the filter
output filter inductance significantly; and the voltage stress of the inductance. However, the switches sustain the whole input volt-
rectifier diodes is reduced too, so that the converter is very suitable age, which is not suitable for high input voltage applications.
for high input voltage and wide input voltage range applications.
The converter also can achieve zero-voltage-switching for the Liu and Ruan proposed a ZVS PWM combined TL dc/dc
leading switches and ZCS for the lagging switches in a wide load converter [13], which is composed of HB TL and full-bridge
range to achieve higher efficiency. The design considerations and sections. The switches sustain only half of the input voltage;
procedures are presented in this paper. The operation principle therefore, it is suitable for high input voltage applications.
and characteristics of the proposed converter are analyzed and The converter has two operation modes: TL and two-level
verified on a 400–800-V input and 54-V/20-A output prototype.
modes. In each mode, the rectified voltage is always close
Index Terms—Combined three-level (TL) dc/dc converter, phase to the output voltage; therefore, the high-frequency content is
shift, zero-current-switching (ZCS), zero-voltage-switching (ZVS). reduced, and a small filter inductance can be obtained. As a
result, the converter can be adopted to wide input voltage range
I. I NTRODUCTION applications. Meanwhile, all the switches can achieve ZVS in
the same manner as phase-shifted full-bridge converter.

H ALF-BRIDGE (HB) three-level (TL) dc/dc converters

are very suited for high input voltage applications be-
cause the switches sustain only half of the input voltage.
One drawback of the ZVS PWM combined TL dc/dc con-
verter is that the two lagging switches experience ZVS difficulty
because only the energy stored in the leakage inductances of
Various soft-switching HB TL dc/dc converters have been the transformers is used to achieve ZVS. In order to achieve a
proposed in recent years, which can be classified into two types: complete ZVS of switches down to light load, we can increase
zero-voltage-switching (ZVS) PWM TL converter [1]–[5] and the leakage inductances of the transformers or add an external
zero-voltage and zero-current-switching (ZVZCS) PWM TL resonant inductance in series with the primary sides of the
converter [6], [7]. transformers. However, the increased leakage inductance and/or
The HB TL converters are essentially two-level converters the resonant inductance will cause a duty cycle loss at the
because the voltage across the output filter is a two-level secondary rectified voltage and will result in severe parasitic
waveform. In some applications such as railway power supply oscillation on the secondary side of the transformers, which will
systems or ship electric power distribution systems, the input reduce the overall conversion efficiency indirectly.
voltage is not only very high but also variable in a wide range. The other disadvantage of the ZVS PWM combined TL con-
The output filter inductance of the HB TL converters should verter is that, in the two-level mode when the primary currents
be large enough to reduce the output current ripple, resulting decrease across zero and increase in the negative direction,
in low power density and slow transient response. Meanwhile, the body diode reverse recovery of the leading switches will
occur due to their slow switching speed, and it will result in a
reverse recovery loss, which degrades severely the conversion
Manuscript received March 14, 2007; revised July 9, 2007. First published
September 22, 2009; current version published April 14, 2010. This work was
efficiency of the converter in the two-level mode.
supported by the Natural Science Foundation of China under Award 50177013 In order to solve the problems, the lagging switches can be
and the Natural Science Foundation of Jiangsu Province, China, under Award realized ZCS, and they can adopt an insulated gate bipolar tran-
BK2003419. An earlier version of this paper was presented at the IEEE Power
Electronics Specialists Conference, Jeju, Korea, June 18–22, 2006.
sistor (IGBT) instead of MOSFET. In the meanwhile, the ZVS
F. Liu is with the College of Automation Engineering, Nanjing University mechanism of the leading switches remains; thus, the combined
of Aeronautics and Astronautics, Nanjing 210016, China (e-mail: liufuxin@ TL dc/dc converter will be turned into a combination of a
nuaa.edu.cn).
J. Yan is with Bel Power Company, Ltd., Hangzhou 310053, China (e-mail: ZVZCS PWM TL converter [6] and a ZVZCS PWM full-bridge
[email protected]). converter [14], as shown in Fig. 1. The proposed dc/dc converter
X. Ruan is with the College of Electrical and Electronic Engineering, can achieve ZVS for the leading switches relying on the output
Huazhong University of Science and Technology, Wuhan 430074, China
(e-mail: [email protected]). filter inductance in a wide load range and realize ZCS for the
Digital Object Identifier 10.1109/TIE.2009.2031950 lagging switches over a wide load and line range too; thus, the

0278-0046/$26.00 © 2010 IEEE

LIU et al.: ZERO-VOLTAGE AND ZERO-CURRENT-SWITCHING PWM COMBINED THREE-LEVEL DC/DC CONVERTER 1645

Fig. 1. ZVZCS PWM combined TL dc/dc converter.

efficiency over the line range can be increased. This converter When the input voltage increases, or during start up, over-
maintains all advantages of the ZVS PWM combined TL dc/dc load, or short circuit, the shift phase of the full-bridge section
converter, including the reduced filter inductance requirement approaches to 180◦ ; therefore, this section operates with zero
and the lower voltage stress on the rectifier diodes. Further- pulsewidth and does not contribute to the output. The shift
more, the body diode reverse recovery of MOSFETs is also phase of the TL section begins to be regulated to maintain the
eliminated due to ZCS in the two-level mode. The operation output voltage, Q1 and Q4 are leading switches, and Q2 and Q3
analysis, characteristics, and design considerations of the pro- are lagging switches. In this situation, the rectified voltage has
posed converter are illustrated in this paper. The performance two levels: the middle and 0 levels, as shown in Fig. 2(b), and
of the converter was experimentally verified by a 54-V/20-A the converter operates in the two-level mode.
prototype operating at 100 kHz and with a 400–800-V input. Whether in TL or two-level modes, vrect is always close to
its average value (the output voltage); therefore, it has a lower
high-frequency content, and the output filter inductance can be
II. O PERATION P RINCIPLE
reduced significantly.
As shown in Fig. 1, the proposed converter is a combination The operation principles of the two modes are analyzed in
of two sections: ZVZCS PWM TL and ZVZCS PWM full- this section. For convenience to analysis, it is assumed that all
bridge sections. The ZVZCS PWM TL section is comprised the switches and diodes are ideal, the flying capacitor Css is
of the switches Q1 −Q4 , the series diodes D2 and D3 , the large enough to be treated as a voltage source with a value of
freewheeling diodes Df 1 and Df 2 , the flying capacitor Css , Vin /2, and the output filter inductance Lf is large enough to be
and the transformer T1 . The ZVZCS PWM full-bridge section considered as a constant current source of Io , where Io is the
is comprised of the switches Q2 , Q3 , Q5 , and Q6 ; the diodes output current.
D2 and D3 ; and the transformer T2 . Cd1 and Cd2 form a
capacitive divider that splits the input voltage in half (i.e.,
VCd1 = VCd2 = Vin /2). Llk1 and Llk2 are the primary intrinsic A. TL Mode
leakage inductances of T1 and T2 , respectively. Cb is the
Referring to the time diagram as shown in Fig. 2(a), the
blocking capacitor that makes the primary currents decay to
proposed converter has 14 operation stages during a switching
zero to achieve ZCS for Q2 and Q3 . Cb can be in series with
period in the TL mode. The corresponding equivalent circuits
T1 or T2 . In Fig. 1, Cb is in series with T1 . D2 and D3 are in
for all operation stages are shown in Fig. 3.
series with Q2 and Q3 , respectively, to make them conduct only
in the positive direction. The output of each section is added at 1) Stage 1 [t0 , t1 ] [refer to Fig. 3(a)]: From t0 , Q1 , Q2 , and
the secondary side and rectified and filtered to obtain the output Q6 conduct; vAB = vAC = Vin /2; DR1 conducts; and
voltage. DR2 is off. The primary current ip1 charges Cb , and the
Fig. 2 shows the key waveforms of the proposed converter. initial values of ip1 and ip2 at t0 are Ip01 = k1 Io and
When the input voltage is low, the shift phase between Q1 &Q4 Ip02 = k2 Io , respectively.
and Q2 &Q3 is set at a minimum value of δ to make the primary 2) Stage 2 [t1 , t2 ] [refer to Fig. 3(b)]: At t1 , Q6 is turned
currents reset and ensure ZCS for Q2 and Q3 . Q2 , Q3 , Q5 , and off, and ip2 charges C6 and discharges C5 . As C5 and C6
Q6 are phase-shift controlled to regulate the output voltage, and limit the rising rate of the voltage across Q6 , Q6 is zero-
Q5 and Q6 are switched leading to Q3 and Q2 , respectively. voltage turn off. During this stage, the current source Io
Therefore, Q5 and Q6 are called leading switches, and Q2 and is reflected to the primary sides of the transformers and in
Q3 are called lagging switches. As shown in Fig. 2(a), the series with the leakage inductances; therefore, ip1 and ip2
rectified voltage vrect has three levels: 1 level ((k1 + k2 )Vin /2), are keep at Ip01 and Ip02 . ip1 continues to charge Cb . The
the middle level (k1 Vin /2), and 0 level, where k1 and k2 are the voltage of C6 (vC6 ) rises linearly, and the voltage of C5
secondary to primary turn ratios of T1 and T2 , respectively. In (vC5 ) decays linearly. At t2 , vC6 rises to Vin /2, and vC5
this situation, the proposed converter operates in the TL mode. drops to zero, so that D5 conducts naturally.
1646 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010

Fig. 2. Key waveforms of the ZVZCS PWM combined TL dc/dc converter. (a) TL mode. (b) Two-level mode.

3) Stage 3 [t2 , t3 ] [refer to Fig. 3(c)]: D5 conducts and From (1)–(3), the following expressions can be
clamps the voltage across Q5 at zero; as a result, Q5 can obtained:
be zero-voltage turn on. vAB = Vin /2, vAC = 0, and ip1
k22 · Llk2 · Vcbp
continues to charge Cb . vP 1 = − (4)
Leq
4) Stage 4 [t3 , t4 ] [refer to Fig. 3(d)]: Q1 is turned off at
t3 , and ip1 charges C1 and discharges C4 via Css . As C1 k1 · k2 · Llk2 · Vcbp
vP 2 = (5)
and C4 limit the rising rate of the voltage across Q1 , Q1 Leq
is zero-voltage turn off. At t4 , vC1 rises to Vin /2, vC4 disec k1 · Vcbp
=− (6)
decays to zero, Df 1 conducts naturally, and vAB = 0. dt Leq
5) Stage 5 [t4 , t5 ] [refer to Fig. 3(e)]: As Df 1 is conducting,
the voltage of C4 is clamped to zero; therefore, Q4 is where Leq = k12 Llk1 + k22 Llk2 .
turned on at zero-voltage condition. The voltage across At t5 , isec transits from Io to zero, and ip1 and ip2
Cb (vcb ) is applied to the leakage inductances and primary decay to zero. According to (6), t45 can be given by the
windings, which forces ip1 and ip2 to reduce simulta- following:
neously. ip1 and ip2 cannot provide the output current; Leq · Io
t45 = . (7)
therefore, both the rectifier diodes conduct, shorting the k1 · Vcbp
series-connected secondary windings. The further equiv-
alent circuit corresponding to this stage is shown in Fig. 4, 6) Stage 6 [t5 , t6 ] [refer to Fig. 3(f)]: D2 blocks the reverse
where we have the following expressions: paths of ip1 and ip2 ; therefore, ip1 and ip2 are kept at
zero. As there is no current flowing through Q2 , Q2 can
be zero-current turn off during [t5 , t6 ]. Both the rectifier
dip1 k1 ·disec
vP 1 +Llk1 · +Vcbp = vP 1 +Llk1 · +Vcbp = 0 (1) diodes conduct and share the output current.
dt dt 7) Stage 7 [t6 , t7 ] [refer to Fig. 3(g)]: Q3 is turned-on at
dip2 k2 ·disec zero-current condition because the leakage inductances
vP 2 +Llk2 · = vP 2 +Llk2 · =0 (2)
dt dt limit the rising rate of the primary currents. The primary
currents begin to rise linearly in the negative direction and
vS1 +vS2 = k1 ·vP 1 +k2 ·vP 2 = 0 (3)
are not sufficient to power the load; therefore, both the
rectifier diodes continue conducting. At t7 , ip1 and ip2
where vP 1 , vP 2 , vS1 , and vS2 are the primary and sec- reach the reflected load current.
ondary voltages of T1 and T2 , respectively; isec is the 8) Stage 8 [t7 , t8 ] [refer to Fig. 3(h)]: From t7 , the primary
secondary current; and Vcbp is the peak value of vcb . powers the load, and ip1 discharges Cb . DR1 turns off,
LIU et al.: ZERO-VOLTAGE AND ZERO-CURRENT-SWITCHING PWM COMBINED THREE-LEVEL DC/DC CONVERTER 1647

Fig. 3. Equivalent circuits in the TL mode. (a) [t0 , t1 ]. (b) [t1 , t2 ]. (c) [t2 , t3 ]. (d) [t3 , t4 ]. (e) [t4 , t5 ]. (f) [t5 , t6 ]. (g) [t6 , t7 ]. (h) [t7 , t8 ].

B. Two-Level Mode
As shown in Fig. 2(b), the proposed converter has ten oper-
ation stages during a switching period in the two-level mode;
among which, [t0 , t3 ] is the same as [t2 , t5 ] in the TL mode.
In the following, only the operation during [t3 , t6 ] is analyzed.
Fig. 5 shows the equivalent circuits of [t3 , t6 ].
1) Stage 4 [t3 , t4 ] [refer to Fig. 5(a)]: At t3 , ip1 and ip2
drop to zero, and D2 prevents ip1 and ip2 from flowing
in the reverse direction; therefore, ip1 and ip2 are kept at
zero. Both the rectifier diodes conduct and share the load
current. During this interval, Q2 and Q5 can be turned
Fig. 4. Further equivalent circuit during [t4 , t5 ] in the TL mode. off with zero-current, and no body diode reverse recovery
occurs.
DR2 carries the entire load current, and the converter 2) Stage 5 [t4 , t5 ] [refer to Fig. 5(b)]: Turn on Q3 and Q6
operates in the second half period, which is similar to the at t4 , vAB = −Vin /2, and vAC = 0. The rectifier diodes
first half period as described previously. continue conducting and shorting the series secondary
1648 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010

The voltages across Q2 and Q3 are

Vin Vin k 2 · Llk1 · Vcbp
VQ3 = + vAB = + 1 . (10)
2 2 Leq
k1 · k2 · Llk2 · Vcbp
VQ2 = − vAC = − . (11)
Leq
From the earlier expressions, it can be understood that the
voltage stress of Q2 and Q3 will be slightly higher than Vin /2,
and Q2 and Q3 will sustain the negative voltage, which needs
diodes in series with them to avoid reverse breakdown.

B. Conditions to Achieve Soft Switching

1) ZVS for Q1 and Q4 : As analyzed previously, during the
switching transition of Q1 and Q4 in the TL and two-level
modes, the output filter inductance is always reflected to the
primary side and in series with the leakage inductances, and the
energy stored in these inductances is large enough to ensure Q1
and Q4 to achieve ZVS even at light load.
2) ZCS for Q2 and Q3 : To achieve ZCS for Q2 and Q3 ,
the primary currents should decay to zero before Q2 or Q3
turns off.
In the TL mode, referring to Fig. 2(a), the time t45 is relative
to Vcbp under different loads according to (7). As the leakage
inductances are small, t67 is very short to be neglected. If Cb is
assumed to be large enough so that vCb is kept constant during
[t4 , t5 ], therefore, vCb varies from −Vcbp to Vcbp during Ts /2 −
Treset
 
k1 Io Ts
Vcbp = − Treset (12)
2Cb 2
Fig. 5. Equivalent circuits in the two-level mode. (a) [t3 , t4 ]. (b) [t4 , t5 ].
(c) [t5 , t6 ]. where Treset is the preset resetting time for primary currents,
which includes t45 and TZCS . TZCS is the time for most of
windings of transformers. ip1 and ip2 increase in the minority carriers to be combined for IGBTs used as Q2 and
negative direction and arrive at the reflected load current Q3 , and Ts is the switching period.
at t5 . Substituting (12) into (7) yields
3) Stage 6 [t5 , t6 ] [refer to Fig. 5(c)]: From t5 , the primary
currents power the load, DR1 turns off and DR2 carries 2Leq · Cb
t45 = . (13)
all the output current, the proposed converter operates in k12 · (Ts /2 − Treset )
the second half period, which is similar to the first half Equation (13) indicates that t45 is independent of load current.
period. If (14) is satisfied, the primary currents will be ensured to be
reset, and ZCS will be achieved for Q2 and Q3 in the full-load
and the line range
III. T HEORETICAL A NALYSIS OF THE
P ROPOSED C ONVERTER t45 + TZCS ≤ Treset . (14)
A. Power Switches As shown in Fig. 2(a), t34 is so short that it can be neglected;
According to the operation principle of the combined TL therefore, Treset is the sum of Tδ and Td , where Tδ is the
dc/dc converter, we can know that Q1 , Q4 , Q5 , and Q6 sustain time corresponding to the minimal shift phase δ between the
only half of the input voltage. drive signals of Q1 &Q4 and Q2 &Q3 and Td is the delay time
During [t5 , t6 ] in TL mode, ip1 = ip2 = 0, vB = Vin /2, between the drive signals of the complementary switches. In
vA = Vcbp + vP 1 + Vin /2, and vC = −vP 2 + Vcbp + vP 1 + practical design, Treset is set at a fixed value of around 0.05Ts .
Vin /2. Therefore Similarly, in the two-level mode, referring to Fig. 2(b), time
t23 , during which the primary currents decay to zero, can be
k12 · Llk1 · Vcbp derived as
vAB = vA − vB = Vcbp + vP 1 = . (8)
Leq 2Leq · Cb 2Leq · Cb 4Leq · Cb
t23 = = 2 = 2 (15)
k1 · k2 · Llk2 · Vcbp k1 · t02
2 k1 · DT · Ts /2 k1 · DT · Ts
vAC = vA − vC = vP 2 = . (9)
Leq where DT = Vo /(k1 · Vin /2).
LIU et al.: ZERO-VOLTAGE AND ZERO-CURRENT-SWITCHING PWM COMBINED THREE-LEVEL DC/DC CONVERTER 1649

Fig. 6. Rectified voltage waveforms. (a) TL mode, Vo ≥ k1 Vin /2. (b) TL mode, Vo < k1 Vin /2. (c) Two-level mode.

From (15), it can be seen that t23 is independent with load 3) Voltage stress of Q2 and Q3 and series diodes. Referring
current and increases along with the input voltage due to the to (10)–(12), Cb should be selected as large as possible to
reduced DT , as shown in Fig. 2(b). The realization of ZCS for reduce the voltage stress of Q2 and Q3 and series diodes.
Q2 and Q3 in overall load range in the two-level mode depends In the prototype, there will be a tradeoff in determining
on the following constraint: the value of Cb .

Dsum = D23 + DZCS + DT ≤ 1 (16)

D. VA Ratings of the Transformers
where D23 = t23 /((1/2)Ts ) and DZCS = TZCS /((1/2)Ts ). As previously explained, in the two-level mode, T2 does
3) ZVS for Q5 and Q6 : In the TL mode, during the switch- not contribute to the output, and only T1 transfers the whole
ing transition of Q5 and Q6 , Lf is reflected to the primary sides power. Therefore, T1 should be designed to be able to deliver
of the transformers, and the energy stored in Lf is large enough the whole power at maximum input voltage and full load;
to realize ZVS for Q5 and Q6 in a wide load range. then, the VA rating of T1 is approximately identical to that
In the two-level mode, prior to turning off of Q5 and Q6 , of the conventional dc/dc converters with single transformer at
the drain currents have already decayed to zero, as shown the same specifications. In the TL mode, as the input voltage
in Fig. 2(b); therefore, Q5 and Q6 are zero-current turn off. decreases, the contribution from T1 to the output drops, and
However, there is no current to charge or discharge the intrinsic T2 delivers the balance of the output power; therefore, T2 will
capacitors of Q5 and Q6 prior to their turn on; therefore, they be chosen to supply the partial output power right down to the
are capacitive turn on. minimum input voltage and full load. As a result, the total VA
rating of the two transformers in the proposed converter is a
little higher than that of the conventional dc/dc converters with
C. Blocking Capacitor single transformer.
The value of the blocking capacitor Cb should be designed
based on three considerations. IV. D ESIGN C ONSIDERATION FOR T URN R ATIOS
1) ZCS condition for Q2 and Q3 . Substituting (13) into (14) OF T RANSFORMERS
yields
The turn ratios should be designed to obtain the required
2Leq · Cb output voltage at low line. Fig. 6 shows the ideal secondary
+ TZCS ≤ Treset . (17) rectified voltage waveforms of the proposed converter.
k1 · (Ts /2 − Treset )
2
From Fig. 6(a), k1 and k2 should satisfy the following
To ensure that Q2 and Q3 realize ZCS over the whole expression:
load range, Cb must be satisfied with the following Vinmin
expression: (k1 · DTLmax + k2 · DHmax ) · = Vo (20)
2

Cb ≤ k12 · (Ts /2 − Treset ) · (Treset − TZCS )/2Leq . (18) where DTLmax = 1 − Treset /((1/2)Ts ) = 1 − (Tδ + Td )/
((1/2)Ts ), DHmax is the value at full load and the lowest input
2) Maximum duty cycle of the TL section (DTLmax ). In the voltage, and DH = TH /((1/2)Ts ).
proposed converter, Treset should be preset to realize ZCS The proposed converter has two freedoms (k1 and k2 ) which
for Q2 and Q3 , as shown in Fig. 2(a). DTLmax is given by provides possibilities of optimizing the performance of the
the following: converter. Under the precondition of (20), the specific value
of k1 and k2 will be designed according to two principles:
Treset 1) minimize the output filter inductance and 2) minimize the
DTLmax = 1 − . (19)
Ts /2 voltage stress on rectifier diodes.
According to Fig. 6, the output filter inductance Lf of the
In order to increase DTLmax , Cb should be reduced combined TL dc/dc converter is shown by (21a)–(21c) the
according to (13) and (19). bottom of the next page, where ΔiLf is the current ripple of Lf .
1650 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010

Vinmin = 400 V, Vinmax = 800 V, Vo = 54 V, Io = 20 A, Ts =

10 us, ΔiLf = 4 A, and DTLmax = 0.9. In the following, the
design procedures of k1 and k2 will be discussed.
1) Minimize Lf : According to the computational procedure
of minimizing Lf in [13], the maximal Lf in two modes
(TL mode, Vo ≥ k1 Vin /2, and two-level mode) Lf _max_3L and
Lf _max_2L should be equal; then, the turn ratios must satisfy
⎡ ⎤2
2V +k ·V ·(D −D ) 
⎣ o 1 inmin Hmax TLmax
− k1 ·DTLmax⎦
Vinmin ·DHmax

(2Vo −k1 ·Vinmin ·DTLmax )·(k1 ·Vinmax −2Vo )

= . (23)
k1 ·Vinmin ·Vinmax ·DHmax
Once k1 is calculated, k2 can be calculated according to (20);
therefore, a minimal Lf can be obtained, as shown in Fig. 7
[curve (a)]. However, the VDR in such case is shown in Fig. 8
[curve (a)], where the maximal VDR in the TL mode is higher
Fig. 7. Curves of the output filter inductance versus the input voltage.
than that in the two-level mode.
2) Minimize VDR : Similar to the calculation method of min-
imizing VDR in [13], the turn ratios should satisfy
2Vo · (DHmax − DTLmax )
k12 − k1 ·
Vinmax · DHmax · DTLmax
4Vo2
− = 0. (24)
Vinmax · Vinmin · DHmax · DTLmax
Once k1 is calculated, k2 can be solved according to (20),
and then, a minimal VDR can be achieved, as shown in Fig. 8
[curve (b)]. Curve (b) in Fig. 7 shows the value of Lf when the
turn ratios are designed to minimize VDR , where the maximal
Lf in the two-level mode is larger than that in the TL mode.
From Figs. 7 and 8, it can be known that Lf and VDR cannot
obtain minimal values simultaneously whatever the turn ratios
may be and that the turn ratios should be determined depending
on the specific requirement. In addition, it should be noted that
the imprecise turn ratios will have an effect on the boundary
Fig. 8. Curves of the voltage stress on the rectifier diodes versus the input input voltage between two modes and subsequently affect the
voltage. output current ripple and VDR , but the influence is so slight that
it can be neglected in a practical design.
With a full-wave output rectifier, the voltage stress on the
rectifier diodes is
 V. D ESIGN P ROCEDURE AND E XAMPLE
(k1 + k2 ) · Vin (TL mode) (22a)
VDR =
k1 · Vin (two-level mode). (22b) This section illustrates a simplified design procedure and
example with the input data given in Section IV.
According to (20)–(22), it can be known that Lf and VDR In order to achieve ZCS for Q2 and Q3 and increase
are the functions of k1 , k2 , and Vin . Figs. 7 and 8 show Lf DTLmax as large as possible, the preset resetting time is de-
and VDR versus input voltage for different choices of turn signed as 0.05Ts (i.e., Treset = 0.05 × Ts = 500 ns), so that
ratios, respectively, where the specifications are the following: DTLmax = 1 − Treset /(Ts /2) = 0.9. The delay time between

⎧ V    
⎪ (k1 +k2 )· 2in −Vo
·
⎪ k2 Vin − · DTLmax · TL mode, Vo ≥
2Vo k1 Ts k1 Vin
⎪ (21a)
⎨ Δi Lf k2 2
 2

Vo
Lf = ΔiLf · (1 − DTLmax ) · T2s TL mode, Vo < k1 Vin
(21b)
⎪
⎪  2V  2
⎪
⎩ Vo · 1− k1 Voin · Ts
ΔiLf 2 (two-level mode) (21c)
LIU et al.: ZERO-VOLTAGE AND ZERO-CURRENT-SWITCHING PWM COMBINED THREE-LEVEL DC/DC CONVERTER 1651

the complementary switches is td = 300 ns; therefore, the time

corresponding to the minimum shift phase δ is Tδ = 500 −
300 ns = 200 ns.
DHmax should be chosen as large as possible to minimize
the turn ratios and subsequently reduce the conduction losses in
the primary side. DHmax is, however, limited by the maximum
duty cycle of the ZVZCS PWM TL section (DTLmax ), and it
cannot surpass the value of DTLmax . Let DHmax = 0.8 at the
lowest input voltage; then, the relationship between k1 and k2
is obtained from (20)

k2 = 0.338 − 1.125k1 . (25)

The specific values of k1 and k2 are designed to minimize

Lf to achieve higher power density and better dynamic per-
formance. From (23) and (25), we can obtain k1 = 0.169 and
k2 = 0.147. According to (21), Lf = 13.62 μH.
Substituting k1 and k2 into (22), the maximum VDR in the
two modes is 224.4 and 135.2 V, respectively; therefore, the Fig. 9. D23 , DT , and Dsum as functions of the input voltage in the two-level
mode.
voltage stress of the rectifier diodes is 224.4 V.
The leakage inductances Llk1 and Llk2 of the two trans-
formers measured at 100 kHz are 2.6 and 3 μH, respectively;
therefore, Leq = 0.139 μH. Referring to the datasheet of the
chosen IGBT (IXGH40N60C2D1) for Q2 and Q3 , the current
tail time is Ttail = TZCS = 130 ns. According to (18), Cb ≤
0.171 μF. In actual prototype, Cb is selected as 0.1 μF and is
inserted into the ZVZCS PWM TL section.
In the two-level mode, the peak value of vcb (Vcbp ) is
given by

k1 Io k1 Io Ts Io Vo Ts
Vcbp = · t57 = · DT · = . (26)
2Cb 2Cb 2 2Cb Vin

Therefore, at full load and maximum input voltage, Vcbp is

67.5 V. Then, the voltage stresses of IGBTs and series diodes
are VIGBT = 436 V and VD(series) = 40.8 V, respectively,
according to (10) and (11).
With the parameters calculated earlier, it is indicated that
IGBTs can realize ZCS over a wide load range in TL mode
Fig. 10. Minimum load current to achieve ZVS for the switches versus the
according to (14), (17), and (18). Meanwhile, it is necessary input voltage.
to verify that whether ZCS for IGBTs can be achieved in the
two-level mode, and the boundary condition is given by (16).
According to the calculation method in [13], the boundary input In order to ensure ZVS for Q1 and Q4 , the intrinsic capacitor
voltage between the TL and two-level modes is Vin,bound = of the incoming switch should be fully discharged by ip1 during
710.1 V. the delay time. The ZVS condition will be lost if the load
D23 , DT , and Dsum as the functions of the input voltage in current is below Io_min_Q1(Q4) , which is expressed by
the two-level mode are shown in Fig. 9. As shown, within the Vin · Co
input voltage limit of the two-level mode, Dsum is always less Io_min_Q1 (Q4 ) = . (28)
td · k1
than one, which means that the ZCS for IGBTs can be realized
over a wide load range in the two-level mode. Io_min_Q1(Q4) as the function of the input voltage is shown
The chosen MOSFET (SPW20N60S5) to meet the voltage in Fig. 10, from which we can see that Q1 and Q4 can realize
and current requirements has an intrinsic capacitor Coss = ZVS when the output current is 4.35 A (21.7% of the full load)
1170 pF at Vds = 25 V. and 6.15 A (30.8% of the full load) at the lowest and highest
The value of the effective intrinsic capacitance Co is Coss input voltages, respectively.
multiplied by a factor of 4/3 [13], i.e., As analyzed earlier, when the converter transits into the two-
 level mode, the ZVS condition for Q5 and Q6 is lost. While
4 −12 25 in the TL mode, the intrinsic capacitor of the incoming switch
Co = × 1170 × 10 × . (27)
3 Vin /2 should be fully discharged by ip2 during the delay time to
1652 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010

Fig. 11. Experimental waveforms at full load. (a) TL mode. (b) Two-level mode.

Fig. 12. vGS (vGE ), vDS (vCE ), and iD (iC ) of (a) Q1 (Io = 5.5 A), (b) Q2 (Io = 2.5 A), and (c) Q5 (Io = 5.5 A) at Vin = 400 V.

provide ZVS for Q5 and Q6 . Therefore, the minimum load waveform due to the voltages of the two transformers added
current needed is given by at the secondary side. Fig. 11(b) shows that, in the two-level
mode, the pulsewidth of the full-bridge section decreases to
Vin · Co
Io_min_Q5 (Q6 ) = . (29) zero; therefore, vrect is a two-level voltage waveform.
td · k2 Fig. 12 shows the gate drive signal vGS (vGE ), the voltage
Io_min_Q5(Q6) as a function of the input voltage is also across the drain (collector) and source (emitter) vDS (vCE ),
shown in Fig. 10; it is illustrated that Q5 and Q6 can achieve and the drain (collector) current iD (iC ) of Q1 , Q2 , and Q5 ,
ZVS when the output current is 5 A (25% of the full load) at respectively, at light load and Vin = 400 V. It can be seen
the lowest input voltage, and the dotted line indicates that the that the ZVS turn on for MOSFETs is achieved while the
ZVS condition for Q5 and Q6 in the two-level mode is lost. antiparallel diode is conducting before the MOSFET is turned
on. The IGBTs are turned off with complete ZCS since the
current through it is zero before turning off. There is no IGBT
VI. E XPERIMENTAL R ESULTS
tail current due to ZCS.
The performance of the proposed dc/dc converter is veri- Fig. 13 shows the experimental waveforms at light load and
fied by a 1080-W (54-V/20-A) prototype circuit operating at Vin = 800 V, where the converter operates in the two-level
100 kHz from a 400–800-V input. The parameters of the pro- mode. As shown in Fig. 13(a) and (b), Q1 and Q2 can still
totype are as follows: MOSFET, SPW20N60S5 (21 A/650 V); realize ZVS and ZCS. However, as shown in Fig. 13(c), before
IGBT, IXGH40N60C2D1 (75 A/600 V); series diode, DSS16- Q5 turns off, ip2 has already decreased to zero; therefore, Q5
01A (16 A/100 V); freewheeling diode, DSEI30-06A (30 A/ can realize zero-current turn off, and there is a current spike
600 V); rectifier diode, DSEP30-03A (30 A/300 V); turn ra- resulted by charging its own output capacitance when Q6 is
tios of transformers, k1 = 0.169 and k2 = 0.147; output filter turned on. The experimental results are in substantial agreement
inductance, Lf = 13.6 μH; blocking capacitor, Cb = 0.1 μF; with the theoretical analysis in Section V.
and switching frequency, fs = 100 kHz. Fig. 14(a) shows the overall efficiency of ZVZCS PWM
Fig. 11 shows the experimental waveforms of ip1 , vAB , vAC , combined TL converter under different load currents with an
and vrect at full load in the TL and two-level modes. From input voltage of 400 and 800 V; the ZVS PWM combined TL
Fig. 11(a), it can be seen that, in the TL mode, vrect is a TL converter is also included for comparison. Fig. 14(b) shows the
LIU et al.: ZERO-VOLTAGE AND ZERO-CURRENT-SWITCHING PWM COMBINED THREE-LEVEL DC/DC CONVERTER 1653

Fig. 13. vGS (vGE ), vDS (vCE ), and iD (iC ) of (a) Q1 (Io = 7 A), (b) Q2 (Io = 2.5 A), and (c) Q5 (Io = 2.5 A) at Vin = 800 V.

Fig. 14. Conversion efficiency. (a) Efficiency at different output currents under the lowest and highest input voltages. (b) Efficiency at full load under different
input voltages.

overall efficiency at full load under different input voltages. Furthermore, with the reduced output filter inductance, the
As shown in Fig. 14(a), the efficiency of the ZVZCS type converter has potentially high power density and rapid dynamic
is relatively higher under full load range variations, owing to response. It is quite suitable in high power and high input
ZVS and ZCS realization for the switches and the elimination voltage with wide range applications.
of the body diode reverse recovery loss. As the load current In addition, it should be pointed out that, as the total VA
increases in the TL mode, the additional conduction losses of rating of the transformers in the proposed converter is higher
series diodes increases, which reduce the efficiency difference than that of the dc/dc converter with single transformer, some
between ZVZCS and ZVS types until the two efficiency curves optimization schemes such as magnetic integration technique
intersect at full load. In Fig. 14(b), the efficiency of the ZVZCS for the transformers should be investigated and employed in the
type is lower than the ZVS type in the TL mode due to the future to achieve a higher power density.
conduction loss of the series diodes and is higher in the two-
level mode because there is no body diode reverse recovery loss.
R EFERENCES
[1] J. R. Pinheiro and I. Barbi, “The three-level ZVS PWM converter—A new
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[5] K. Jin, X. Ruan, and F. Liu, “Improved voltage clamping scheme for ZVS Jiajia Yan was born in Henan, China, in 1983.
PWM three-level converter,” IEEE Power Electron. Lett., vol. 3, no. 1, She received the B.S. and M.S. degrees in electrical
pp. 14–18, Mar. 2005. engineering from Nanjing University of Aeronautics
[6] X. Ruan, L. Zhou, and Y. Yan, “Soft-switching PWM three-level con- and Astronautics, Nanjing, China, in 2005 and 2008,
verters,” IEEE Trans. Power Electron., vol. 16, no. 5, pp. 612–622, respectively.
Sep. 2001. She is currently an Engineer with Bel Power
[7] F. Canales, P. M. Barbosa, and F. C. Lee, “A zero-voltage and zero-current Company, Ltd., Hangzhou, China. Her main research
switching three-level DC/DC converter,” IEEE Trans. Power Electron., interests include soft-switching dc/dc converters and
vol. 17, no. 6, pp. 898–904, Nov. 2002. drivers for ultrasonic motors.
[8] R. Ayyanar and N. Mohan, “Novel soft-switching DC–DC converter with
full ZVS-range and reduced filter requirement—Part I: Regulated-output
applications,” IEEE Trans. Power Electron., vol. 16, no. 2, pp. 184–192,
Mar. 2001.
[9] R. Ayyanar and N. Mohan, “Novel soft-switching DC–DC converter with
full ZVS-range and reduced filter requirement—Part II: Constant-input,
variable-output applications,” IEEE Trans. Power Electron., vol. 16, no. 2, Xinbo Ruan (M’97–SM’02) was born in Hubei
pp. 193–200, Mar. 2001. Province, China, in 1970. He received the B.S.
[10] X. Ruan, Z. Chen, and W. Chen, “Zero-voltage-switching PWM hybrid and Ph.D. degrees in electrical engineering from
full-bridge three-level converter,” IEEE Trans. Power Electron., vol. 20, Nanjing University of Aeronautics and Astronau-
no. 2, pp. 395–404, Mar. 2005. tics (NUAA), Nanjing, China, in 1991 and 1996,
[11] X. Ruan and B. Li, “Zero-voltage and zero-current-switching PWM hy- respectively.
brid full-bridge three-level converter,” IEEE Trans. Ind. Electron., vol. 52, In 1996, he joined the Faculty of Electrical En-
no. 1, pp. 213–220, Feb. 2005. gineering Teaching and Research Division, NUAA,
[12] W. Song and B. Lehman, “Dual-bridge DC–DC converter: A new topol- and became a Professor in 2002 in the College of
ogy characterized with no deadtime operation,” IEEE Trans. Power Automation Engineering, NUAA, where he has been
Electron., vol. 19, no. 1, pp. 94–103, Jan. 2004. engaged in teaching and research in the field of
[13] F. Liu and X. Ruan, “ZVS combined three-level converter—A topol- power electronics. From August to October 2007, he was a Research Fellow
ogy suitable for high input voltage with wide range applications,” IEEE in the Department of Electronics and Information Engineering, The Hong
Trans. Ind. Electron., vol. 54, no. 2, pp. 1061–1072, Apr. 2007. Kong Polytechnic University, Kowloon, Hong Kong. Since March 2008, he
[14] X. Ruan and Y. Yan, “A novel zero-voltage and zero-current-switching has been with the College of Electrical and Electronic Engineering, Huazhong
PWM full-bridge converter using two diodes in series with the lagging University of Science and Technology, Wuhan, China. His main research in-
leg,” IEEE Trans. Ind. Electron., vol. 48, no. 4, pp. 777–785, Aug. 2001. terests include soft-switching dc/dc converters, soft-switching inverters, power-
factor-correction converters, modeling the converters, power electronics system
integration, and renewable energy generation systems. He has published over
Fuxin Liu (S’04–M’09) was born in Heilongjiang 100 technical papers in journals and conference proceedings and also published
Province, China, in 1979. He received the B.S., M.S., three books.
and Ph.D. degrees in electrical engineering from Since 2005, Dr. Ruan has served as Vice President of the China Power
Nanjing University of Aeronautics and Astronautics Supply Society, and since 2008, he has been a Member of the Technical
(NUAA), Nanjing, China, in 2001, 2004, and 2007, Committee on Renewable Energy Systems in the IEEE Industrial Electronics
respectively. Society. He is a Senior Member of the IEEE Power Electronics Society and
In 2007, he joined the Faculty of the College the IEEE Industrial Electronics Society. He was awarded the Delta Scholar
of Automation Engineering, NUAA, where he is by the Delta Environment and Education Fund, in 2003, and was awarded
currently an Associate Professor. His main research the Special Appointed Professor of the Chang Jiang Scholars Program by the
interests include soft-switching dc/dc converters, Ministry of Education, China, in 2007. He is a Guest Professor at Beijing
electric vehicle power systems, and renewable en- Jiaotong University, Beijing, China, and at Hefei University of Technology,
ergy generation systems. Hefei, China.