Verilog codes
1)FULL ADDER
—>Module full_adder
(
Input a,
Input b,
Input cin,
Output sum,
Output cout
);
assign sum = a^b^cin;
assign cout = (a & b) | (b & cin) | (a & cin);
end module.
2)FULL SUBTRACTOR
—>Module full_subtractor
(
Input a,
Input b,
Input bin,
Output diff,
Output bout
);
assign diff = a^b^bin;
assign bout = (~a & b) | (~(a^b) & bin);
end module.
3)HALF ADDER
—>module half _adder
(
Input a,
Input b,
Output sum,
Output carry
);
assign sum = a^b;
assign carry = a & b
end module.
4)HALF SUBTRACTOR
—>module half _adder
(
Input a,
Input b,
Output diff,
Output borrow
);
assign diff = a^b;
assign borrow = ~a & b
end module.
5)SR FLIP FLOP
—>module sr_flipflop
(
Input S,
Input R,
Input clk,
Output reg Q,
Output reg Qbar,
);
always @ (posedge clk) begin,
case ({S,R})
2’b00 : Q<=Q;
2’b01 : Q<=0;
2’b10 : Q<=1;
2’b11 : Q<=1’bx;
endcase
Qbar<=~Q;
end
endmodule
6)JK FLIP FLOP
—>module sr_flipflop
(
Input J,
Input K,
Input clk,
Output reg Q,
Output reg Qbar,
);
always @ (posedge clk) begin,
case ({J,K})
2’b00 : Q<=Q;
2’b01 : Q<=0;
2’b10 : Q<=1;
2’b11 : Q<=~Q;
endcase
Qbar<=~Q;
end
endmodule
7)T-FLIP FLOP
—>module t_flipflop
(
Input T,
Input clk,
Output reg Q,
Output reg Qbar,
);
always @ (posedge clk) begin,
If (T)
Q<=~Q;
else
Q<=Q;
Qbar<=~Q;
end
endmodule
8)D-FLIP FLOP
—>module d_flipflop
(
Input D,
Input clk,
Output reg Q,
Output reg Qbar,
);
always @ (posedge clk) begin,
Q <=D;
Qbar <=~D;
end
endmodule
