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Digital System Design Using FPGA

The document outlines a course on Advanced Digital System Design Using FPGA, aimed at providing training from campus to corporate environments. It includes learning objectives, prerequisites, and a detailed module breakdown covering topics such as Verilog constructs, combinational and sequential design, multiplexers, decoders, counters, and static timing analysis. Participants will gain hands-on experience with digital circuit design tools like Xilinx ISE or Vivado to implement their learning.

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obulaprasanth
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3 views4 pages

Digital System Design Using FPGA

The document outlines a course on Advanced Digital System Design Using FPGA, aimed at providing training from campus to corporate environments. It includes learning objectives, prerequisites, and a detailed module breakdown covering topics such as Verilog constructs, combinational and sequential design, multiplexers, decoders, counters, and static timing analysis. Participants will gain hands-on experience with digital circuit design tools like Xilinx ISE or Vivado to implement their learning.

Uploaded by

obulaprasanth
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Advanced Digital System Design Using FPGA

Course Learning Objectives


1. To provide campus-to-corporate training in Advanced Digital System Design Using
FPGA.
2. Participants gain a fundamental understanding of FPGA design. The workshop
may cover the basics of digital design and introduce participants FPGA and advc
Digital System Design. By the end of the workshop, participants should have a
good understanding of the underlying principles and techniques of Digital system
Design Using FPGA.
3. Participants learn how to use Digital Circuit design tools. The workshop may also
provide hands-on training on popular Digital Circuit design tools such as Xilinx
ISE or Xilinx Vivado. Participants will learn how to use this tool to implement
Advanced Digital System Design Using FPGA.

Pre-requisites
1. Fundamental knowledge of Digital System design.
2. Laptop or Desktop with 4GB RAM.
3. Basics in DLD.

Module 1: Verilog Constructs and Combinational Design-I


• Logic Gates and Synthesizable RTL
– NOT, OR, NOR, AND, NAND Logic
– Two Input XOR and XNOR Logic
• Tristate Logic
• Arithmetic Circuits
– Adder

Digital VLSI Using FPGA 1


– Subtractor
• Exercises
• Summary

Module 2: Verilog Constructs and Combinational Design-II


• Procedural Block always @***
• Multi-bit Adders and Subtractors
• Optimization of Resources
• Procedural Block initial
• Simulation Concepts: Basic Testbench
• Comparators and Parity Detectors
• Code Converters
• Let Us Think About the Design from Specifications
• Exercises
• Summary

Module 3: Multiplexers as Universal Logic


• Multiplexers
• Multiplexer as Universal logic
• Demux and its Realizations
• Let Us Design Combinational Logic Using Multiplexers
• Exercises
• Summary

Digital VLSI Using FPGA 2


Module 4: Decoders and Encoders
• Decoders
• Encoders
• Testbench
• Exercises
• Summary

Module 5: Event Queue and Design Guidelines


• Verilog Stratified Event Queue
• Design Guidelines
• Exercises
• Summary

Module 6: Basics of Sequential Design Using Verilog


• Sequential Logic
• Flip-Flops
• Exercises
• Summary

Module 7: Synchronous Counter and Asynchronous Counters


Design Using Synthesizable Constructs
• Synchronous Counters and Asynchronous Counters.
• Cascading Of Counters
• Implement the Digital Clock
• Exercises
• Summary

Digital VLSI Using FPGA 3


Module 8: RTL Design of Shift Registers
• Shift Register
• Exercises
• Summary

Module 9: Finite State Machines Using Verilog


• FSM Basics
• Melay and Moore’s State Machine’s
• FSM sequence detectors
• Exercises
• Summary

Module 10: Datapath And Controller


• Introduction Datapath and Controller.
• GCD Using Datapath and Controller
• Exercises
• Summary

Module 11: Static Timing Analysis


• Propagation Delay and Contamination Delay
• Setup Time And Hold Time
• timing Violations and Avoid
• Clock Skew,Clock Jitter and Slack
• Maximum Clock Operating Frequency
• Summary

Digital VLSI Using FPGA 4

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