SHRI H.H.J.B.

Polytechnic , Chandwad

CM3I Subject Code: 22320 Second Year CM

Digital Techniques
Prashant G. Aher (M.Tech CSE)
Lecturer,
Department of Computer Technology,
SHRI H.H.J.B. Polytechnic Chandwad
Specification table for Question Paper

Distribution of Theory Marks

Unit Teaching
Unit title
No. Hours
Total
R Level U Level A Level
Marks

I Number System and Codes 06 2 2 4 08

II Logic Gates and Logic Families 10 4 4 4 12

III Combinational Logic Circuits 16 4 6 8 18

IV Sequential Logic Circuits 16 4 6 8 18

V Data Converters and PLDs 16 4 4 6 14

Total 64 18 22 30 70

Legends: R=Remember, U=Understand, A = Apply

and above
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half and Full Subtractor, Gray
to Binary and Binary to Gray Code Converter (up to 4 bit).
3
 Unit III – Combinational Logic Circuits

 Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD

Adder
 Encoder/Decoder: Basics of Encoder, decoder, comparison,
(IC 7447) BCD to 7- Segment decoder/driver.

 Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX tree,
IC 74151 as MUX, DEMUX tree, DEMUX as decoder, IC
74155 as DEMUX

 Buffer: Tristate logic, Unidirectional and Bidirectional buffer

(IC 74LS244 and IC 74LS245)
4
 Unit-III
Combinational
Logic Circuits

5
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization
using NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half and Full Subtractor, Gray
to Binary and Binary to Gray Code Converter (up to 4 bit).
6
Standard Representation

Any logical expression can be expressed in

the following two forms:

 Sum of Product (SOP) Form

 Product of Sum (POS) Form

7
SOP Form

For Example, logical expression

given is;
Sum

Y  A . B  B .C  A.C
Produc
t

8
POS Form

For Example, logical expression

given is;
Produc
t

Y  ( A  B).(B  C).( A  C )
Sum

9
Standard or Canonical SOP & POS Forms

We can say that a logic expression is said to

be in the standard (or canonical) SOP or

POS form if each product term (for SOP)

and sum term (for POS) consists of all the

literals in their complemented or

uncomplemented form.
10
Standard SOP

Y  ABC  ABC  ABC

Each product
term consists all
the literals

11
Standard POS

Y  ( A  B  C).( A  B  C).( A  B  C )
Each sum
term
consists all
the literals

12
Examples

Sr.
Expression Type
No.

1 Y  AB  ABC  ABC Non Standard SOP

2 Y  AB  AB  AB Standard SOP

3 Y  ( A  B).( A  B).( A  B) Standard POS

4 Y  ( A  B).( A  B  C) Non Standard POS

13
Conversion of SOP form to Standard SOP

Procedure:
1. Write down all the terms.
2. If one or more variables are missing in any
product term, expand the term by
multiplying it with the sum of each one of
the missing variable and its complement .

3. Drop out the redundant terms

14
Example 1

Convert given expression into its standard SOP Y  AB  AC  BC

form
Y  AB  AC  BC

Missing literal is
A Missing literal is B

Missing literal is C

Y  AB.(C  C )  AC.(B  B)  BC.( A  A)

Term formed by ORing of

missing
literal & its complement
15
Example 1 Continue….

Y  AB.(C  C )  AC.(B  B)  BC.( A  A)

Y  ABC  ABC  ABC  ABC  ABC  ABC

Y  ABC  ABC  ABC  ABC  ABC  ABC

Y  ABC  ABC  ABC  ABC

Standard SOP form

Each product term consists all the
literals

16
Conversion of POS form to Standard POS

Procedure:
1. Write down all the terms.
2. If one or more variables are missing in any
sum term, expand the term by adding the
products of each one of the missing
variable and its complement .

3. Drop out the redundant terms

17
Example 2
Convert given expression into its standard SOP Y  ( A  B).( A  C).(B  C)
form
Y  ( A  B).( A  C).(B  C)

Missing literal is
A Missing literal is B

Missing literal is C

Y  ( A  B  CC).( A  C  BB).(B  C  AA)

Term formed by ANDing of

missing
literal & its complement
18
Example 2 Continue….

Y  ( A  B  CC).( A  C  BB).(B  C  AA)

Y  ( A  B  C)( A  B  C).( A  B  C)( A  B  C).(A  B  C)(A  B  C)

Y  ( A  B  C)( A  B  C)( A  B  C)( A  B  C)

Y  (A  B  C)(A  B  C)(A  B  C)(A  B  C)

Standard POS form

Each sum term consists all the
literals

19
 Concept of Minterm and Maxterm

 Minterm: Each indicisual term in the

standard SOP form is called as “Minterm”.
 Maxterm: Each indivisual term in the
standard POS form is called as “Maxterm”.
 The concept of minterm and maxterm
allows us to introduce a very convenient
shorthand notation to express logic
functions

20
Minterms & Maxterms for 3 variable/literal logic function

Variables Minterms Maxterms

A B C mi Mi

0 0 0 ABC  m0 ABC  M 0

0 0 1 A B C  m1 ABC  M 1

0 1 0 ABC  m2 ABC  M 2

0 1 1 ABC  m3 ABC  M 3

1 0 0 ABC  m4 ABC  M 4

1 0 1 ABC  m5 ABC  M 5

1 1 0 ABC  m6 ABC  M 6

1 1 1 ABC  m7 ABC  M 7
21
Minterms and maxterms
 Each minterm is represented by mi where
i=0,1,2,3,…….,2n-1

 Each maxterm is represented by Mi where

i=0,1,2,3,…….,2n-1

 If ‘n’ number of variables forms the function,

then
number of minterms or maxterms will be 2n
• i.e. for 3 variables function f(A,B,C), the number of
22
minterms or maxterms are 23=8
Minterms & Maxterms for 2 variable/literal logic function

Variables Minterms Maxterms

A B mi Mi

0 0 AB  m0 AB  M 0

0 1 AB  m1 AB  M 1

1 0 AB  m2 AB  M 2

1 1 AB  m3
AB  M 3

23
Representation of Logical expression using minterm

Y  ABC  ABC  ABC  ABC Logical

Expression
m7 m3 m4 m5 Correspondi
ng
minterms
Y  m7  m3  m 4  m5

Y  m(3, 4, 5, 7) O
R
Y  f ( A, B, C)  m(3, 4, 5, 7)

where denotes sum of

products
24
Representation of Logical expression using maxterm

Y  ( A  B  C).( A  B  C).( A  B  C ) Logical

Expression
M2 M0 M6 Correspondi
ng
maxterms
Y  M 2.M 0.M 6

Y  M (0, 2, 6) O
R
Y  f ( A, B, C)  M (0, 2, 6)

where  denotes product of sum

25
Conversion from SOP to POS & Vice versa

The relationship between the expressions

using minters and maxterms is
complementary.

We can exploit this complementary

relationship to write the expressions in
terms of maxterms if the expression in
terms of minterms is known and vice versa
26
Conversion from SOP to POS & Vice versa

For example, if a SOP expression for 4

variable is given by,
Y  m(0, 1, 3, 5, 6, 7 ,11, 12 ,1 5)

Then we can get complementary

expression using the equivalent POS the
relationship as follows,
Y   M (2, 4, 8 , 9, 10,13 , 1 4 )

27
Examples

1. Convert the given expression into standard

form

Y  A  BC  ABC
2. Convert the given expression into standard
form

Y  ( A  B).( A  C)

28
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables
(SOP & POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half and Full Subtractor, Gray
to Binary and Binary to Gray Code Converter (up to 4 bit).
29
Karnaugh Map (K-map)

In the algebraic method of simplification, we

need to write lengthy equations, find the
common terms, manipulate the expressions
etc., so it is time consuming work.

Thus “K-map” is another simplification

technique to reduce the Boolean equation.

30
Karnaugh Map (K-map)

It overcomes all the disadvantages of

algebraic simplification techniques.

The information contained in a truth table or

available in the SOP or POS form is

represented on K-map.

31
Karnaugh Map (K-map)

K-map Structure - 2 Variable

 A & B are variables or inputs

 0 & 1 are values of A & B

 2 variable k-map consists of 4 boxes i.e.

22=4 A
B 0 1

32
Karnaugh Map (K-map)

 K-map Structure - 2 Variable

Inside 4 boxes we have enter values of Y i.e.

output
A A A A
A A
B 0 1 B 0 1

AB AB m0 m1
B 0 B 0

B 1 AB AB B m2 m3

1 K-map & its associated

minterms

33
Karnaugh Map (K-map)

 Relationship between Truth Table & K-

map A A
A
B 0 1

A B Y 0 0 0
B
0 0 0 B 1 1 1

0 1 1

1 0 0
B B
B
A 0 1
1 1 1
A 0 0 1

A 1 0 1
34
Karnaugh Map (K-map)
 K-map Structure - 3 Variable
 A, B & C are variables or inputs
 3 variable k-map consists of 8 boxes i.e.
23=8
AB
A 0 1
C
BC
0
00
1
01
BC
00 01 11 10 11
A
10
0

35
Karnaugh Map (K-map)

 3 Variable K-map & its associated product

terms

36
Karnaugh Map (K-map)

 3 Variable K-map & its associated minterms

37
Karnaugh Map (K-map)
Karnaugh Map (K-map)

 4 Variable K-map and its associated product terms

39
Karnaugh Map (K-map)
 4 Variable K-map and its associated minterms

40
Representation of Standard SOP form expression on K-map

For example, SOP equation is given as

Y  ABC  ABC  ABC  ABC  ABC

 The given expression is in the standard SOP form.
 Each term represents a minterm.
 We have to enter ‘1’ in the boxes corresponding to each minterm as below
Simplification of K-map

Once we plot the logic function or truth table

on K-map, we have to use the grouping
technique for simplifying the logic function.

Grouping means the combining the terms in

adjacent cells.

The grouping of either 1’s or 0’s results in the

simplification of Boolean expression.
42
Simplification of K-map

If we group the adjacent 1’s then the result of

simplification is SOP form

If we group the adjacent 0’s then the result of

simplification is POS form

43
Grouping

 While grouping, we should group most number of 1’s.

 The grouping follows the binary rule i.e we can
group 1,2,4,8,16,32,…..…number of 1’s.

 We cannot group 3,5,7,………number of 1’s

 Pair: A group of two adjacent 1’s is called as Pair

 Quad: A group of four adjacent 1’s is called as Quad

 Octet: A group of eight adjacent 1’s is called as Octet

44
Grouping of Two Adjacent 1’s : Pair

A pair eliminates 1 variable

45
Grouping of Two Adjacent 1’s : Pair
Grouping of Two Adjacent 1’s : Pair
Possible Grouping of Four Adjacent 1’s : Quad
A Quad eliminates 2 variable

48
Possible Grouping of Four Adjacent 1’s : Quad
A Quad eliminates 2 variable

49
Possible Grouping of Four Adjacent 1’s : Quad
A Quad eliminates 2 variable

50
Possible Grouping of Four Adjacent 1’s : Quad
A Quad eliminates 2 variable
Possible Grouping of Eight Adjacent 1’s : Octet
A Octet eliminates 3 variable

52
Possible Grouping of Eight Adjacent 1’s : Octet

A Octet eliminates 3 variable

53
Rules for K-map simplification

1. Groups may not include any cell containing

a zero.

54
Rules for K-map simplification

2. Groups may be horizontal or vertical,

but may not be diagonal

55
Rules for K-map simplification

3. Groups must contain 1,2,4,8 or in general 2n cells

Rules for K-map simplification
4. Each group should be as large as possible

57
Rules for K-map simplification

5. Each cell containing a one must be in at least

one group
Rules for K-map simplification
6. Groups may be overlap

59
Rules for K-map simplification
7. Groups may wrap around the table. The
leftmost cell in a row may be grouped with
rightmost cell and the top cell in a column may
be grouped with bottom cell

60
Rules for K-map simplification
8. There should be as few groups as possible, as
long as this does not contradict any of the
previous rules.

61
Rules for K-map simplification
9. A pair eliminates one variable.

10. A Quad eliminates two variables.

11. A octet eliminates three variables

62
Example 1

For the given K-map write simplified Boolean

expression

63
Example 1 continue…..

64
Example 2
For the given K-map write simplified Boolean expression

65
Example 2 continue…..

66
Example 3

A logical expression in the standard SOP

form is as follows;

Y  ABC  ABC  ABC  ABC

Minimize it with using the K-map

technique

67
Example 3 continue……

68
Example 4

A logical expression representing a logic

circuit is;
Y  m(0,1, 2, 5,13,15)

Draw the K-map and find the minimized

logical expression

69
Example 4 continue…..

70
Example 5

Minimize the following Boolean expression

using K-map ;

f ( A, B, C, D)  m(1, 3, 5, 9,11,13)

71
Example 5 continue…..

72
Example 6

Minimize the following Boolean expression

using K-map ;

f ( A, B, C, D)  m(4, 5,8, 9,11,12,13,15)

73
Example 6 continue…..

74
Example 7

Minimize the following Boolean expression

using K-map ;

f 2( A, B, C, D)  m(0,1, 2, 3,11,12,14,15)

75
Example 7 continue…..

76
Example 8

Solve the following expression with K-

maps;
1. f 1( A, B, C)  m(0,1, 3, 4, 5)
2. f 2( A, B, C)  m(0,1, 2, 3, 6, 7)

77
Example 8 continue……

78
Example 9

Simplify ;

f ( A, B, C, D)  m(0,1, 4, 5, 7,8, 9,12,13,15)

79
Example 9 continue…..

80
Example 10

Solve the following expression with K-

maps;
1. f 1( A, B, C, D)  m(0,1, 3, 4, 5, 7)
2. f 2( A, B, C)  m(0,1, 3, 4, 5, 7)

81
Example 10 continue……

82
K-map for Product of Sum Form (POS
Expressions)

Karnaugh map can also be used for

Boolean expression in the Product of sum
form (POS).

The procedure for simplification of

expression by grouping of cells is also
similar
83
K-map for Product of Sum Form (POS Expressions)

 The letters with bars (NOT) represent 1 and

unbarred

letters represent 0 of Binary.

 A zero is put in the cell for which there is a term in

the Boolean expression

 Grouping is done for adjacent cells containing zeros.

84
Example 11

Simplify ;

f ( A, B, C, D)  M (0,1, 3, 5, 6, 7,10,14,15)

85
 Example 11 continue…..

f (A, B,C, D)  M (0,1,3,5, 6, 7,10,14,15)

Simplified Boolean expression

f  ( A  D)(B  C)( A  C  D)( A  B  C )
Example 12

Simplify
;

f ( A, B, C, D)  M (4, 6,10,12,13,15)

87
Example 12 continue…..

f (A, B,C, D)  M (4, 6,10,12,13,15)

Simplified Boolean expression

f  ( A  B  C  D)( A  B  D)( A  B  D)( A  B  C )
88
K-map and don’t care conditions

For SOP form we enter 1’s corresponding to

the combinations of input variables which
produce a high output and we enter 0’s in
the remaining cells of the K-map.
For POS form we enter 0’s corresponding to
the combinations of input variables which
produce a high output and we enter 1’s in
the remaining cells of the K-map.
89
K-map and don’t care conditions

But it is not always true that the cells not

containing 1’s (in SOP) will contain 0’s,
because some combinations of input
variable do not occur.

Also for some functions the outputs

corresponding to certain combinations of
input variables do not matter.

90
K-map and don’t care conditions

In such situations we have a freedom to

assume a 0 or 1 as output for each of these
combinations.
These conditions are known as the “Don’t
Care Conditions” and in the K-map it is
represented as ‘X’, in the corresponding cell.
The don’t care conditions may be assumed
to be 0 or 1 as per the need for
91
simplification
K-map and don’t care conditions - Example

Simplify ;

f ( A, B, C, D)  m(1, 3, 7,11,15)  d (0, 2, 5)

92
K-map and don’t care conditions - Example

93
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half Adder and Full Adder, Half and Full Subtractor,
Gray to Binary and Binary to Gray Code Converter (up to 4
bit). 94
 Half Adder

 Half adder is a combinational logic circuit with

two inputs and two outputs.
 It is a basic building block for addition of two
single bit numbers.

A Sum

Inputs Half Outputs

Adde
B r Carry

95
Half Adder

Truth Table for Half Adder

Input Output

A B Sum (S) Carry (C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

96
Half Adder
K-map for Sum Output:
A
A A
B 0 1
S  AB  AB
0 1
B 0
S  A B
B 1 1 0

K-map for Carry Output:

A
A A
B 0 1

B 0 0 0 C  AB

B 1 0 1

97
Half Adder

Logic
Diagram:
A
S  A B
B

C  AB

98
Half Adder
Logic Diagram using Basic
Gates:

A B

S  A B

C  AB

99
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half and Full Subtractor, Gray
to Binary and Binary to Gray Code Converter (up to 4 bit).
100
 Full Adder
Full adder is a combinational logic circuit with
three inputs and two outputs.

A Sum
Inputs
B Full Outputs
Adde
r Carry

Cin

101
Full Adder
Truth Table
Inputs Outputs
A B Cin Sum (S) Carry (C)
0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
102
Full Adder
K-map for Sum Output:

BC BC BC BC BC
A 00 0 11 10
1
S  ABC  ABC  ABC  ABC
A 0 0 1 0 1
S  ABC  ABC  ABC  ABC
A 1 1 0 1 0 S  C( AB  AB)  C( AB  AB)
Let AB  AB  X
ABC
ABC ABC
ABC  S  C( X )  C( X )
S  C X
Let X  A B
S  C  A B
103
Full Adder

K-map for Carry Output:

BC BC BC BC BC
A 00 0 11 10
1
A 0 0 0 1 0
C  AB  BC  AC
A 1 0 1 1 1

BC
AB
AC

104
Full Adder
Logic
Diagram:

A B C

S  A B C

C  AB  BC  AC

105
Full Adder using Half Adders

A S0 S1 Sum
HA1 HA2
B C0 C1

C
Carry

106
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half Subtractor and Full
Subtractor, Gray to Binary and Binary to Gray Code
Converter (up to 4 bit). 107
 Half Subtractor
Half subtractor is a combinational logic
circuit with two inputs and two outputs.

It is a basic building block for subtraction of

two single bit numbers.

A Difference

Inputs Half Outputs

Subtract
B or Borrow

108
Half Subtractor
Truth Table

Input Output

A B Difference (D) Borrow (B)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

109
Half Subtractor
K-map for Difference Output:
A
A A
B 0 1
D  AB  AB
0 1
B 0
D  A B
B 1 1 0

K-map for Borrow Output:

A
A A
B 0 1

0 1
B 0 B  AB
B 1 0 0

110
Half Subtractor
Logic
Diagram:

A
D  A B
B

B  AB

111
Half Subtractor
Logic Diagram using Basic
Gates:

A B

D  A B

B  AB

112
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half and Full Subtractor, Gray
to Binary and Binary to Gray Code Converter (up to 4 bit).
113
 Full Subtractor
Full subtractor is a combinational logic
circuit with three inputs and two outputs.

A Differenc
e
Input B Full Output
s Subtract s
or Borro
w
Bi
n

114
Full Subtractor
Truth Table
Inputs Outputs

A B Bin (C) Difference (D) Borrow (B0)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
115
Full Subtractor
K-map for Difference Output:

BC BC BC BC BC
A 00 0 11 10
1
D  ABC  ABC  ABC  ABC
A 0 0 1 0 1
D  ABC  ABC  ABC  ABC
A 1 1 0 1 0 D  C( AB  AB)  C ( AB  AB)
Let AB  AB  X
ABC
ABC ABC
ABC  D  C( X )  C( X )
DCX
Let X  A B
D  C  A B
116
Full Subtractor

K-map for Borrow Output:

BC BC BC BC BC
A 00 0 11 10
1
A 0 0 1 1 1
B 0  AB  BC  AC
A 1 0 0 1 0

BC
AB
AC

117
Full Subtractor
Logic
Diagram:
A B C

D  A B  C

B 0  AB  B C  AC

118
Full Subtractor using Half Subtractor

A D0 D1
Difference
HS1 HS2
B B0 B1

C
Borrow

119
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half and Full Subtractor, Gray
to Binary Code Converter and Binary to Gray Code
Converter (up to 4 bit). 120
Design of Gray to Binary Code Converter
Block Diagram:

121
Design of Gray to Binary Code Converter
Truth Table :
Gray Inputs Binary Outputs Gray Inputs Binary Outputs

G3 G2 G1 G0 B3 B2 B1 B0 G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0
0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1

0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1

0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0

0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0

0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1

0 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1

0 1 1 1 0 1 0 0 1 1 1 1 1 0 0 0
Design of Gray to Binary Code Converter
K-map for B0: G1G0 G1G0 G1G0 G1G0 G1G0
00 01 11 10
G3G2
0 1 3 2
G3G2 00 0 1 0 1
4 5 7 6
GG23 01 1 0 1 0
12 13 15 14
G3G2 11 0 1 0 1
8 9 11 10
G3G2 10 1 0 1 0

B0  G3G2G1G0  G3G2G1G0  G3G2G1G0  G3G2G1G0

G3G2G1G0  G3G2G1G0  G3G2G1G0  G3G2G1G0
B0  G3  G2  G1  G0
Design of Gray to Binary Code Converter
K-map for B1: G1G0 G1G0 G1G0 G1G0 G1G0
00 01 11 10
G3G2
0 1 3 2
G3G2 00 0 0 1 1
4 5 7 6
GG23 01 1 1 0 0
12 13 15 14
G3G2 11 0 0 1 1
8 9 11 10
G3G2 10 1 1 0 0

B1  G3G2G1  G3G2G1  G 3 G 2 G 1  G 3 G 2 G 1

B1  G 3  G 2  G1
Design of Gray to Binary Code Converter
K-map for B2: G1G0 G1G0 G1G0 G1G0 G1G0
00 01 11 10
G3G2
0 1 3 2
G3G2 00 0 0 0 0
4 5 7 6
GG23 01 1 1 1 1
12 13 15 14
G3G2 11 0 0 0 0
8 9 11 10
G3G2 10 1 1 1 1

B2  G3G2  G3G2

B1  G 3  G 2
Design of Gray to Binary Code Converter

K-map for B3:

G1G0 G1G0 G1G0 G1G0 G1G0
00 01 11 10
G3G2
0 1 3 2
G3G2 00 0 0 0 0
4 5 7 6
GG23 01 0 0 0 0
12 13 15 14
G3G2 11 1 1 1 1
8 9 11 10
G3G2 10 1 1 1 1

B3  G3
Design of Gray to Binary Code Converter

Logic Diagram:
G3 G2 G1 G0

B3

B2  G 3  G 2

B1  G1  G2  G3

B0  G0  G1  G2  G3
 Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP)
& Product of Sum (POS), Maxterm and Minterm ,
Conversion between SOP and POS forms, realization using
NAND/NOR gates.

 K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP &
POS form)

 Design of Airthmetic circuits and code converter using

K-map: Half and Full Adder, Half and Full Subtractor, Gray
to Binary and Binary to Gray Code Converter (up to 4
bit).
 Design of Binary to Gray Code Converter

Block
Diagram:

B3 G3
B2 Binary to G2
Binary Gray Code Gray
B1 G1
Inputs Outputs
converter
B0 G0
 Design of Binary to Gray Code Converter
Truth Table :
Binary Inputs Gray Outputs Binary Inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0 B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0

0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1

0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1

0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0

0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0

0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1

0 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1

0 1 1 0 1 0 1 1 1 1 0 0
1 0 1 0
 Design of Binary to Gray Code Converter

K-map for G0:

B1 B0 B1B0 B1B0 B1B0 B1B0

00 01 11 10
B3B2
0 1 3 2
B3B2 00 0 1 0 1
4 5 7 6
B B23 01 0 1 0 1 G0  B1B0  B1B0
12 13 15 14
B3B2 11 0 1 0 1 G0  B0  B1
8 9 11 10
B3B2 10 0 1 0 1

B1B0 B1B0
Design of Binary to Gray Code Converter

K-map for G1:

B1B0 B1B0 B1B0 B1B0 B1B0

00 01 11 10
B3B2
0 1 3 2
B3B2 00 0 0 1 1
4 5 7 6
B B23 01 1 1 0 0 G1  B2B1  B2 B1
12 13 15 14
B3B2 11 1 1 0 0 G1  B2  B1
8 9 11 10
B3B2 10 0 0 1 1

B2B1 B2B1
Design of Binary to Gray Code Converter

K-map for G2:

B1 B0 B1B0 B1B0 B1B0 B1B0

00 01 11 10
B3B2
0 1 3 2
B3B2 00 0 0 0 0
4 7
B B23 01 1 1
5
1 1
6
G2  B3B2  B3B2
1 1 1 1
B3B2 11 02 03 05 04 G2  B3  B2
8 9 11 1
B3B2 10 1 1 1 0
1

B3B2 B3B2
Design of Binary to Gray Code Converter

K-map for G3:

B1 B0 B1B0 B1B0 B1B0 B1B0

00 01 11 10
B3B2
0 1 3 2
B3B2 00 0 0 0 0
4 5 7 6
B B23 01 0 0 0 0 G 3  B3
12 13 15 14
B3B2 11 1 1 1 1
8 9 11 10
B3B2 10 1 1 1 1

B3
Design of Binary to Gray Code Converter

Logic Diagram:
B3 B2 B1 B0

G3

G 2  B3  B 2

G1  B2  B1

G0  B1  B0
 Unit III – Combinational Logic Circuits

 Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD

Adder
 Encoder/Decoder: Basics of Encoder, decoder, comparison,
(IC 7447) BCD to 7- Segment decoder/driver.

 Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX tree,
IC 74151 as MUX, DEMUX tree, DEMUX as decoder, IC
74155 as DEMUX

 Buffer: Tristate logic, Unidirectional and Bidirectional buffer

(IC 74LS244 and IC 74LS245)
N – Bit Parallel Adder

 The full adder is capable of adding two single digit

binary numbers along with a carry input.

 But in practice we need to add binary numbers which

are much longer than one bit.

 To add two n-bit binary numbers we need to use the

n-bit parallel adder.

 It uses a number of full adders in cascade.

 The carry output of the previous full adder is
connected to the carry input of the next full adder..
 N – Bit Parallel Adder

An  1 Bn  1 A2 B2 A1 B1 A0 B0

FA-(n-1) FA-2 FA-1 FA-0

C0 C in

Sn  1 S2 S1 S0
 4 – Bit Parallel Adder using full adder

A3 B3 A2 B2 A1 B1 A0 B0

FA-3 FA-2 FA-1 FA-0

C0 C in

S3 S2 S1 S0
 IC 7483 4 – Bit Binary Parallel Adder

A3 B3 A2 B2 A1 B1 A0 B0

FA-3 FA-2 FA-1 FA-0

C0 C in

S3 S2 S1 S0
IC 7483 4 – Bit Binary Parallel Adder

A Binary B Binary
number number
A 3 A 2 A1 A 0
B 3 B 2 B1 B 0

IC 7483 Cin
C0
Carr
Carry
y
Outpu
Input
t

S3 S 2 S1 S0
Sum
Output
 Cascading of IC 7483

 If we want to add two 8 bit binary numbers using 4 bit binary parallel adder IC
7483,
then we have to cascade the two ICs in following way
Design of 1 Digit BCD Adder
Block A BCD no. B BCD no.
Diagram:
C0 IC
7483-I S 3 S 2 S1 S 0 C in

Logic
Circuit

Add 0110
Command

IC 7483-II
C0 C in

S3 S 2 S1 S0
Design of 1 Digit BCD Adder

As we know BCD addition rules, we understand that

the 4 bit BCD adder should consists of following:

 A 4 bit binary adder to add the given two (4 bit

numbers).

 A combinational logic circuit to check if sum is

greater than 9 or carry 1.

 One more 4 bit binary adder to add 0110 to the

invalid BCD sum or if carry is 1
Design of 1 Digit BCD Adder
Logic Table for design of Logic circuit:
Inputs Y Inputs Y

S3 S2 S1 S0 S3 S2 S1 S0

0 0 0 0 0 1 0 0 0 0

0 0 0 1 0 1 0 0 1 0

0 0 1 0 0 1 0 1 0 1

0 0 1 1 0 1 0 1 1 1
Sum
0 1 0 0 0 1 1 0 0 1 is
invalid
0 1 0 1 0 1 1 0 1 1 BCD
Number
0 1 1 0 0 1 1 1 0 1 Y=1

0 1 1 1 0 1 1 1 1 1
Design of 1 Digit BCD Adder

K-map for Logic circuit:

S1 S0 S1S0 S1S0 S1S0 S1S0

S3s2 00 01 11 10
0 1 3 2
S3S2 00 0 0 0 0
4 5 7 6
S3S2 01 0 0 0 0
12 13 15 14 Y  S 3S 2  S 3S1
S3S2 11 1 1 1 1
8 9 11 10
S3S2 10 0 0 1 1

S3S2 S1S3
Design of 1 Digit BCD Adder A BCD B BCD
no. no.
Combinational
Logic
Circuit
C0 IC
7483-I S 3 S 2 S1 S 0 C in

Y' Y

C0
IC 7483-II
Not S3 S 2 S1 C in
S0
used
Carry output
BCD Output Sum
4 Bit Binary Parallel Subtractor using IC 7483

A Binary number B Binary number

A 3 A 2 A1 A 0 B 3 B 2 B1 B 0
NOT gates for 1’s
complement of
B

Vcc 5V

C0
Carry IC 7483 Cin  1
Output S3 S 2 S1 S0 It adds 1 to 1’s
complement of B

Difference
Output
 IC 7483 as Parallel Adder/Subtractor
B Binary number
B3 B2 B1 B0
A Binary number
M
A 3 A 2 A1 A 0 Mode
Select

C0
Carry IC
7483 C in
Output S3 S 2 S1 S0

Sum or Difference Mode Select

Output M=0 Addition
M=1 Subtraction
 Unit III – Combinational Logic Circuits

 Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD

Adder
 Encoder/Decoder: Basics of Encoder, decoder,
comparison, (IC 7447) BCD to 7- Segment
decoder/driver.

 Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX tree,
IC 74151 as MUX, DEMUX tree, DEMUX as decoder, IC
74155 as DEMUX

 Buffer: Tristate logic, Unidirectional and Bidirectional buffer

(IC 74LS244 and IC 74LS245)
Encoder
 Encoder is a combinational circuit which is
designed to perform the inverse operation of
decoder.

 An encoder has ‘n’ number of input lines and ‘m’

number of output lines.

 An encoder produces an m bit binary code

corresponding to the digital input number.

 The encoder accepts an n input digital word and

converts it into m bit another digital word
Encoder

‘n’ ‘m’
. Encoder .
inputs . .
outputs
. .
Types of Encoders

Priority Encoder

Decimal to BCD Encoder

Octal to BCD Encoder

Hexadecimal to Binary Encoder

Priority Encoder

This is a special type of encoder.

Priorities are given to the input lines.

If two or more input lines are “1” at the same

time, then the input line with highest priority

will be considered.
Priority Encoder 8:3

Highest
Priority

D0
D1 Y2
D2 Priority ‘3’
‘8’ D3 Y1 outputs
Encoder
inputs D4 8:3
Y
0
D5
D6
D7

Lowest
Priority
Priority Encoder 8:3
Truth Table:
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 Y2 Y1 Y0
0 0 0 0 0 0 0 0 X X X

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 1 X X X 0 1 1

0 0 0 1 X X X X 1 0 0

0 0 1 X X X X X 1 0 1

0 1 X X X X X X 1 1 0

1 X X X X X X X 1 1 1
Decimal to BCD Encoder

D1
D2 A
D3
D4 Decimal to B. ‘BCD’
‘9’ D5 BCD C. outputs
inputs D6 Encoder
D7 D
D8
D9
Decimal to BCD Encoder
Truth Table:
Inputs Outputs
D9 D8 D7 D6 D5 D4 D3 D2 D1 D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 0 1 X 0 0 1 0
0 0 0 0 0 0 1 X X 0 0 1 1
0 0 0 0 0 1 X X X 0 1 0 0
0 0 0 0 1 X X X X 0 1 0 1
0 0 0 1 X X X X X 0 1 1 0
0 0 1 X X X X X X 0 1 1 1
0 1 X X X X X X X 1 0 0 0
1 X X X X X X X X 1 0 0 1
Decoder

Decoder is a combinational circuit is which

designed to perform the inverse operation
of encoder
An decoder has ‘n’ number of input lines
and maximum ‘2n’ number of output lines.
Decoder is identical to a demultiplexer
without data input.
Decoder

‘n’ ‘2n’
. decod .
inputs . .
outputs
er
. .
Typical applications of Decoders

Code Converters

BCD to 7 segment decoders

Nixie tube decoders

Relay actuators
Types of Decoders

2 to 4 line Decoder

3 to 8 line Decoder

BCD to 7 Segment
Decoder
 2 to 4 Line Decoder
Y0
A
Inputs 2:4 Y1 Block
B Decoder Y2 Diagram
Y3

E Enable
Input Enabl
Data Inputs Outputs
e
i/p
E A B Y0 Y1 Y2 Y3

0 X X 0 0 0 0

Truth 1 0 0 1 0 0 0
Table
1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1
2 to 4 Line Decoder
E A B
A B

Y0

Y1

Y2

Y3
3 to 8 Line Decoder
Block
Diagram

Y0
A
Y1
Input B Y2
3:8 Y3
Decoder Y4
C Y5
Y6
Y7

Enable
Input
 3 to 8 Line Decoder
Truth Table

Enabl
Inputs Outputs
e i/p

E A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0
1 0
Comparison between Encoder & Decoder

Sr.
Parameter Encoder Decoder
No.
1 Input applied Active input signal Coded binary input
(original message
signal)
2 Output Coded binary output Active output signal (original
generated message)

3 Input lines 2n n

4 Output lines N 2n

5 Operation Simple Complex

6 Applications E-mail , video Microprocessors,

encoders etc. memory chips etc.
BCD to 7 Segment Decoder - Seven Segment
Display
a

f b
g

e c

d dp
Seven Segment Display
Segments
Display Seven Segment
a b c d e f g Number Display

ON ON ON ON ON ON OFF 0

OFF ON ON OFF OFF OFF OFF 1

ON ON OFF ON ON OFF ON 2

ON ON ON ON OFF OFF ON 3

OFF ON ON OFF OFF ON ON 4

ON OFF ON ON OFF ON ON 5

ON OFF ON ON ON ON ON 6

ON ON ON OFF OFF OFF OFF 7

ON ON ON ON ON ON ON 8

ON ON ON ON OFF ON ON 9
Types of Seven Segment Display

Common Cathode Display

Common Anode Display

Common Anode Display

+Vc
c

R R R R R R R R

a b c d e f g dp
Common Anode Display

+Vc
c
a

R
b

R
c

R
d

R
BCD to
BCD e

R
7 Segment
Input
Decoder f

R
g
R
R

dp
Common Cathode Display

a b c d e f g d
p
R R R R R R R R
Common Cathode Display

R
b

R
c

R
d
BCD to
7 Segment

R
BCD e
Input Decoder

R
f

R
g

R
d
R
p
BCD to 7 Segment Decoder Driver ICs

Sr. No. IC Number Specifications

Active Low open collector

IC 7446,
1 outputs, maximum voltage 30
IC 74246
V,
maximum current sinking capability 40mA
Active Low open collector
IC 7447,
outputs, maximum voltage 15
2 IC 74247
V,
maximum current sinking capability 40mA
Active High open collector
outputs, Pull up resistor 2kohm,
IC 7448,
3 maximum voltage 5.5 V,
IC 74248
maximum current sinking capability 6.4mA
IC 7447
Pins Description

A,B,C,D BCD Inputs

a to g Active Low Outputs

LT
Lamp Test

RBI Ripple Blanking

Input
BI
Blanking Input

RBO Ripple
Blanking
output
 RBI - Ripple Blanking Input
 For the normal decoding operation, this input
should be connected to logic 1.
 If RBI is connected to ground, then it switches off
the display when BCD inputs or responding to 0.
 For non-zero BCD inputs, the decoder
output will be normal and the BCD number will be
displayed.
 RBI=0is connected for blanking out the leading
zeros in multidigit displays.
 BI – Blanking Input

If BI is connected to 0, then the display will

be switched off irrespective of the BCD
input.

This feature is used in the multiplexed

display in order to save power.

In the non-multiplexed displays this input

is permanently connected to Vcc
 RBO – Ripple Blanking Output

This output is normally at logic 1. But it

goes to logic 0 during the zero blanking
interval when RBI is forced to a low level.

RBO is used for cascading purpose and it

is connected to RBI of the next stage.

LT - Lamp Test

This pin can be used to check whether all

the segments of the display are working
properly or not.

If LT is forced low with RBO at logic 1 or

open, then all the output terminals will be

forced to their active state

 7 Segment Decoder Driver Circuit Diagram
5V

1
3 6
a 1 R Common
LT V cc
a
5 3
RBI R a
4 BI / RBO
b 1
b
2
11 R f b
c c g
IC R
1
LS 1 A0
7447 d 0 d
B 9 R e c
2 A1 e e dp
BC 6 R
1
Input
D A2 f f d dp
7 5
s A3 R
MS Gnd 14 g
B 8 g
Display Configuration – LTS 542

Common
g f a b

a
f b
g

e c

d d
p
e d c dp
Common
Display Configuration
 Unit III – Combinational Logic Circuits

 Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD

Adder
 Encoder/Decoder: Basics of Encoder, decoder, comparison,
(IC 7447) BCD to 7- Segment decoder/driver.

 Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX
tree, IC 74151 as MUX, DEMUX tree, DEMUX as decoder,
IC 74155 as DEMUX

 Buffer: Tristate logic, Unidirectional and Bidirectional buffer

(IC 74LS244 and IC 74LS245)
Multiplexers

Multiplexer is a circuit which has a number of

inputs but only one output.

Multiplexer is a circuit which transmits

large number of information signals over a
single line.

Multiplexer is also known as “Data Selector”

or MUX.
Necessity of Multiplexers
 In most of the electronic systems, the digital data is
available on more than one lines. It is necessary to
route this data over a single line.
 Under such circumstances we require a circuit which
select one of the many inputs at a time.
 This circuit is nothing but a multiplexer. Which has
many inputs, one output and some select lines.
 Multiplexer improves the reliability of the digital
system because it reduces the number of external
wired connections.
Advantages of Multiplexers

It reduces the number of wires.

So it reduces the circuit complexity and cost.

We can implement many combinational
circuits using Mux.

It simplifies the logic design.

It does not need the k-map and

simplification.
Applications of Multiplexers

It is used as a data selector to select one out

of many data inputs.

It is used for simplification of logic design.

It is used in data acquisition system.

In designing the combinational circuits.

In D to A converters.

To minimize the number of connections.

 Block Diagram of Multiplexer

D0 D0
D1 D1
Data D2 D2
Inputs D3 Y
D3
. .
.
n:1 .
. Mux Output .
. .
Output
. .
Dn-1 Dn-1
E
Enable
... ...
Input . .
Sm- S2 s0 Sm- S2 s0
SelectS1 S1
1 1

Lines
Fig. General Block Fig. Equivalent
Diagram Circuit
Relation between Data Input Lines & Select Lines

In general multiplexer contains , n data

lines, one output line and m select lines.

To select n inputs we need m select lines

such that 2m=n.

Types of Multiplexers

2:1 Multiplexer

4:1 Multiplexer

8:1 Multiplexer

16:1 Multiplexer

32:1 Multiplexer

64:1 Multiplexer

and so
on…………
 2:1 Multiplexer

Data D0
Inputs 2:1 Y
D1 Block
Mux
Output Diagram
E
Enable
Input
s
Select
Lines Enable Select Outpu
i/p i/p t
(E) (S) (Y)
0 X 0

Truth
1 0 D0
Table

1 1 D1
Realization of 2:1 Mux using gates

S D1 D0
S

SD0
Y

Output
SD 1
E
Enable
Input
 4:1 Multiplexer

Block Truth
Diagram Table
Output
Enable i/p Select i/p
D0
D1 E S1 S0 Y
Data
Y
Inputs D2 4:1
Mux 0 X X 0
Output
D3 D0
1 0 0
E
1 0 1 D1
Enable
Input S1 S0
1 1 0 D2
Select
Lines D3
1 1 1
Realization of 4:1 Mux using gates

S1 S0

S1S 0D0
D0
S1S 0 D 1
D1 Y

Output
D2 S1S 0D2

E
D3 S1S 0 D3 Enable
Input
 8:1 Multiplexer
Block
Truth
Diagram
Table
D0
Out
D1 Enable
Select i/p p
i/p
D2 ut
D3 E S2 S1 S0 Y
Data
Y
Inputs D4 8:1 0 X X X 0
Mux Output 1 0 0 0 D0
D5
1 0 0 1 D1
D6
1 0 1 0 D2
D7
1 0 1 1 D3
1 1 0 0 D4
E
1 1 0 1 D5
Enable
Input 1 1 1 0 D6
S2 S1 S0 1 1 1 1 D7
Select Lines
16:1 Multiplexer
Block
D0
Diagram D1
D2
D3
D4
D5
Data D6 Y
Inputs D7 16:
D8 1
D9 Outpu
Mu
D10 t
x
D11
D12
D13
D14
D15

E
Enable Input

S3 S2 S1 S0
Select Lines
 Enable Select Lines Output
16:1 Multiplexer
E S3 S2 S1 S0 Y
0 X X X X 0
1 0 0 0 0 D0
1 0 0 0 1 D1
1 0 0 1 0 D2
1 0 0 1 1 D3
1 0 1 0 0 D4
1 0 1 0 1 D5
Truth 1 0 1 1 0 D6
Table 1 0 1 1 1 D7
1 1 0 0 0 D8
1 1 0 0 1 D9
1 1 0 1 0 D10
1 1 0 1 1 D11
1 1 1 0 0 D12
1 1 1 0 1 D13
1 1 1 1 0 D14
1 1 1 1 1 D
Mux Tree

The multiplexers having more number of

inputs can be obtained by cascading two or
more multiplexers with less number of
inputs. This is called as Multiplexer Tree.

For example, 32:1 mux can be realized

using two 16:1 mux and one 2:1 mux.
 8:1 Multiplexer using 4:1 Multiplexer

D0
D1
Y
D2 4:1 1
Mux
D3

S2 E S Y
Select
S1 0
Lines S1
S0 Output
S S
D4 1 0

D5
4:1
D6 Mux
Y2
D7

E
8:1 Multiplexer using 4:1 Multiplexer

D0
D1
Y
D2 4:1 1
Mux
D3

D0
E S 2:1 Y
D1
S1 S1 0 Mux
S0 Output
E
S S
D4 1 0

D5 S2
4:1
D6 Mux
Y2
D7

E
 D0
4:1 Y1
16:1 Mux using
D1
D2
D3
Mux 4:1 Mux
S1 S0
S1
S0
D4 S1 S0
D5 4:1 Y2
D6 Mux
D7
D0
D1 4:1 Y
D2 Mux
D3 S S Output
D8 1

D9 4:1 Y3 0

D10 Mux
D11
S1 S0 S3 S2

D12 S1 S0
D13 4:1 Y4
D14 Mux
D15
Realization of Boolean expression using Mux

We can implement any Boolean expression

using Multiplexers
It reduces circuit complexity.

It does not require any simplification

 Example 1

Implement following Boolean expression using multiplexer

f ( A, B , C )   m ( 0 , 3, 5, 6 )

Since there are three variables, therefore a

multiplexer with three select input is required
i.e. 8:1 multiplexer is required
The 8:1 multiplexer is configured as below to
implement given Boolean expression
Example 1 continue…..

+Vcc f ( A, B , C )   m ( 0 , 3, 5, 6 )

D0
D1
D2
D3
Y
D4 8:1
Mux
Output
D5
D6
D7

E S2 S1
S
0

A B C
Example 2

Implement following Boolean expression using multiplexer

f ( A, B , C , D )   m ( 0 , 2, 3, 6 , 8 , 9 , 1 2 , 1 4 )

Since there are four variables, therefore a

multiplexer with four select input is required

i.e. 16:1 multiplexer is required

The 16:1 multiplexer is configured as below
to implement given Boolean expression
Example 2 continue…..

+Vcc f ( A, B , C , D )   m ( 0 , 2, 3, 6 , 8, 9 , 1 2, 1 4)

D0
D1
D2
D3
D4
D5
D6 Y
D7 16:1
D8 Mux
D9 Output
D10
D11
D12
D13
D14
D15
S3 S2 S1 S0
E

A B C D
 Unit III – Combinational Logic Circuits

 Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD

Adder
 Encoder/Decoder: Basics of Encoder, decoder, comparison,
(IC 7447) BCD to 7- Segment decoder/driver.

 Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX
tree, IC 74151 as MUX, DEMUX tree, DEMUX as decoder,
IC 74155 as DEMUX

 Buffer: Tristate logic, Unidirectional and Bidirectional buffer

(IC 74LS244 and IC 74LS245)
De-multiplexer

A de-multiplexer performs the reverse

operation of a multiplexer i.e. it receives one
input and distributes it over several outputs.
At a time only one output line is selected by
the select lines and the input is transmitted
to the selected output line.
It has only one input line, n number of
output lines and m number of select lines.
 Block Diagram of De-multiplexer

Y0 Y0
Y1 Y1
Y2 Y2
Data Y3 Y3
Input 1:n . Data .
. .
De-mux .
Outputs Input .
Output
. .
. .
Yn-1 Yn-1
E
Enable
Input ... ...
. .
Sm-1 S2 S1s0 Sm-1 S2 S1s0
Select
Lines
Fig. General Block Fig. Equivalent
Diagram Circuit
Relation between Data Output Lines & Select
Lines

In general de-multiplexer contains , n output

lines, one input line and m select lines.

To select n outputs we need m select lines

such that n=2m.

Types of De-multiplexers

1:2 De-multiplexer
1:4 De-multiplexer
1:8 De-multiplexer
1:16 De-multiplexer
1:32 De-multiplexer
1:64 De-multiplexer
and so on………
1: 2 De-multiplexer

Y0
Data Din 1:2
Block
Input De-mux
Y1 Diagram
E
Enable
Input S
Select
Lines
Enable i/p Select i/p Outputs

E S Y0 Y1

Truth 0 X 0 0
Table
1 0 Din 0

1 1 0 Din
1:2 De-mux using basic gates

E Din S
S

Y0

Y1
 1: 4 De-multiplexer
Y0
Data Din 1:4 Y1
Block
Input De-mux Y2 Diagram
Y3
E
Enable
Input Enabl
S1 S0 Select i/p Outputs
Select e
Lines i/p
E S1 S0 Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1 0 0 Din 0 0 0
Truth
Table 1 0 1 0 Din 0 0

1 1 0 0 0 Din 0

1 1 1 0 0 0 Din
1:4 De-mux using basic gates
E Din S 1 S0
S1 S0

Y0

Y1

Y2

Y3
1: 8 De-multiplexer

Block
Diagram
Y0
Y1
Data Din Y2
1:8 Y3
Input Y4
De-mux
Y5
Y6
E Y7
Enable
Input
S2 S1 S0
Select
Lines
 1: 8 De-multiplexer
Truth Table

Enabl
Select i/p Outputs
e i/p

E S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 Din
1 0 0 1 0 0 0 0 0 0 Din 0

1 0 1 0 0 0 0 0 0 Din 0 0

1 0 1 1 0 0 0 0 Din 0 0 0

1 1 0 0 0 0 0 Din 0 0 0 0

1 1 0 1 0 0 Din 0 0 0 0 0

1 1 1 0 0 Din 0 0 0 0 0 0

1 1 Din 0 0 0 0 0 0
1 1 0
1: 16 De-multiplexer
Y0
Block
Y1
Diagram
Y2
Y3
Y4
Y5
Y6
Din
Data Y7
Input Y8
1:16
Y9
De-mux
Y10
Y11
Y12
Y13
Y14
E Y15
Enable
Input
S3 S2 S1 S0
De-mux Tree

Similar to multiplexer we can construct the

de- multiplexer with more number of lines

using de- multiplexer having less number of

lines. This is call as “De-mux Tree”.

1:4 De-mux using 1:2 De-mux

Data Y Y0
1:2 0
Input Din
De-mux
Y1 Y1
S1 E S0
Select
Lines
S0

S0
Y0 Y2
Din 1:2
De-mux
Y1 Y
E 3
 Y0
1:16 De-mux using 1:4 1:4 Y1
De-mux Din De-mux Y2
Y3
S1 S0

S1 S0 Y4
1:4 Y5
Din Y6
Data Y0 De-
D mux Y7
Input in 1:4 Y1
De-mux Y2
Y3
S1 S0
Y8
1:4 Y9
Din De-mux
Y10
S3 S2 S1 S0 Y11

S1 S0 Y12
Din 1:4 Y13
De- Y14 S1 S0
mux Y15
Decoder

Decoder is a combinational circuit.

It converts n bit binary information at its

input into a maximum of 2n output lines.

For example, if n=2 then we can design upto

2:4 decoder
 2:4 Decoder
Y0
A
2:4 Y1
Inputs
Decoder Y2
B
Y3
Truth Table
E Enable
Input Enabl
Data Inputs Outputs
Block Diagram e
i/p
E A B Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1
De-multiplexer as Decoder

It is possible to operate a de-multiplexer as

a decoder.

Let us consider an example of 1:4 de-mux

can be used as 2:4 decoder

 1:4 De-multiplexer as 2:4 Decoder

Vcc

Y0 Din Y0
A S1
Data 1:4 Y1 1:4 Y1
Inputs
Din De-mux Y2 De-mux Y2
B S0
Input Y3 Y3
E
Enabl Input
E Enable
e S1 S0
Input Select Lines
1: 4 De- 1: 4 De-multiplexer as 2:4
multiplexer Decoder
Realization of Boolean expression using De-
mux
We can implement any Boolean
expression

using de-multiplexers.

It reduces circuit complexity.

It does not require any simplification

Example 1

Implement following Boolean expression using de-multiplexer

f ( A, B , C )   m ( 0 , 3, 5, 6 )

 Since there are three variables, therefore a de-

multiplexer with three select input is required
i.e. 1:8 de-multiplexer is required

 The 1:8 de-multiplexer is configured as below

to implement given Boolean expression
Example 1 continue…..

f ( A, B , C )   m ( 0 , 3, 5, 6 )

+Vcc Y0
Y1
Data Y2
Din 1:8 Y3 Y
Input Y4
De-
mux Y5
Y6
E S2 S1 S0 Y7
Enable
Input
A B
C
Example 2

Implement following Boolean expression using de-

multiplexer

f ( A, B , C , D )   m ( 0 , 2, 3, 6 , 8 , 9 , 12 , 1 4)

 Since there are four variables, therefore a de-

multiplexer with four select input is required
i.e. 1:16 de-multiplexer is required
 The 1:16 de-multiplexer is configured as
below to implement given Boolean
expression
Example 2 continue…..

Y0
Y1
Y2
+Vcc Y3
Y4
Y5
Y6
Data 1:16 Y7 Y
Input De-mux Y8
Din
Y9
Y10
Y11
Y12
Y13
Y14
E S3 S2 S S Y15
1 0
Enable
Input f ( A, B , C , D )   m ( 0 , 2, 3, 6 , 8, 9 , 1 2, 1 4)
A B C D
Multiplexer
ICs
IC Number Description Output

IC 74157 Quad 2:1 Mux Same as input

IC 74158 Quad 2:1 Mux Inverted Output

IC 74153 Dual 4:1 Mux Same as input

IC 74352 Dual 4:1 Mux Inverted Output

IC 74151 8:1 Mux Inverted Output

IC 74152 8:1 Mux Inverted Output

IC 74150 16:1 Mux Inverted Output

IC 74151 – General Description
 This Data Selector/Multiplexer contains full on-chip decoding to
select one-of-eight data sources as a result of a unique three-bit
binary code at the Select inputs.

 Two complementary outputs provide both inverting and non-

inverting
buffer operation.
 A Strobe input is provided which, when at the high level, disables
all data inputs and forces the Y output to the low state and the

Y output to the high state.

 The Select input buffers incorporate internal overlap features to
ensure that select input changes do not cause invalid output
transients.
IC 74151 - Features

Advanced oxide-isolated, ion-

implanted Schottky TTL process
Switching performance is guaranteed over full
temperature and VCC supply range
Pin and functional compatible with LS
family counterpart

Improved output transient handling

capability
IC 74151 – Pin Diagram VC GN
C D

D0
D1

D2 Y
Data D3
Input D4 8:1
s Mu
D5 x Y
D6
D7

E
Enable
Pin
Input
Diagram S2 S1 S0
Select Lines
Equivalent Diagram
De-multiplexer ICs

IC Number Description

IC 74138 1:8 De-multiplexer

IC 74139 Dual 1:4 De-multiplexer

IC 74154 1:16 De-multiplexer

IC 74155 Dual 1:4 De-multiplexer

IC 74155 – General Description

These monolithic TTL circuits feature dual 1

line to 4 line de-multiplexers with individual
strobes and common binary address inputs
in a single 16 pin package.

The individual strobes permit activating or

inhibiting each of the 4-bit sections as
desired.
IC 74155 - Features
 Input clamping diodes simplify system design.
 Choice of outputs : Totem pole (‘LS155A) or
open collector (‘LS156).
 Individual strobes simplify cascading for decoding or
de- multiplexing larger words.
 Applications:
• Dual 2 to 4 Line Decoder
• Dual 1: 4 De-multiplexer
• 3 to 8 line Decoder
• 1 to 8 line de-multiplexer
IC 74155 – Pin Diagram
IC 74154 – General Description
 The M74HC154 is an DECODER/DEMULTIPLEXER technology
high speed fabricated CMOS 4 to 16 Line with silicon gate
C2MOS
 A binary code applied to the four inputs (A to D) provides a low
level at the selected one of sixteen outputs excluding the other
fifteen outputs, when both the strobe inputs, G1 and G2, are
held low.

 When either strobe input is held high, the decoding function is

inhibited to keep all outputs high.

 The strobe function makes it easy to expand the decoding lines

through cascading, and simplifies the design of address
decoding circuits in memory control systems.
IC 74154 - Features
 HIGH SPEED: tPD = 16ns (TYP.) at VCC = 6V

 LOW POWER DISSIPATION: ICC = 4mA(MAX.) at TA=25°C

 HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)

 SYMMETRICAL OUTPUT IMPEDANCE:|IOH| = IOL = 4mA
(MIN)

 BALANCED PROPAGATION DELAYS: tPLH @ tPHL

 WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to

6V

 PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 154

IC 74154 – Pin Diagram
 Unit III – Combinational Logic Circuits

 Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD

Adder
 Encoder/Decoder: Basics of Encoder, decoder, comparison,
(IC 7447) BCD to 7- Segment decoder/driver.

 Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX tree,
IC 74151 as MUX, DEMUX tree, DEMUX as decoder, IC
74155 as DEMUX

 Buffer: Tristate logic, Unidirectional and Bidirectional

buffer (IC 74LS244 and IC 74LS245)
Tristate Logic

In digital electronics three-state, tri-state, or

3- state logic allows an output port to

assume a high impedance state in addition

to the 0 and 1 logic levels, effectively

removing the output from the circuit.

Digital Buffer

Sometimes in digital electronic circuits we

need to isolate logic gates from each other
or have them drive or switch higher than
normal loads, such as relays, solenoids and
lamps without the need for inversion.

One type of single input logic gate that allows

us to do just that is called the Digital Buffer.
Digital Buffer

Symbol Truth Table

A Q

0 0

The Digital Buffer 1 1

Boolean Expression Q = A Read as: A gives Q

Digital Buffer

 Unlike the single input, single output inverter or NOT

gate such as the TTL 7404 which inverts or
complements its input signal on the output, the
“Buffer” performs no inversion or decision making
capabilities (like logic gates with two or more inputs)
but instead produces an output which exactly
matches that of its input. In other words, a digital
buffer does nothing as its output state equals its
input state.
Digital Buffer

Then digital buffers can be regarded as

Idempotent gates applying Boole’s
Idempotent Law because when an input
passes through this device its value is not
buffer is So
changed. a “non-inverting”
the digital device
therefore and will giveus the
of: Q = Boolean expression
A.
Tri-state Buffer

As well as the standard Digital Buffer

seen above, there is another type
circuit
of digital
whose
buffer
output can “electronically”
be disconnected circuitry
required.
from
Thisits
type of Buffer
outputis known aswhe
a 3-
State Buffer or more commonly
n a Tri-state
Buffer.
Tri-state Buffer
 A Tri-state Buffer can be thought of as an input
controlled switch with an output that can be
electronically turned “ON” or “OFF” by means of an
external “Control” or “Enable” ( EN ) signal input.
This control signal can be either a logic “0” or a
logic “1” type signal resulting in the Tri-state Buffer
being in one state allowing its output to operate
normally producing the required output or in another
state were its output is blocked or disconnected.
Tri-state Buffer - Equivalent
Active High Tri-state Buffer

Symbol Truth Table

Enable IN OUT

0 0 Hi-Z

0 1 Hi-Z

1 0 0
Tri-state Buffer

1 1 1

Read as Output = Input if Enable is equal to “1”

Active Low Tri-state Buffer

Symbol Truth Table

Enable IN OUT

0 0 0

0 1 1

1 0 Hi-Z

Tri-state Buffer 1 1 Hi-Z

Read as Output = Input if Enable is NOT equal to “1”

Tri-state Buffer Control
Buffer ICs
Sr.
IC Number Description
No.
1 IC 7407 TTL Hex non inverting Buffer

2 IC 7417 TTL Hex Buffer/Driver

3 IC 74244 TTL Octal Unidirectional Buffer

4 IC 74245 TTL Octal Bi-directional Buffer

5 IC 4050 CMOS Hex Non-inverting Buffer

6 IC 4503 CMOS Hex Tri-state Buffer

7 IC 40244 CMOS Octal Tri-state Buffer

IC 74244 - Features
 ESD protection: HBM EIA/JESD22-A114-A exceeds 2000
V MM EIA/JESD22-A115-A exceeds 200 V CDM
EIA/JESD22-C101 exceeds 1000 V

 Balanced propagation delays

 All inputs have a Schmitt-trigger action
 Inputs accepts voltages higher than VCC
 For AHC only: operates with CMOS input levels
 For AHCT only: operates with TTL input levels
 Specified from − 40 to +85 and +125°C
IC 74244 – Internal Diagram
Bi-directional Buffer

It is also possible to connect Tri-state Buffers

“back-to-back” to produce what is called a Bi-
directional Buffer circuit with one “active-
high buffer” connected in parallel but in
reverse with one “active-low buffer”.
Bi-directional Buffer

Here, the “enable” control input acts more

like a
directional control signal causing the data to
be both read “from” and transmitted “to” the
same data bus wire. In this type of
application a tri- state buffer with bi-
directional switching capability such as the
TTL 74245 can be used.
IC 74245 - Description
 These octal bus transceivers are designed for
asynchronous two-way communication between data
buses.
 The control function implementation minimizes external
timing requirements.
 The device allows data transmission from the A Bus to
the B Bus or from the B Bus to the A Bus depending
upon the logic level at the direction control (DIR) input.
 The enable input (G) can be used to disable the device
so that the buses are effectively isolated.
IC 74245 - Features
 Bi-Directional bus transceiver in a high-density 20-
pin package

 3-STATE outputs drive bus lines directly

 PNP inputs reduce DC loading on bus lines
 Hysteresis at bus inputs improve noise margins
 Typical propagation delay times, port-to-port 8 ns
 Typical enable/disable times 17 ns
 IOL (sink current) - 24 mA
 IOH (source current) - -15 mA
IC 74245 – Internal Diagram
References
 Modern Digital
Electronics by R.P. Jain
 Digital Electronics,
Principles and
Applications by Tokheim
 Digital Techniques by A.
Anand Kumar