Digital Comparator:

There are two main types of Digital comparators available and these are; Identity
Comparator and Magnitude Comparator. Digital/Binary Comparators are built up of standard
AND, NOR and NOT gates

Identity Comparator

An Identity Comparator is a digital comparator that examines only the equality of two
involved signals at its inputs. It has two inputs and only one output pin. The output pin displays a
logic high signal when the two values are equal otherwise it gives a low signal.

For two inputs say, P and Q, if P = Q then output HIGH, i.e P = Q=1 or P = Q=0 and if P ≠ Q
then output LOW

Magnitude Comparators

A magnitude comparators performs the comparison by analyzing all the factors. It shows
results for either greater (>), equal (=) or lesser than(<) value by comparing the magnitude of two
inputs.

1 Bit Comparators
A comparator which compare two bits is termed a single bit comparator. Henceforth
contains three output pins and accordingly, any one of the 3 output pins of a magnitude
comparator becomes high as per the input conditions(less than, equal to and greater).

Suppose A and B are the two inputs of magnitude comparators. And the three outputs will be A
> B, A = B and A < B. Moreover depending upon the comparison done, any one of the given
outputs will be high. The truth table for 1 Bit Comparator is explained below:

A B A<B A=B A>B

0 0 0 1 0
 0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

1-Bit Digital Comparator Circuit

It is clear from the above truth table that when both the inputs are identical i.e. either 0 or 1 then
the 2nd pin which is giving equivalency between the two values in the comparison table becomes
high.

4-Bit Magnitude Comparator

The 4-bit magnitude comparator is used in more complex digital circuits like
microprocessors, microcontrollers, and many more. It is a type of comparator that can compare
the values or magnitudes of two 4-bit binary numbers and produce an output indicating whether
one number is equal to or less than or greater than the other.

The block diagram of the 4-bit magnitude comparator is shown in the following figure

Let us now understand the working of this 4-bit magnitude comparator. For that consider
A = A3A2A1A0 is the first 4-bit binary number and B = B3B2B1B0 is the second 4-bit binary
number. The comparator will show the results as follows.

Case-1 A=B
E=(A3⊙B3)(A2⊙B2)(A1⊙B1)(A0⊙B0)

Case-2 A<B

Case-3 A>B

The logic circuit implementation of the 4-bit magnitude comparator is shown in the following
figure.

The IC 7485 compares corresponding bits of the two input numbers and determines whether one
number is equal to or greater than or less than the other. The pin diagram of the IC 7485 is
depicted in the following figure.
Seven Segment Decoder:
Seven Segment display is an electronic device which consists of seven Light Emitting Diodes
(LEDs) arranged in a some definite pattern (common cathode or common anode type), which is
used to display Hexadecimal numerals (in this case decimal numbers, as input is BCD i.e., 0-
9). Two types of seven segment LED display:
1. Common Cathode Type: In this type of display all cathodes of the seven LEDs are
connected together to the ground or -Vcc(hence, common cathode) and LED displays digits
when some 'HIGH' signal is supplied to the individual anodes.
2. Common Anode Type: In this type of display all the anodes of the seven LEDs are
connected to battery or +Vcc and LED displays digits when some 'LOW' signal is supplied
to the individual cathodes.
But, seven segment display does not work by directly supplying voltage to different segments
of LEDs. First, our decimal number is changed to its BCD equivalent signal then BCD to seven
segment decoder converts that signals to the form which is fed to seven segment display. This
BCD to seven segment decoder has four input lines (A, B, C and D) and 7 output lines (a, b, c,
d, e, f and g), this output is given to seven segment LED display which displays the decimal
number depending upon inputs.
Truth Table
For common cathode type BCD to seven segment decoder:

K-Maps:
#for a:

#for b:
#for c:

#for d:
#for e:
 #for f:
#for g:
Programmable Logic Devices (PLDs)

Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of AND
gates & another array of OR gates. There are three kinds of PLDs based on the type of array(s),
which has programmable feature.

1. Programmable Read Only Memory (PROM)

2. 2. Programmable Array Logic (PAL)

3. Programmable Logic Array (PLA)

The process of entering the information into these devices is known as programming. Basically,
users can program these devices or ICs electrically in order to implement the Boolean functions
based on the requirement. Here, the term programming refers to hardware programming but not
software programming.

Programmable Read Only Memory (PROM)

Read Only Memory (ROM) is a memory device, which stores the binary information
permanently. That means, we can’t change that stored information by any means later. If the
ROM has programmable feature, then it is called as Programmable ROM (PROM). The user has
the flexibility to program the binary information electrically once by using PROM programmer.

PROM is a programmable logic device that has fixed AND array & Programmable OR array.
The block diagram of PROM is shown in the following figure.

Here, the inputs of AND gates are not of programmable type. So, we have to generate 2n product
terms by using 2n AND gates having n inputs each. We can implement these product terms by
using nx2n decoder. So, this decoder generates n min terms.
Here, the inputs of OR gates are programmable. That means, we can program any number of
required product terms, since all the outputs of AND gates are applied as inputs to each OR gate.
Therefore, the outputs of PROM will be in the form of sum of min terms.

Example

Let us implement the following Boolean functions using PROM.

A(X,Y,Z)=∑m(5,6,7) B(X,Y,Z)=∑m(3,5,6,7)

The given two functions are in sum of min terms form and each function is having three
variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for
producing these two functions. The corresponding PROM is shown in the following figure.

Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access
of all these min terms. But, only the required min terms are programmed in order to produce the
respective Boolean functions by each OR gate. The symbol X is used for programmable
connections.