Name of faculty Dr.

Rajesh Kumar Bathija

Class B. Tech – IInd Year III Sem F Section

Branch COMPUTER ENGINEERING

Course Code 3CS3-04
Course Name Digital Electronics
Session 2024-25
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING

Vision & Mission of Poornima College of Engineering

Vision

To create knowledge based society with scientific temper, team spirit and dignity of labor to face the
global competitive challenges.
Mission

To evolve and develop skill based systems for effective delivery of knowledge so as to equip
young professionals with dedication and commitment to excellence in all spheres of life.

Vision & Mission of Department of Computer Engineering

Vision
Become most preferred department for the latest advanced computing programs through creating
appropriate teaching-learning and skill up gradation environment that fulfill current industry needs.
Mission

1. To create experiential learning environment that will enable students to compete globally in
advanced computing domain.
2. To adapt latest technological tools and contribute significantly for the advancement of
knowledge in computer engineering application in industry, society and environment.
3. To inculcate essential characteristic in the students for their all-round professional
development, interaction with industry and society and lifelong learning.
4. To create R & D infrastructure and center of excellence in various advanced computing sub
domains.
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING

PROGRAM EDUCATIONAL OBJECTIVES (PEO’S)

PEO1: Gradates will exhibit knowledge and expertise to design and develop solution for complex
engineering problem of industry and society efficiently using Artificial Intelligence.
PEO2: Gradates will be able to occupy lead position through their problem solving skills and life-long
learning ability.

PEO3: Gradates will have strong professional ethics, social & moral values, entrepreneurial ability and
interaction with society & industry.

PROGRAM OUTCOMES (POs)

PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems.

PO2: Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
PO3: Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for the public health and safety, and the cultural, societal, and environmental considerations.
PO4: Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO7: Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO9: Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO10: Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive clear
instructions.
PO11: Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader in
a team, to manage projects and in multidisciplinary environments.
PO12: Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO1: Apply the knowledge of Artificial Intelligence, machine learning, Human Computer Interaction
in any societal, industrial and environmental application

PSO2: Demonstrate skills to design develop and investigate complex real time problems using AI and
its tools by working individual or in groups as a leader or member of the team following professional
ethics and human values.

PSO3: Adapt, analyse, investigate the problems and provide solutions for interdisciplinary problems
using modern and advanced AI tools and techniques possessing lifelong learning ability.
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING

MAPPING OF KEY PHRASES OF THE INSTITUTES MISSION STATEMENT WITH THE KEY
PHRASES OF INSTITUTES VISION STATEMENT

(Institution Mission vs Institute Vision)

Key Phrases of the Mission Key Phrases of the Vision Statement of the Institute

Statement of the Institute To create knowledge based Team To face the global
society with scientific temper spirit competitive challenges
Skill based systems for effective 3 3
delivery of knowledge
To equip young professionals 1 3
with dedication
Excellence in all spheres of life 2 2

MAPPING OF KEY PHRASES OF THE DEPARTMENTSVISION STATEMENT WITH THE KEY

PHRASES OF INSTITUTES MISSION STATEMENT

(Department Vision vs Institution Mission)

Key Phrases of the Vision Statement of Key Phrases of the Mission Statement of the Institute

the Department Skill Based Delivery of Excellence in all

Systems Knowledge spheres of life

Centre of Excellence 3 2 1

Wider recognition 2 2 1

Rapid innovation. 2 1
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING

MAPPING OF KEY PHRASES OF THE DEPARTMENTS MISSION STATEMENT WITH THE KEY
PHRASES OF DEPARTMENTS VISION STATEMENT (Department Mission Vs Department Vision)

Key Phrases of the Vision Statement of the Department

Key Phrases of the Mission Statement of the
Department Centre of Wider Rapid
Excellence recognition innovation.

Learning-centered environment 3 2

Research and Discovery 2 2

Social Responsibility 1 2 1

MAPPING OF KEY PHRASES PEOS WITH KEY PHRASES OF DEPARTMENTS MISSION

STATEMENT
(PEO Vs Department Mission)

Key Phrases of the Mission of the Department

Key Phrases of PEO Statements Learning-centered Research and Social

environment Discovery Responsibility

Skillful engineers 3 2

Innovative, Creative, and 3 1

Sophisticated Technologies
Pioneering Ideas 2 2
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING

MAPPING OF KEY PHRASES OF PSO WITH KEY PHRASES OF DEPARTMENTS MISSION

STATEMENT
(PSO Vs Department Mission)

Key Phrases of the Mission Department

Key Phrases of PSO Statement
Learning-centred Research and Social
environment Discovery Responsibility
Technical Knowledge 3 2

Standards, Ethic, Tools, Challenges 1 2 2

Societal Problems
Entrepreneur, Lifelong Learning and 2
Higher Studies.
MAPPING OF KEY PHRASES OF PEO WITH KEY PHRASES OF PO

(PEO Vs PO)

Key Phrases of PO Statement

Cond
Desig uct Mo The Envir Indi Project
Pro n/ investi engi vidu
Engine der onmen Com manage Life-
Key Phrases of PEO ble devel gation nee Et al
ering n t and muni ment long
m opme s of r hic and
Statement knowle tool sustai catio and learn
anal nt of compl and s: team
dge: usa nabilit n: finance ing:
ysis: soluti ex soci wor
ge: y: :
ons: proble ety: k:
ms:
Skillful engineers 3 3 3 3 2 1 1 2 2 1 2

Innovative, Creative, 3 2 2 1 1 1
and Sophisticated
Technologies
Pioneering Ideas 2 1 1 2 2 1 1 2 1 2
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING

MAPPING OF KEY PHRASES OF PSO WITH KEY PHRASES PEO

(PSO Vs PEO)

Key Phrases of the PSO Department

Key Phrases of the PEO

Standards, Ethic, Tools, Entrepreneur, Lifelong
Department
Technical Challenges Societal Learning and Higher
Knowledge Problems Studies.

Skillful engineers 3 2 2

Innovative, Creative, and 2 2 2

Sophisticated Technologies
Pioneering Ideas 1 2
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING
Campus: Poornima College of Engineering Year/Section: 2nd Date: 05 Aug 2024
Course: B. Tech. Semester/ Section – III F
Name of Faculty: Dr. Rajesh Kumar Bathija Name of Subject : Digital Electronics Code: 3CS3-04
ABC analysis (RGB method) of unit & topics:-

Unit A B C Preparedness
No. (Hard Topics) (Topics with average hardness level) (Easy to understand topics) for ‘A’ topics
Features of logic algebra, Fixed point representation, Fundamental concepts:
postulates of Boolean algebra. complement notation, various Number systems and
I Theorems of Boolean algebra codes & arithmetic in different codes codes, Basic logic Gates PPT
& their inter conversion., and Boolean algebra:
Sign & magnitude
representation
Minimization of Boolean Minimization Techniques Quine-McCluskey method
expressions –– Minterm – and Logic Gates: Principle of Duality of
Maxterm - Sum of Products - Boolean expression Minimization. PPT
II (SOP) – Product of Sums
(POS) – Karnaugh map
Minimization – Don’t care
conditions
Open collector TTL. Three Digital Logic Gate Characteristics: Realization of logic gates
III state output logic. TTL TTL logic gate characteristics. Theory in RTL, DTL, ECL, C- Video
subfamilies. MOS& CMOS & operation of TTL NAND gate MOS & MOSFET Lecture,
logic families. circuitry. PPT
BCD to 7-segment BCD adder, encoder, decoder, Combinational logic Video
IV decoder, multiplexer, circuit design, adder, Lecture,
demultiplexer. subtractor, PPT
Sequential Circuits: Synchronous counters– Synchronous sequential circuits design
Latches, Flip- flops - SR, Up/Down counters – Programmable methodology. Registers –
V JK, D, T, and Master- Slave counters – State table shift registers. Video
Characteristic table and and state
equation, counters and their transition diagram, Lecture
design
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR DEPARTMENT OF COMPUTER ENGINEERING
Campus: Poornima College of Engineering Year/Section: 2nd Date: 05 Aug 2024
Course: B. Tech. Semester/ Section – III-F
Name of Faculty: Dr. Rajesh Kumar Bathija Name of Subject : Digital Electronics Code: 3CS3-04

Zero Lecture
Name of Faculty: Prof. (Dr.) Rajesh Kumar Bathija Branch: Computer Engineering

1). Name of Subject with Code: Digital Electronics (3CS3-04)

2). Self-Introduction:

a). Name: Prof. (Dr.) Rajesh Kumar Bathija

b). Qualification: BE, M. Tech., PhD

c). Designation: Professor

d). Research Area: VLSI Design, DSP

e). E-mail Id: [email protected]

f). Other details:

3). Introduction of Students: II year III Semester (Computer Engineering)

a). Identifying and keeping records of students based on meritorious/weak in academics.
b). Achievement of students in previous years:-

4). Instructional Language: - 100% English

5). Introduction to subject: -

a). Relevance to Branch:

The ability to connect anywhere and anytime has led to the increasing use of Digital Electronics in
homes, in offices, on the roads, and almost everywhere. Data intensive applications such as streaming
media and two-way video-chat have further fueled the need for higher data-rates. Several faculties in our
group have multiple projects related to wireless networking. Our focus is to design reliable, robust,
higher data-rate, spectrally efficient, and secure network services and architectures for tomorrow. Some
of the key research topics studied are as follows: full-duplex Digital Electronics, resource allocation,
mobility, medium access control, vehicular networks, wireless local-area networks, cognitive radios,
cellular networks, sensor and actuator networks, cross-layer design, scaling laws, and wireless security.

b). Relevance to Society:

Digital Electronics have enabled the connection of billions of people to the Internet so that they
can reap the benefits of today’s digital economy. Similarly, agreed standards for mobile phones
 allow people to use their devices everywhere in the world. Nearly every sector of the economy
now relies upon wireless technologies in fundamental ways – from banking and agriculture to
transportation and healthcare. And powerful new technologies that rely on robust Digital
Electronics networks – such as 5G, artificial intelligence and Internet of Things – hold great
promise to improve lives at an unprecedented pace and scale. Indeed, they have potential to
accelerate progress towards achieving each of the 17 United Nations Sustainable Development
Goals (SDGs).

c). Relevance to Self:

This subject has its own importance, for the personal growth this is must to have the knowledge
of wireless, every core company required knowledgeable Computer engineers. Right now, this is
the only sector which is touching sky-heights. There are many more projects in which students
can be imparted and in spite of that many research projects are going on to make the system.

d). Relation with lab: - In labs we learn to do initialize the basic gate and conversion of gates.

6). Syllabus of Rajasthan Technical University, Kota

a.) Index Terms/ Key Words: Logic Gates, Number System, Boolean Algebra, Combinational Circuit,
Sequential Circuits
b.) RTU Syllabus with Name of Subject & Code: Digital Electronics (3CS3-04)

UNIT I: Objective, scope and outcome of the course.

UNIT II: Fundamental concepts:

Number systems and codes, Basic logic Gates and Boolean algebra: Sign & magnitude representation,
Fixed point representation, complement notation, various codes & arithmetic in different codes & their
inter conversion. Features of logic algebra, postulates of Boolean algebra. Theorems of Boolean algebra.

UNIT III: Minimization Techniques and Logic Gates:

Principle of Duality - Boolean expression -Minimization of Boolean expressions –– Minterm – Maxterm

- Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don’t care
conditions – Quine – Mc-Cluskey method of minimization.

UNIT IV: Digital Logic Gate Characteristics:

TTL logic gate characteristics. Theory & operation of TTL NAND gate circuitry. Open collector TTL.
Three state output logic. TTL subfamilies.MOS& CMOS logic families. Realization of logic gates in
RTL, DTL, ECL, C-MOS & MOSFET.

UNIT V: Combinational Circuits:

Combinational logic circuit design, adder, Subtractor, BCD adder, encoder, decoder, BCD to 7-segment
decoder, multiplexer, demultiplexer

UNIT VI: Sequential Circuits:

Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation, counters and their
design, Synchronous counters – Synchronous Up/Down counters – Programmable counters – State table
and state transition diagram ,sequential circuits design methodology. Registers –shift registers.
ABC analysis (RGB method) of unit & topics :-

Unit A B C Preparedness
No. (Hard Topics) (Topics with average hardness (Easy to understand for ‘A’ topics
level) topics)
Features of logic algebra, Fixed point representation, Fundamental concepts:
postulates of Boolean algebra. complement notation, various Number
Theorems of Boolean algebra codes & arithmetic in different systems and codes, PPT
I codes & their inter conversion, Basic logic Gates and
Boolean algebra:
Sign &
magnitude
representation
Minimization of Boolean Minimization Techniques Quine - McCluskey
expressions –– Minterm – and Logic Gates: Principle of method of
Maxterm - Sum of Products Duality Minimization. PPT
II (SOP) – Product of Sums - Boolean expression
(POS) – Karnaugh map
Minimization – Don’t care
conditions
Open collector TTL. Three Digital Logic Gate Characteristics: Realization of logic
III state output logic. TTL TTL logic gate gates in RTL, DTL, Video
subfamilies. MOS& CMOS Characteristics. Theory & ECL,C-MOS& Lecture,
logic families. operation of TTL NAND gate MOSFET PPT
circuitry.
BCD to 7-segment BCD adder, encoder, decoder, Combinational logic Video
IV decoder, multiplexer, circuit design, adder, Lecture,
demultiplexer. subtractor, PPT
Sequential Circuits: Latches, Synchronous counters– Sequential circuits
Flip- flops - SR, JK, D, T, and Synchronous Up/Down counters – design methodology. Video
V Master- Slave Characteristic Programmable countersState Registers –shift
table and equation, counters tableand state transition diagram, registers. Lecture
and their design
7.) Books/ Website/Journals & Handbooks/ Association & Institution:

a.) Recommended Text & Reference Books and Websites:-

S. No. Title of Book Authors Publisher No. of books in

Library

Text Books

T1 Digital Logic Circuit S. SALIVAHANAN PHI 65

T2 Digital Electronics V.K. JAIN, AARTI Genius 32
AGARWAL Publication
Reference Books

TNH
R1 Digital Logic Design M.MORRIS MANO R1
Websites related to subject

1 https://nptel.ac.in/courses/117/106/117106114/ Web
2 https://nptel.ac.in/courses/117/106/117106086/ Videos
b). Journals: -

1 IEEE communication system magazine ( international ) www.ieee.explore.com

2 Institute of Engineers (national) www.ie.org.in
3 IETE publications
c). Association and Institution: -

1)IETE

2)IEEE

8). Syllabus Deployment: - Total no of Lectures: - 40

Unit 1: Fundamental concepts - 10 lectures

Unit 2: Minimization Techniques and Logic Gates - 8 lectures
Unit 3: Digital Logic Gate Characteristics - 7 lectures
Unit 4: Combinational Circuits - 7 lecture
Unit 5: Sequential Circuits - 8 lectures
a.) Special Activities (To be approved by HOD, Dean & Campus Director & must be mentioned in
deployment):
Open Book Test- Once in a semester
Quiz (100% Technical)- One in a semester
Special Lectures (SPL)- 10% of total no. of lectures including following
i. Few PPT Lecture
Revision classes:- 1 to 3 turn at the end of semester (Before II Mid Term Exam)
Solving Important Question Bank- 1 Turn before I & II Mid Term Exam (each) - Total Two
turn. b.) Lecture schedule per week:
i). University scheme (L+T+P) = 2L+T+0P

ii). PGC scheme (L+T+P) = 3L+0T+0P

c.) Introduction & Conclusion: Each subject, unit and topic shall start with introduction & close with
conclusion.

d.) Time Distribution in lecture class: - Number of chapters is beginning with objective and end of
course/chapter/lecture with summary and quiz (Time allotted: 60 min.)
First 5 min. should be utilized for paying attention towards students who were absent for last
lecture or continuously absent for many days + taking attendance by calling the names of the
students and also sharing any new/relevant information.
Actual lecture delivery should be of 45 minutes
Last 5 min. should be utilized by recapping of the topic. Providing brief introduction of the
coming up lecture and suggesting portion to read.
After completion of any Unit/Chapter a short quiz should be organized
During lecture student should be encouraged to ask the question.

11). University Examination systems: -

Sr. Name of the exam Max. passing Nature of paper Syllabus Conducted
No. Marks marks Coverage by
1. I Mid Term Exam 60 24 40% Theory + 60% 60% PCE
Numerical
2. II Mid Term Exam 60 24 40% Theory + 60% 40% PCE
Numerical
3. University (End)Term 70 25 40% Theory + 60% 100% RTU
exam Numerical

Place: - Jaipur Prof. (Dr.) Rajesh Kumar Bathija

Date: - 05 August 2024 Professor, CS Department

 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING

Campus: Poornima College of Engineering Year/Section: IInd Date: 05 Aug 2024

Course: B. Tech. Semester/ Section –III F
Name of Faculty: Dr. Rajesh Kumar Bathija Name of Subject : Digital Electronics Code: 3CS3-04

COURSE PLAN –BLOWN UP

SNo. TOPIC AS PER SYLLABUS BLOWN UP TOPICS ( up to 10 Times Syllabus)
1. Zero Lecture Introduction to the subject and its significance.
2. Unit -1 1.1 Number system
1.1.1 Decimal numbers
Fundamental concepts: Number 1.1.2 Binary numbers
systems and codes, Basic logic Gates 1.1.3 Octal numbers
and Boolean algebra: Sign & 1.1.4 Hexadecimal numbers
magnitude representation, Fixed 1.2 Conversion between Numbers
point representation, complement 1.2.1 Decimal conversion
notation, various codes & arithmetic 1.2.2 Binary conversion
in different codes & their inter 1.2.3 Octal conversion
conversion. Features of logic algebra, 1.2.4 Hexadecimal conversion
postulates of Boolean algebra. 1.3 Application of Number system, Arithmetic Operation of different
Theorems of Boolean algebra. number system
1.3.1 Addition
1.3.2 Subtraction
1.3.3 Multiplication
1.3.4 Division
1.4 Radix Representation Radix Complement
1.4.1 Diminished Radix Complement (R-1)’s
1.4.2 Simple Radix Complement R’s
1.4.3 Subtraction using complements
1.4.4 Sign & Magnitude Representation
1.5 Fixed Point Representation
1.6 Floating Point Representation
1.7 Coding scheme and arithmetic in different codes and inter
conversion
1.7.1 Introduction to codes scheme
1.7.2 Introduction to codes
1.7.3 BCD Weighted binary codes
1.7.3.1 BCD addition
1.7.3.2 BCD subtraction
1.7.3.3 Different BCD Codes
1.7.4 Excess -3 code
1.8 Non-weighted binary codes
1.9 Gray code
1.9.1 Conversion of binary to gray
1.9.2 Conversion of gray to binary
1.10 Error detecting code
1.10.1 Parity check
1.10.2 Check sum
1.11 Error Correcting code
1.11.1 Hamming Code Alphanumeric code
1.12 Logic and Boolean algebra
1.12.1 Logic Operation
1.12.2 Logical AND operation
1.12.3 Logical OR operation
1.12.4 Logical complementation
1.13 Laws of Boolean Algebra
 1.13.1 Boolean addition
1.13.2 Boolean Multiplication
1.13.3 Fundamental theorems
1.13.4 Properties of Boolean Algebra
1.13.5 Principle of duality
1.13.6 Demorgan’s theorem
1.14 Boolean Functions
1.14.1 Simplification of Boolean expressions
1.14.2 Logic gates and their truth table and Symbols
Introduction
1.15 Basic gate
1.15.1 OR Gate Symbol Truth table
1.15.2 AND gate Symbol Truth table
1.15.3 NOT gate Symbol Truth table
1.15.4 Ex-or gate Symbol Truth table
1.15.5 Ex-nor gate Symbol Truth table
1.16 Universal gate
1.16.1 NAND gate Symbol Truth table
1.16.2 NOR gate Symbol Truth table
1.17 Conversion of Logic Diagrams from Boolean expression Using
Basic Gate
1.18 Using Universal Gates Positive, Negative and Mixed Gate Basic
Operation

3. Unit -2 2.1 Designation of functions

2.1.1 Minterm
Minimization Techniques and Logic 2.1.2 Maxterm
Gates: Principle of Duality - Boolean 2.2 Simplification of functions on Karnaugh map
expression -Minimization of Boolean 2.2.1 Two variable
expressions –– Minterm – Maxterm - 2.2.2 Three variable
Sum of Products (SOP) – Product of 2.2.3 Four variable
Sums (POS) – Karnaugh map 2.2.4 Five variable
Minimization – Don’t care conditions 2.3 Conversion of truth tables in POS and SOP form
– Quine - McCluskey method of 2.3.1 Sum of product ( SOP)
minimization. 2.3.2 Product of sum (SOP)Algebraic methods
2.4 Incompletely specified functions
2.5 Don’t care combinations
2.6 Cubical representation of Boolean functions
2.7 Determination of prime Implicants
2.8 Quine – Mc Clunskey method
2.9 Selection of an optimal set of prime implicants
2.9.1 Multiple output circuits and map minimization of
multiple output circuit
2.9.2 Tabula determination of multiple output prime implicant

4. Unit-3 3.1 Logic Families

3.1.1 Introduction Types
Digital Logic Gate Characteristics: 3.1.2 Bipolar Logic Families
TTL logic gate characteristics. Theory 3.1.3 MOS Families
& operation of TTL NAND gate 3.2 Characteristics of Digital ICs
circuitry. Open collector TTL. Three 3.3 Current Sourcing and Sinking Logic
state output logic. TTL 3.4 RTL Circuit Characteristics
subfamilies.MOS& CMOS logic 3.5 RCTL Circuit Characteristics
families. Realization of logic gates in 3.6 DTL Circuit Characteristics
RTL, DTL, ECL, C-MOS & 3.7 HTL Circuit Characteristics
MOSFET. 3.8 TTL Circuit description of TTL NAND gate
3.8.1 Theory and Operation
3.8.2 Open collector TTL and three state output logic
3.8.3 TTL NAND gate
3.8.4 Other TTL series
3.8.5 TTL OR/AND/NOR gate and Inverter
3.9 ECL Circuit Characteristics
3.10 MOS Digital Integrated Circuits
 3.10.1 MOSFET
3.11 CMOS Logic Circuit
3.12 CMOS Invertors
3.13 CMOS NAND/NOR
3.14 Characteristics of CMOS
3.15 Comparison b/w TTL and CMOS

4. Unit : 4 4.1 Introduction of Combinational Circuits

4.2 Adder
Combinational Circuits: 4.2.1 Half Adder
Combinational logic circuit design, 4.2.2 Full Adder
adder, subtractor, BCD adder, 4.2.3 4- bit serial Adder
encoder, decoder, BCD to 7-segment 4.2.4 4-bit Parallel/Adder
decoder, multiplexer, demultiplexer. 4.2.5 Fast and BCD Adder
4.3 Subtractor
4.3.1 Half Subtractor
4.3.2 Full Subtractor
4.3.3 4-bit Parallel Subtractor
4.3.4 4-bit Serial Subtractor
4.4 Decoder
4.4.1 Basic Binary Decoder
4.4.2 3-to-8 Decoder & 4-to-16 Decoder
4.4.3 Binary to Gray Decoder
4.4.4 BCD to 7 Segment Decoder
4.4.5 Dual 2-to-4 Decoder
4.4.6 Binary to Decimal Decoder
4.4.7 Implementation of Higher Order Decoders Using Lower
Order Decoders
4.5 Encoder
4.5.1 Octal-to-Binary Encoder
4.5.2 Decimal-to-BCD Encoder
4.5.3 BCD to excess-3 Encoder
4.5.4 Priority Encoder
4.6 Multiplexer
4.6.1 Basic 4-input Multiplexer
4.6.2 8-to-1 Multiplexer
4.6.3 16-to-1 Multiplexer
4.6.4 Implementation Of Higher Order Multiplexer
Implementation of sequential circuit using mux
4.7 Demultiplexer
4.7.1 Introduction
4.7.2 1-to-4 and 1-to-8 Demultiplexer
4.7.3 1-to-16 Demultiplexer
4.8 Design Of Combinational Circuit Using Multiplexer
4.9 Implementation Of Boolean Expressions Using Multiplexers
6. Unit-5 5.1 Latches
5.1.1 Introduction
Sequential Circuits: Latches, Flip- 5.1.2 Basic SR Latch and D Latch
flops - SR, JK, D, T, and Master-Slave 5.1.3 State Diagram and Characteristic Equations
Characteristic table and 5.2 Flip Flops
equation,counters and their design, 5.2.1 Introduction
Synchronous counters – Synchronous 5.2.2 Characteristics equations truth table and State Diagram
Up/Down counters – Programmable 5.3 RS Flip Flop
counters – State table and state 5.3.1 NAND and NOR based RS Flip Flop
transition diagram ,sequential circuits 5.3.2 Characteristics equations truth table and State Diagram
design methodology. Registers –shift 5.4 D Flip Flop
registers. 5.4.1 Relation to Latch
5.4.2 Characteristics equations truth Table and State Diagram
5.5 J-K Flip Flop
5.5.1 JK using SR Flip Flop
5.5.2 Characteristics equations truth table and State Diagram
5.6 T Flip Flop
5.6.1 Toggling
5.6.2 Characteristics equations truth table and State Diagram
5.7 Pulse Mode Sequential Circuits
 5.7.1 Positive Edge Triggering
5.7.2 Negative Edge Triggering
5.7.3 Level Mode Sequential Circuits
5.7.4 Positive Edge Triggering
5.7.5 Negative Edge Triggering
5.8 Master Slave Flip Flop
5.8.1 Introduction
5.8.2 Race Around Condition
5.8.3 Prevention
5.8.4 Clock Driven Sequential Circuits
5.9 Realization Of One Flip-Flop From Other Flip-Flop
5.10 Analysis of Clocked Sequential circuit
5.11 State Reduction and Assignment
5.12 Application Of Flip-Flop
5.12.1 Parallel Data Storage
5.12.2 Shift Register
5.12.3 Frequency Division
5.12.4 Counters
5.12.5 Mealy and Moore Machines
5.13 Counters
5.13.1 Introduction to Counters
5.13.2 Asynchronous(Ripple) Counter
5.13.3 Ripple Counter with Modulus
5.13.4 Asynchronous Down Counter
5.13.5 Asynchronous Up-down Counter
5.13.6 Propagation delay in Ripple Counter
5.13.7 Synchronous(Parallel)Counter
5.13.8 Synchronous Down Counter
5.13.9 Synchronous(Up-down) Counter
5.13.10 Programmable Counters
5.14 Design of Synchronous Counter
5.15 MOD-3 and MOD-6 Counter
5.16 BCD or Decade (MOD-10) Counter
5.17 MOD-8 Up-Down Counter
5.18 Design Using Flip Flops
5.19 Counter Implementation And Application
5.20 Skipping State Counter
5.21 Register
5.21.1 Introduction to Registers
5.21.2 4-bit Shift Register
5.21.3 Shift Register
5.21.4 Serial-in-Serial out
5.21.5 Serial-in-Parallel out
5.21.6 Parallel-in-Serial out
5.21.7 Parallel-in-Parallel out
5.22 Universal Shift Register
5.23 Shift Register Counter
5.24 Ring Counter Shift(Johnson) Counter
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
DEPARTMENT OF COMPUTER ENGINEERING
Campus: Poornima College of Engineering Year/Section: 2nd Date: 05 Aug 2024
Course: B. Tech. Semester/ Section – III F
Name of Faculty: Dr. Rajesh Kumar Bathija Name of Subject : Digital Electronics Code: 3CS3-04

COURSE PLAN (Deployment)

Ref.
Lecture Topics, Problems, Applications CO/LO Target Date Actual Date Book/Journal
No. of Coverage of Coverage with Page
No.

1 Zero lecture

Number system , Decimal numbers, Binary

2 numbers, Octal numbers, Hexa decimal numbers, CO1 T1-1-6
Conversion between Numbers, Decimal conversion,
Binary conversion
Octal conversion, Hexa decimal conversion,
3 Application of Number system, Arithmetic CO2 T1 8-17
Operation of different number system, Addition,
Subtraction, Multiplication, Division
Radix Representation Radix Complement,
3 Diminished Radix Complement (R-1)’s, Simple CO1 R1 13
Radix Complement R’s, Subtraction using
complements,
Sign & Magnitude Representation, Fixed Point
Representation, Floating Point Representation
4 Coding scheme and arithmetic in different codes CO2 T1 20-21

and inter-conversion, Introduction to codes scheme,

Introduction to codes, BCD Weighted binary codes,
BCD addition, BCD subtraction, Different BCD
Codes, Excess -3 code, Non-weighted binary codes
Gray code, Conversion of binary to gray,
Conversion of gray to binary, Error detecting code,
Parity check, Check sum, Error Correcting code,
4 Hamming Code Alphanumeric code CO1 T1 25
Logic and Boolean algebra, Logic Operation,

Logical AND operation, Logical OR operation,

Logical complementation
Laws of Boolean Algebra, Boolean addition,
5 Boolean Multiplication, Fundamental theorems, CO2 T1 39-44
Properties of Boolean Algebra, Principle of duality,
Demorgan’s theorem
Boolean Functions, Simplification of Boolean
6 expressions CO2 T1 77-83

Logic gates and their truth table and Symbols

Introduction, Basic gate, OR Gate Symbol Truth
 table, AND gate Symbol Truth table, NOT gate
Symbol Truth table, Ex-or gate Symbol Truth table,
Ex-nor gate Symbol Truth table
Universal gate, NAND gate Symbol Truth table,
6 NOR gate Symbol Truth table, Conversion of Logic CO1 T1 82-84
Diagrams from Boolean expression Using, Basic
Gate, Using Universal Gates Positive, Negative and
Mixed Gate Basic Operation
7 Designation of functions, Min-term, Max-term,
Simplification of functions on Karnaugh-map, Two- CO2 T1 50
variable, Three variable, Four variable , Five-
variable
Conversion of truth tables in POS and SOP form
Sum of product (SOP) Product of sum (SOP)
8 Algebraic methods CO2 T1 55
Incompletely specified functions
Don’t care combinations, Cubical representation of
Boolean functions
9 Determination of prime Implicants CO1 T1 64
Quine – Mc Clunskey method, Selection of an
optimal set of prime implicants
9 Determination of prime Implicants CO2 T1 67
Quine – Mc Clunskey method, Selection of an
optimal set of prime implicants
10 Multiple output circuits and map minimization of CO2 R1 51
multiple output circuit, Tabula determination of
multiple output prime implicant
10 Logic Families, Introduction Types, Bipolar Logic CO3 T1 113
Families, MOS Families
11 Class Test -1 All CO

Characteristics of Digital ICs, Current Sourcing

12 and Sinking Logic, RTL Circuit Characteristics, CO3 T1 114
RCTL Circuit Characteristics, DTL Circuit
Characteristics

HTL Circuit Characteristics, TTL Circuit

12 description of TTLNAND gate, Theory and CO3 T1 121-123
Operation, Open collector TTL and three state
output logic, TTL NAND gate
13 Other TTL series, TTL OR/AND/NOR gate and CO3 T1 134-138
Inverter, ECL Circuit Characteristics, MOS Digital
Integrated Circuits
13 MOSFET, CMOS Logic Circuit, CMOS Invertors, CO3 T1 140-147
CMOS NAND/NOR, Characteristics of CMOS,
Comparison b/w TTL and CMOS
Introduction of Combinational Circuits, Adder, Half T1 161-163,
14 Adder, Full Adder, 4- bit serial Adder 4- CO4 T1 168, 178
bitParallel/Adder, Fast and BCD Adder, Subtractor,
Half Subtractor T1 165
Full Subtractor
14 4-bit Parallel Subtractor, 4-bit Serial Subtractor, CO2 T1 172
Decoder, Basic Binary Decoder
3-to-8 Decoder & 4-to-16Decoder, Binary to Gray T1 205-207
15 CO4
Decoder, BCD to 7 Segment Decoder, Dual 2-to-
T1 213
4Decoder
 Binary to Decimal Decoder, Implementation of
16 Higher Order Decoders Using Lower Order, CO3 T1 210-212
Decoders Encoder, Octal-to-Binary Encoder,
Decimal-to-BCD Encoder
BCD to excess-3 Encoder, Priority Encoder, R1 139
17 CO4
Multiplexer, Basic 4-inputMultiplexer, 8-to-1
T1 223
Multiplexer, 16-to-1 Multiplexer
Implementation Of Higher Order Multiplexer,
Implementation of sequential circuit using mux,
Demultiplexer Introduction
19 1-to-4 and 1-to-8Demultiplexer CO4 T1 192-193

1-to-16Demultiplexer, Design Of Combinational

Circuit Using Multiplexer
Implementation Of Boolean Expressions Using
Multiplexers
Latches, Introduction, Basic SR Latch and D Latch,
State Diagram and Characteristic Equations, Flip
22 Flops, Introduction, Characteristics equations truth CO3 T1 255-260
table and State, Diagram, RS Flip Flop, NAND and
NOR based RS Flip Flop, Characteristics equations
truth table and State Diagram
D Flip Flop, Relation to Latch, Characteristics
equations truth Table and State Diagram, J-K Flip
Flop, JK using SR Flip Flop, Characteristics
equations truth table and State Diagram, T Flip Flop
23 Toggling, Characteristics equations truth table and CO4 T1 263-273
State Diagram Pulse Mode Sequential Circuits,
Positive Edge Triggering, Negative Edge
Triggering, Level Mode Sequential Circuits,
Positive Edge Triggering
Negative Edge Triggering
Master Slave Flip Flop, Introduction
23 Race Around Condition Prevention CO2 T1 275-284
Clock Driven Sequential Circuits, Realization Of
One Flip-Flop From Other Flip-Flop, Analysis of
Clocked Sequential circuit
State Reduction and Assignment Application Of
24 Flip-Flop, Parallel Data Storage, Shift Register, CO3 T1 286-288
Frequency Division, Counters, Mealy and Moore
Machines
Counters, Introduction to Counters,
Asynchronous(Ripple) Counter Ripple Counter with
24 Modulus, Asynchronous Down Counter, CO4 T1 293-309
Asynchronous Up-down Counter, Propagation delay
in Ripple Counter, Synchronous(Parallel)Counter,
Synchronous Down Counter, Synchronous(Up-
down)Counter, Programmable Counters
Design of Synchronous Counter, MOD-3 and
25 MOD-6Counter, BCD or Decade(MOD-10) CO3 T1 311-324
Counter, MOD-8 Up-Down Counter, Design Using
Flip Flops
Counter Implementation And Application, Skipping T1 336-338
26 CO4
State Counter, Register, Introduction to Registers,
T1 345
4-bit Shift Register, Shift Register
26 Serial-in-Serial out, Serial-in-Parallel out Parallel- CO4 T1 347-358
in-Serial out, Parallel-in-Parallel out, Universal
Shift Register
27 Shift Register Counter, Ring Counter CO4 T1 361-368
Shift(Johnson)Counter
 Coverage of Units by lectures
Presentation
Solving Numerical Problem
Assignments

Study material

Textbook:

T1) S Salivahanan, S Arivazhagan: Digital Circuits and Design: ISBN 978-81-259-2063, Vikas Publishing
House Pvt. Ltd..

Reference books:

R1) M Morris Mano: Digital Design: ISBN 81-7808-837-1, Pearson Education Asia.
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR DEPARTMENT OF COMPUTER ENGINEERING
Campus: Poornima College of Engineering Year/Section: IInd Date: 05 Aug 2024
Course: B. Tech. Semester/ Section – III-F
Name of Faculty: Dr. Rajesh Kumar Bathija Name of Subject : Digital Electronics Code: 3CS3-04

COURSE OUTCOME

3CS3-04.1: Able to understand different coding and number system and its applications.

3CS3-04.2: Understand the basic concepts of logic gates and minimize the circuit by using the different
Boolean algebra.

3CS3-04.3: Analyze the various logic families and Interfacing between digital and analog components.
3CS3-04.4: Able to design various combinational circuits & sequential circuits.

CO-PO-PSO Mapping: Mapping Levels: 1- Low, 2- Moderate, 3-Strong

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

CO1 2 - - - - - - - - - - - 2 - -

CO2 - 2 - - - - - - - - - - 2 - -

CO3 - - 2 - - - - - - - - - 2 - -

CO4 - - 2 - - - - - - - - - - 2 -

CO-PO MAPPING JUSTIFICATION

CO1 PO1 2 Able to understand different coding and number system and its applications.
Understand the basic concepts of logic gates and minimize the circuit by using the
CO2 PO2 2 different Boolean algebra.
3CS3-04
CO3 PO3 2 Analyze the various logic families and Interfacing between digital and analog
components.
CO4 PO3 2 Able to design various combinational circuits & sequential circuits.

CO-PSO MAPPING JUSTIFICATION

3CS3-04 CO1 PSO1 2

Able to understand different coding and number system and its applications.
CO2 PSO1 2 Understand the basic concepts of logic gates and minimize the circuit by To Recognize m
using the different Boolean algebra. circuits.

CO3 PSO1 2 Analyze the various logic families and Interfacing between digital and analog To Design comb
components.
energy dissipatio

CO4 PSO2 2 Able to design various combinational circuits & sequential circuits. To Evaluate the
 POORNIMA COLLEGE OF ENGINEERING, JAIPUR
II B.TECH. (III Sem.) Roll No. __________________
FIRST MID TERM EXAMINATION 2024-25 Code: 3CS3-04 Category: PCC Subject Name–
Digital Electronics (BRANCH – COMPUTER ENGINEERING)
Max. Time: 2 hrs. Course Credit: 3 Max. Marks: 60
Instructions to the candidate:
Figures to the right indicate full marks.
Usage of non-programmable calculator is permitted.
Draw neat sketches and diagram wherever is necessary.
Course Outcomes (CO):
At the end of the course the student should be able to:

CO-1: Able to understand different coding and number system and its applications.
CO2: Understand the basic concepts of logic gates and minimize the circuit by
using the different Boolean algebra.
CO3: Analyze the various logic families and Interfacing between digital and analog
components.
CO4: Able to design various combinational circuits & sequential circuits.

PART - A: (All questions are compulsory) Max. Marks (10)

Q. Questions Mark C B P PI
No. s O L O
Q. 1 (49.75)10 = (__________)2 = (___________)16 2 1 4 2 1.1.2

Q. 2 Draw symbols and truth tables of AND gate, Ex- 2 2 1 1 1.1.1

OR and NOR gate

Q. 3 Perform (1011000)2 – (1001000)2 using 2’s 2 1 5 2 1.1.2

complement.

Q. 4 (196)10 = (____________)BCD = (_________) Ex-3 2 1 4 2 1.1.2

Q. 5 List the characterics of TTL family. 2 3 1 1 1.1.1

PART - B: (Attempt 4 questions out of 6) Max. Marks (20)
Q. 6 Convert the following into canonical SOP form 5 3 2 2 1.1.3
Y = (A+C’+D’) (A’+C’) (B’+D’)

Page 1 of 3
Q. 7 Explain 3 input TTL Nand gate circuit. 5 3 1 1 1.1.1

Q. 8 Explain Consensus, Absorption and Distributive 5 3 1 1 1.1.1

property of Boolean algebra.

Q. 9 Simplify using K-Map f(x,y,z)= ∑m(1,3,4,6) 5 1 5 2 1.1.4

Q. 10 Using absorption theorem simplify following 5 2 4 1 1.1.4

AB’C+(B’+C’)(B’+D’)+(A+C+D)’

Add and multiply following numbers without

Q. 11 converting them into decimal 5 2 3 4 1.1.4
a) Binary numer 1011 and 101
b) Hexadecimal number 2E and 34.
PART - C: (Attempt 3 questions out of 4) Max. Marks (30)
Reduce the following function using K’map and
implement logical circuit using NOR only
Q. 12 F(A,B,C,D)= ΠM (1,2,5,6,8,9,12,13,15) * 10 3 6 2 1.1.4

d(0,3,7,14)

Reduce the following function using K’map and

Q. 13 Draw circuit using NAND gate 10 3 6 2 1.1.4

F(A,B,C,D)= ∑m(1,2,5,9,10,12,13, 14,15)

Simplify using tabular method and draw a

Q. 14 digital circuit for the following equation. 10 2 6 2 1.1.4
F = ∑m(0,2,6,10,11,12,13)

Prove the following using Boolean Theorems:

Q. 15 a) (A+C)(A+D)(B+C)(B+D)=AB+CD 10 2 5 2 1.1.3
b) (A’+B’+D’)(A’+B+D’)(B+C+D)(A+C’
+D)(A+C’)=A’C’D+ACD’+BC’D’
Page 2 of 3
 BLOOM's LEVEL COURSE OUTCOME WISE
WISE MARKS MARKS DISTRIBUTION
40 37
DISTRIBUTION 32
30
23%

RKS
MA
L1
20
L2 11
50% 8% L3 10
8% L4 0
L5
L6 0
15%
CO1 CO2 CO3 CO4
28%
COs

BL – Bloom’s Taxonomy Levels (1- Remembering, 2- Understanding, 3 – Applying, 4 –

Analyzing, 5 – Evaluating, 6 - Creating)
CO – Course Outcomes; PO – Program Outcomes

Page 3 of 3
Number Systems
Overview

▶ Introduction

▶ Number Systems [binary, octal and hexadecimal]

▶ Number System conversions

Introduction

Number System
Code using symbols that refer to a number of items

Decimal Number System

Uses ten symbols (base 10 system)

Binary System
Uses two symbols (base 2 system)

Octal Number System

Uses eight symbols (base 8 system)

Hexadecimal Number System

Uses sixteen symbols (base 16 system)
 Binary Number

• Numeric value of symbols in different positions.

• Example - Place value in binary system:
Place Value 8s 4s 2s 1s

Binary Yes Yes No No

Number 1 1 0 0

RESULT: Binary 1100 = decimal 8 + 4 + 0 + 0 = decimal 12

BINARY TO DECIMAL CONVERSION

Convert Binary Number 110011 to a Decimal Number:

Binary 1 1 0 0 1 1

Decimal 32+16+0+0+2+1=51
 TEST
Convert the following binary
numbers into decimal numbers:
Binary 1001 =
Binary 1111 =
Binary 0010 =
 TEST
Convert the following binary
numbers into decimal numbers:
Binary 1001 = 9
Binary 1111 = 15
Binary 0010 = 2
DECIMAL TO BINARY CONVERSION

Divide by 2 Process

Decimal # 13 ÷ 2 = 6 remainder 1

6 ÷ 2 = 3 remainder 0

3 ÷ 2 = 1 remainder 1

1 ÷ 2 = 0 remainder 1

1 1 0 1
 TEST

Convert the following decimal

numbers into binary:
Decimal 11 =
Decimal 4 =

Decimal 17 =
 TEST

Convert the following decimal

numbers into binary:
Decimal 11 = 1011

Decimal 4 = 0100

Decimal 17 = 10001
HEXADECIMAL NUMBER SYSTEM

Uses 16 symbols -Base 16 System, 0-9, A, B, C, D, E, F

Decimal Binary Hexadecimal
0 0000 0
1 0001 1
2 0010 2
3 0011 3
4 0100 4
5 0101 5
6 0110 6
7 0111 7
8 1000 8
9 1001 9
10 1010 A
11 1011 B
12 1100 C
13 1101 D
14 1110 E
15 1111 F
16 0001 0000 10
HEXADECIMAL AND BINARY CONVERSIONS

• Hexadecimal to Binary Conversion

Hexadecimal C 3

Binary 1100 0011

• Binary to Hexadecimal Conversion

Binary 1110 1010

Hexadecimal E
A
DECIMAL TO HEXADECIMAL CONVERSION

Divide by 16 Process

Decimal # 47 ÷ 16 = 2 remainder 15

2 ÷ 16 = 0 remainder 2

2 F
HEXADECIMAL TO DECIMAL CONVERSION

Convert hexadecimal number 2DB to a decimal number

Place Value 256s 16s 1s

Hexadecimal 2 D B

(256 x 2) (16 x 13) (1 x 11)

Decimal 512+ 208 +11=

731
 TEST
Convert Hexadecimal number A6 to Binary

A6 = Translate every hexadecimal digit into

1010 0110 ▶
its 4-bit binary equivalent
(Binary)
▶ Examples:
Convert Hexadecimal number 16 to Decimal = (0011 1010 0101)2
(3A5)16
(12.3D)16 = (0001 0010 . 0011 1101)2
16 = 22
(1.8)16 = (0001 . 1000)2
(Decimal)

Convert Decimal 63 to Hexadecimal

63= 3F
(Hexadecimal)
OCTAL NUMBERS

Uses 8 symbols -Base 8 System

0,1,2,3,4,5,6,7
Decimal Binary Octal
0 000 0
1 001 1
2 010 2
3 011 3
4 100 4
5 101 5
6 110 6
7 111 7
8 001 000 10
9 001 001 11
 OCTAL AND BINARY CONVERSIONS

• Octal to Binary Conversion

Octal 5 6
Binary 101 110

• Binary to Octal Conversion

Binary 100 101
Octal 4 5
DECIMAL TO OCTAL CONVERSION

Divide by 8 Process

Decimal # 129 ÷ 8 = 16 remainder 1

16 ÷ 8 = 2 remainder 0

2 ÷ 8 = 0 remainder 2

20 1
 OCTAL TO DECIMAL CONVERSION

Convert octal number 201to a decimal number

Place Value 64s 8s 1s

Octal 2 0 1

(64 x 2) (8 x 0) (1 x 1)

Decimal 128+ 0 + 1=
129
Convert 0.101112 to base 8: 0.101_110 = 0.568
Convert 0.1110101 to base 16: 0.1110_1010 = 0.EA16
Arithmetic Operations
Overview

▶ Arithmetic Operations
▶
Decimal Arithmetic
▶
Binary Arithmetic
▶
Signed Binary Numbers
Arithmetic Operations

Addition
▶ Follow same rules as in decimal addition, Carry 1 1 1 1 1 0
with the difference that when sum is 2
indicates a carry (not a 10) Augend 0 0 1 0 0 1
▶ Learn new carry rules
Addend 0 1 1 1 1 1
▶ 0+0 = sum 0 carry 0 Result 1 0 1 0 0 0
▶ 0+1 = 1+0 = sum 1carry 0
▶ 1+1 = sum 0 carry1 111 Carry Values
0101
▶ 1+1+1 = sum 1carry1 + 1011
10000
 Subtraction
▶ Learn new borrow rules
Borrow 1 10 0
▶ 0-0 = 1-1 = 0 borrow 0
▶ 1-0 = 1 borrow 0 Minuend 1 10 1 1
▶ 0-1 = 1 borrow 1 Subtrahend 0 11 0 1
Result 0 11 1 0
The rules of the decimal base applies to binary 12
as well. To be able to calculate 0-1, we have 0202
to “borrow one” from the next left digit. 10 1 0
- 0111
0011
 Decimal Subtraction

▶ 9’s Complement Method

▶
10’s Complement Method 72532
9’s Complement Method + 96749
Example: 72532 – 3250 1 69281
9’s complement of 3250 is +1
99999–03250=96749 If Carry, result is positive. 69282
Add carry to the partial result

Example: 3250 – 72532 03250 +27467

9’s complement of 72532 is 30717 =
–69282
9 9 9 9 9 – 7 2 5 3 2 = 2 7 4 6 7If no Carry, result is negative. Magnitude
is 9’s complement of the result
 Decimal Subtraction

▶ 9’s Complement Method

72532
▶ 10’s Complement Method
10’s Complement Method + 96750
Example: 72532 – 3250 1 69282
10’s complement of 3250 is Result is 6 9 2 8 2
100000–03250=96750 If Carry, result is positive.
Discard the carry

7468 If no Carry,
Example: 3250 – 72532 result is negative.
Magnitude is 10’s
10’s complement of 72532 is complement of
the result
 03250
+ 27468
30718
= –69282
 Binary Subtraction

▶ 1’s Complement Method

▶ 2’s Complement Method 1010100
1’s Complement Method + 0111011
1 0001111
Example: 1010100 – 1000100
+1
1’s complement of 1000100 is 0111011 0010000
If Carry, result is positive.
Add carry to the partial result

Example: 1000100 – 1010100 1 000100

1’s complement of 1010100 is 0101011 + 0101011
If no Carry, result is negative. 1 101111
Magnitude is 1’s complement of the result
= –0010000
 Binary Subtraction

▶ 1’s Complement Method

▶ 2’s Complement Method 1010100
2’s Complement Method + 0111100
1 0010000
Example: 1010100 – 1000100
2’s complement of 1000100 is 0111100 If Carry, result is positive. 0010000
Discard the carry

Example: 1000100 – 1010100 1 000100

2’s complement of 1010100 is 0101100 + 0101100
If no Carry, result is negative.
Magnitude is 2’s complement of the result 1110000
= –0010000
Signed Binary Numbers

▶ When a signed binary number is positive

• The MSB is ‘0’ which is the sign bit and rest bits represents the magnitude

▶ When a signed binary number is negative

• The MSB is ‘1’ which is the sign bit and rest of the bits may be
represented by three different ways
 Signed magnitude representation
 Signed 1’s complement representation
 Signed 2’s complement representation
Signed Binary Numbers

-9 +9
1 1001 0 1001
Signed magnitude representation
Signed 1’s complement representation 1 0110 0 1001

Signed 2’s complement representation 1 0111 0 1001

-0 +0
1 0000 0 0000
Signed magnitude representation
Signed 1’s complement representation 1 1111 0 0000

Signed 2’s complement representation -None- 0 0000

Range of Binary Number

Binary Number of n bits

▶
General binary number: ( )

▶
Signed magnitude binary number: – ( ) to + ( )

▶
Signed 1’s complement binary number: – ( ) to +( )

▶
Signed 2’s complement binary number: – ( ) to +( )
Signed Binary Number Arithmetic

▶ Add or Subtract two signed binary number including its sign bit either signed
1’s complement method or signed 2’s complement method
▶ The 1’s complement and 2’s complement rules of general binary number is
applicable to this

• It is important to decide how many bits we will use to represent the number
• Example: Representing +5 and -5 on 8 bits:
– +5: 00000101
– -5: 10000101
• So the very first step we have to decide on the number of bits to represent number
Digital Codes
Overview

▶ Introduction
▶
Binary Coded Decimal Code
▶
EBCDIC Code
▶
▶ Excess-3 Code
▶ Gray Code
ASCII Code
Introduction

▶ Calculations or computations are not useful until their results can be displayed in a
manner that is meaningful to people.
▶ We also need to store the results of calculations, and provide a means for data input.
▶ Thus, human-understandable characters must be converted to computer-
understandable bit patterns using some sort of character encoding scheme.
▶ As computers have evolved, character codes have evolved.
▶
Larger computer memories and storage devices permit richer character codes.
▶
The earliest computer coding systems used six bits.
▶ Binary-coded decimal (BCD) was one of these early codes. It was used by IBM
mainframes in the 1950s and 1960s.
▶ In 1964, BCD was extended to an 8-bit code, Extended Binary-Coded Decimal
Interchange Code (EBCDIC).
▶ EBCDIC was one of the first widely-used computer codes that supported upper and
lowercase alphabetic characters, in addition to special characters, such as punctuation
and control characters.
▶ EBCDIC and BCD are still in use by IBM mainframes today.
▶ Other computer manufacturers chose the 7-bit ASCII (American Standard Code
for Information Interchange) as a replacement for 6-bit BCD codes.
▶ While BCD and EBCDIC were based upon punched card codes, ASCII was based
upon telecommunications (Telex) codes.
▶ Until recently, ASCII was the dominant character code outside the IBM mainframe world.
Binary Coded Decimal (BCD)
▶ Consider 5 + 5
▶ 50101 ▶ Had 1010 and want to add 6 or 0110
▶ +50101 ▶ so 1010
▶ giving 1 0 1 0 which is binary 10 but
not a BCD digit! ▶ plus 6 0 1 1 0
▶ What to do? ▶ Giving 1 0 0 0 0

▶ Try adding 6??

▶ Add 7 + 6
▶ have 7 0111
▶ plus 6 0110
▶ Giving 1 1 0 1 and again out
of range
▶ Adding 6 0110
▶ Giving 1 0 0 1 1 so a 1 carries
out to the next BCD digit
▶ FINAL BCD answer 0001 0011
or 1310
▶ Add the BCD for 417 to 195 ▶ Had a carry to the 2nd BCD digit position
▶ Would expect to get 612 ▶ 1
▶ 0100 0001 done
▶ BCD setup - start with Least Significant
Digit ▶ 0001 1001 0010
0001 0111
▶ 0100 ▶ 1011
▶ 0001 1001 0101
0110
▶ 1100 ▶ Again must add 6
▶ Giving 1 0001
▶ Adding 6 0110 ▶ And another carry
▶ Gives 1 0010
▶ Had a carry to the 3rd BCD digit position
▶ 1
▶ 0100 done done
▶ 0001 0001 0010

▶ 0110
▶ And answer is 0110 0001 0010 or the BCD for the base 10 number
612
EBCDIC Code

▶ The EBCDIC code is an 8-bit alphanumeric code that was

developed by IBM to represent alphabets, decimal digits and
special characters, including control characters.
▶ The EBCDIC codes are generally the decimal and the hexadecimal
representation of different characters.
▶ This code is rarely used by non IBM-compatible computer systems.
The Excess-3- Code

▶ Excess-3 code is self complementary code? Justify.

Gray Code

▶ Gray code is another important code that is also used to convert the decimal number
into 8-bit binary sequence. However, this conversion is carried in a manner that the
contiguous digits of the decimal number differ from each other by one bit only
▶ In pure binary coding or 8421 BCD then counting from 7 (0111) to 8 (1000)
requires 4 bits to be changed simultaneously
▶ Gray coding avoids this since only one bit changes between subsequent numbers
Binary to Gray

Example:
b5 b 4 b 3 b2 b 1 g5 = b 5
Binary: 1 0 1 1
g4 = b 5 b 4
g3 = b 4 b 3
+ + + g2 = b 3 b 2
g1 = b 2 b 1
1 1 g0 = b 1 b 0
Gray: g5
Gray to Binary

b5 = g 5
b4 = g 5 g4
b3 = g 5 g4 g3
b2 = g 5 g4 g3 g2
b1 = g 5 g4 g3 g2 g1
b0 = g 5 g4 g3 g2 g1 g 0
Reflection of Gray Codes

00 0 00 0 000
01 0 01 0 001
11 0 11 0 011
10 0 10 0 010
1 10 0 110
1 11 0 111
1 01 0 101
1 00 0 100
1 100
1 101
So, called reflected code 1 111
1 110
1 010
1 011
1 001
1 000
Alphanumeric Codes

▶ How do you handle alphanumeric data?

▶
Easy answer!
▶

Formulate a binary code to represent characters!
▶ For the 26 letter of the alphabet would need 5 bit
for representation.
▶ But what about the upper case and lower case, and the digits,
and special characters
ASCII

▶ ASCII stands for American Standard Code for Information Interchange

▶ The code uses 7 bits to encode 128 unique characters

▶ Formally, work to create this code began in 1960. 1st standard in 1963. Last updated in 1986
▶ Represents the numbers
▶ All start 011 xxxx and the xxxx is the BCD for the digit
▶ Represent the characters of the alphabet
▶ Start with either 100, 101, 110, or 111
▶ A few special characters are in this area
▶ Start with 010 – space and !”#$%&’()*+.-,/
▶ Start with 000 or 001 – control char like ESC
ASCII Properties

ASCII has some interesting properties:

Digits 0 to 9 span Hexadecimal values 3016 to 3916

Upper case A - Z span 4116 to 5A16
 Lower case a - z span 6116 to 7A16
• Lower to upper case translation (and vice versa)
occurs by flipping bit 6.
 Delete (DEL) is all bits set, a carryover from when
punched paper tape was used to store messages.
 Punching all holes in a row erased a mistake!
Lecture of Module 2

Logic Gates
Overview

▶ Introduction
▶
Logical Operators
▶
▶
Basic Gates
▶ Universal Gates
▶ Realization of Basic Gates using Universal Gates
Other Logic Gates
 Introduction

▶Binary variables take on one of two values

▶Logical operators operate on binary values and binary variables
▶Basic logical operators are the logic functions AND, OR and
NOT ▶Logic gates implement logic functions
▶Boolean Algebra: a useful mathematical system for specifying and
transforming logic functions
▶We study Boolean algebra as a foundation for designing and analyzing digital
systems
Binary Variables

▶ Recall that the two binary values have different names:

▶ True/False
▶ On/Off
▶ Yes/No
▶ 1/0
▶ We use 1 and 0 to denote the two values.
▶ Variable identifier examples:
▶ A, B, x, y, z, or X1 , X2 etc. for now
Logical Operations

▶ The three basic logical operations are:

▶ AND
▶ OR
▶ NOT
▶ AND is denoted by a dot (·)
▶ OR is denoted by a plus (+)
▶ NOT is denoted by an over bar ( ¯ ), a single quote mark (') after, or (~)
before the variable
 Operator


Operators operate on binary values and binary variables

Operations are defined on the values "0" and "1" for each operator:

AND OR NO
T
0·0=0 0+0=0 0
1
0·1=0 0+1=1 1
0
1·0=0 1+0=1
1·1=1 1+1=1
 Truth Tables

▶ Truth table - a tabular listing of the values of a function for all possible combinations of
values on its arguments
▶ Example: Truth tables for the basic logic operations:

AND OR NOT
X Y X Y Z=X+Y X Z= X̅
Z=X·Y 0 0 0 0 1
0 00 0 1 1 1 0
0 10 1 0 1
1 00 1 1 1
1 11
Logic Function Implementation

Switches in parallel => OR

▶ Using Switches
▶ For inputs:
▶ logic 1 is switch closed
▶ logic 0 is switch open
▶ For outputs:
▶ logic 1 is light on Switches in series => AND
▶ logic 0 is light off.
 Logic Gates

▶ In the earliest computers, switches were opened and closed by magnetic

fields produced by energizing coils in relays. The switches in turn
opened and closed the current paths.
▶ Later, vacuum tubes that open and close current paths electronically
replaced relays.
▶ Today, transistors are used as electronic switches that open and close
current paths.
▶ NOT, AND and OR Gates (Basic gates)
▶
NAND and NOR Gates (Universal logic gates)
 NOT Gate

A NOT gate accepts one input signal (0 or 1) and returns the opposite signal as output
AND Gate

If all inputs are 1, the output is 1; otherwise, the output is

0 Or if any input is 0, output is 0
OR Gate

If all inputs are 0, the output is 0; otherwise, the output is

1 Or if any input is 1, output will be 1
Universal Gates

 Universal Logic Gate: Any basic gate or logic function can be

realized using this gate
 Two universal logic gates
 NAND
 NOR
NAND Gate

If all inputs are 1, the output is 0; otherwise, the output is 1

NOR Gate

If all inputs are 0, the output is 1; otherwise, the output is 0

Realization

NAND gates are sometimes called universal gates because they can be used to
produce the other basic Boolean functions.

A
A AB
A
B
AND gate

Inverter

A O e
A R
A+B g
B a
B t
 A
+
B
NOR gate
Realization

NOR gates are also universal gates and can form all of the basic gates.

A
A A+B
A
B
OR gate

Inverter

A
A AB AB
B
B
AND gate NAND gate
XOR Gate

If odd numbers of inputs are 1, the output is 1; otherwise, the output is 0

X-NOR Gate

XNOR X Y Z
X Z
Y 0 0 1
0 1 0
1 0 0
1 1 1
Constructing Gates
Transistor
A device that acts either as a wire that conducts electricity or as a resistor that blocks
the flow of electricity, depending on the voltage level of an input signal
A transistor has no moving parts, yet acts like a switch
It is made of a semiconductor material, which is neither a particularly good conductor
of electricity nor a particularly good insulator
A transistor has three
terminals A source
A base
An emitter, typically connected to a ground wire
If the electrical signal is grounded, it is allowed to flow through
an alternative route to the ground (literally) where it can do
no harm
AND Gate OR Gate
Timing Diagram

t t1 t 2 t 3 t 4 t 5 t 6
0

Input A 1
0
signals B 1 Transitions
0
F=A•B 0

Gate 1
1
Basic
Assumption:
Output G=A+B 0
Zero time for
Signals H=A’ 1
signals to
0
propagate
Through gates
Gate Delay

▶ In actual physical gates, if one or more input changes causes the output to change,
the output change does not occur instantaneously.
▶ The delay between an input change(s) and the resulting output change is the gate delay
denoted by tG:
Input
1

0 tG tG tG = 0.3
1 ns
Output

0
0 0.5 1 1.5 Time (ns)
Boolean Algebra
Overview

▶ Introduction
▶ Boolean Algebra
▶ Properties
▶ Algebraic Manipulation
▶ De-Morgan Theorem
▶ Complementation
▶ Truth Table
 Introduction

▶ Understand the relationship between Boolean logic and digital computer circuits.
▶
Learn how to design simple logic circuits.
▶
Understand how digital circuits work together to form complex computer systems.
▶ In the latter part of the nineteenth century, George Boole suggested that
logical thought could be represented through mathematical equations.
▶ Computers, as we know them today, are implementations of Boole’s Laws of
Thought.
▶ In this chapter, you will learn the simplicity that constitutes the essence of the
machine (Boolean Algebra).
 Boolean algebra

▶ Boolean algebra is a mathematical system for the manipulation of

variables that can have one of two values.
▶ In formal logic, these values are “true” and “false.”
▶ In digital systems, these values are “on” and “off,” 1 and 0, or “high”
and “low.”
▶ Boolean expressions are created by performing operations on Boolean
variables.
▶ Common Boolean operators include AND, OR, NOT, XOR, NAND
and NOR
▶A Boolean operator can be completely described using a truth
table.
▶ The truth table for the Boolean operators AND, OR and NOT are
shown at the right.
▶ The AND operator is also known as a Boolean product.
▶ The OR operator is the Boolean sum.
▶ The NOT operation is most often designated by an over-bar. It is
sometimes indicated by a prime mark ( ‘ ) or an “elbow” ( ).
▶ A Boolean function has:
• At least one Boolean variable,

• At least one Boolean operator, and

• At least one input from the set {0,1}
▶ It produces an output that is also a member of the set {0,1}

Now you know why the binary numbering system is

so handy in digital systems
Conceptually
Boolean
Algebra

Truth Logic
Table Circuit
▶ Digital computers contain circuits that implement Boolean functions.
▶ The simpler that we can make a Boolean function, the smaller the
circuit that will result.
▶ Simpler circuits are cheaper to build, consume less power, and run
faster than complex circuits.
▶ With this in mind, we always want to reduce our Boolean functions to
their simplest form.
▶ There are a number of Boolean identities that help us to do this.
Properties of Boolean Algebra

▶ Most Boolean identities have an AND (product) form as well as an

OR (sum) form.
▶ Our second group of Boolean identities should be familiar to you
from your study of algebra:
▶ Our last group of Boolean identities are perhaps the most useful.
▶ If you have studied set theory or formal logic, these laws are also familiar to you.
▶ We can use Boolean identities to simplify the

function: as follows:
With respect to duality, Identities 1 – 8 have the following
relationship:

1.X+0=X 2.X•1 = X (dual of 1)

3.X+1 =1 4.X•0 = 0 (dual of 3)
5. X + X = X 6. X • X = X (dual of 5)
7. X + X’ = 1 8. X • X’ = 0 (dual of 8)
Algebraic Manipulation

▶ Boolean algebra is a useful tool for simplifying digital circuits.

▶
Why do it? Simpler can mean cheaper, smaller, faster.
▶ Example: Simplify F = x’yz + x’yz’ +
xz. F= x’yz + x’yz’ + xz
=x’y(z+z’) + xz
=x’y•1 + xz
=x’y + xz
▶ Example: Prove x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’
▶ Proof: x’y’z’+ x’yz’+ xyz’
=x’y’z’ + x’yz’ + x’yz’ + xyz’
=x’z’(y’+y) + yz’(x’+x)
=x’z’•1 + yz’•1
=x’z’ + yz’
Complementation

▶ Sometimes it is more economical to build a circuit using the complement of

a function (and complementing its result) than it is to implement the function
directly.
▶ DeMorgan’s law provides an easy way of finding the complement of a Boolean
function.
▶ DeMorgan’s law states:
▶ Find the complement of F(x, y, z) = x y’ z’ + x’ y z

▶ G = F’ = (xy’z’ + x’yz)’

=(x’+y+z) • (x+y’+z’) DeMorgan again

▶ Note: The complement of a function can also be derived by finding

the function’s dual, and then complementing all of the literals
 Truth Table

▶ Enumerates all possible combinations of variable values x y z F1 F2 F3

and the corresponding function value 0 0 0 0 1 1
▶ Truth tables for some arbitrary functions
0 0 1 0 0 1
F1(x,y,z), F2(x,y,z), and F3(x,y,z) are shown to the right.
▶ Truth table: a unique representation of a Boolean function 0 1 0 0 0 1
▶ If two functions have identical truth tables, the 0 1 1 0 1 1
functions are equivalent (and vice-versa).
1 0 0 0 1 0
▶ Truth tables can be used to prove equality theorems.
▶ However, the size of a truth table grows exponentially with
1 0 1 0 1 0
the number of variables involved. This motivates the use 1 1 0 0 0 0
of Boolean Algebra.
1 1 1 1 0 1
Standard SOP and POS
Overview

▶ Introduction
▶
SOP and POS
▶
▶
Minterms and Maxterms
▶ Canonical Forms
▶ Conversion Between Canonical Forms
Standard Forms
Introduction

▶ Through our exercises in simplifying Boolean expressions, we

see that there are numerous ways of stating the same Boolean
expression.
▶ These “synonymous” forms are logically equivalent.
▶ Logically equivalent expressions have identical truth tables.
▶ In order to eliminate as much confusion as possible, designers
express Boolean functions in standardized or canonical form.
SOP and POS

▶ There are two canonical forms for Boolean expressions: Sum-Of-

Products (SOP) and Product-Of-Sums (POS).
▶ Recall the Boolean product is the AND operation and the Boolean
sum is the OR operation.
▶ In the Sum-Of-Products form, ANDed variables are ORed together.
▶ For example:

▶ In the Product-Of-Sums form, ORed variables are ANDed together:

▶ For example:
Definitions

▶ Literal: A variable or its complement

▶
Product term: literals connected by •
▶
Sum term: literals connected by +
▶ Minterm: a product term in which all the variables appear exactly
once, either complemented or un-complemented
▶ Maxterm: a sum term in which all the variables appear exactly
once, either complemented or un-complemented
 Truth Table notation for Minterms and Maxterms

▶ Minterms and Maxterms are easy to

denote using a truth table. x y z Minterm Maxterm
▶ Example: 0 0 0 x’y’z’ = m0 x+y+z = M0
Assume 3 variables x,y,z (order is fixed)
0 0 1 x’y’z = m1 x+y+z’ = M1
▶ Any Boolean function F( ) can be expressed as a
unique sum of minterms and a unique product 0 1 0 x’yz’ = m2 x+y’+z = M2
of maxterms (under a fixed variable ordering). x’yz = m3 x+y’+z’= M3
0 1 1
▶ In other words, every function F() has
two canonical forms: 1 0 0 xy’z’ = m4 x’+y+z = M4

▶ Canonical Sum-Of-Products (sum 1 0 1 xy’z = m5 x’+y+z’ = M5

of minterms)
1 1 0 xyz’ = m6 x’+y’+z = M6
▶ Canonical Product-Of-Sums (product
of maxterms) 1 1 1 xyz = m7 x’+y’+z’ =
M7
 Canonical Forms

▶ Canonical Sum-Of-Products:
The minterms included are those mj such that F( ) = 1 in row j of the truth table for F( ).
▶ Canonical Product-Of-Sums:
The maxterms included are those Mj such that F( ) = 0 in row j of the truth table for F( ).
• f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form,
and m(1,2,4,6) indicates that the minterms to be included are m1, m2, m4, and m6.
• f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and
M(0,3,5,7) indicates that the maxterms to be included are M0, M3, M5, and M7.
• Since mj = Mj’ for any j,
∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)
Conversion Between Canonical Forms

▶ Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared
in the original form with those that do not.
▶ Example:
f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m 2 + m 4 + m 6
=∑(1,2,4,6)
=∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
 F XYZ XYZ XYZ XYZ m0 m2 m5 m7 m(0, 2, 5, 7) F XYZ XYZ XYZ

XYZ m1 m3 m4 m6 m(1, 3, 4, 6)

F m1 m3 m4 m6
→
F m1 m3 m4 m6 m1 m3 m4 m6

F M1 M3 M4 M6 (X Y Z)(X Y Z)(X Y Z)(X Y Z)

M (1, 3, 4, 6)
Standard Forms

• Standard forms are “like” canonical forms, except that not

all variables need appear in the individual product (SOP) or
sum (POS) terms.
• Example:
f1(a,b,c) = a’b’c + bc’ + ac’
is a standard sum-of-products form
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’) is
a standard product-of-sums form.
Conversion of SOP from standard to canonical form

▶ Expand non-canonical terms by inserting equivalent of 1

in each missing variable x:
(x + x’) = 1
▶ Remove duplicate minterms
▶ f1(a,b,c) = a’b’c + bc’ + ac’
=a’b’c + (a+a’)bc’ + a(b+b’)c’
=a’b’c + abc’ + a’bc’ + abc’ + ab’c’
= a’b’c + abc’ + a’bc’ + ab’c’
Conversion of POS from standard to canonical form

▶ Expand non-canonical terms by adding 0 in terms of missing

variables (e.g., xx’ = 0) and using the distributive law
▶ Remove duplicate maxterms
▶ f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
=(a+b+c)•(aa’+b’+c’)•(a’+bb’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)•(a’+b’+c’)
=(a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)
Minimization Techniques
Overview

▶ Introduction
▶ Karnaugh Map (K-Map)
▶ Simplification Rules
▶ K-Map Simplification for Two Variables
▶ K-Map Simplification for Three Variables
▶ K-Map Simplification for Four Variables
▶ Don’t Care Conditions
▶ Redundancy
▶ Design of Combinational Circuits
Introduction

Truth Boolean
Table Function

Unique Many different expressions exist

Simplification from Boolean function

- Finding an equivalent expression that is least expensive to implement

- For a simple function, it is possible to obtain a simple expression
for low cost implementation
- But, with complex functions, it is a very difficult for implementation
Karnaugh Map (K-map) is a simple procedure for simplification of
Boolean expressions.

Truth
Table Simplifie
Karnaugh d
Boolean
Boolean Map Function
function
Karnaugh Map (K-Map)

▶ Karnaugh maps (K-maps) are graphical C’D’ C’D CD CD’

representations of Boolean functions. A’B’

▶ One map cell corresponds to a row in the truth

table. A’B

▶ Also, one map cell corresponds to a minterm or AB

a maxterm in the Boolean expression
AB’
▶ Each term is identified by a decimal number
whose binary representation is identical to the
binary interpretation of the input values of the
term.
 K-Map Simplification for Two Variables

▶ Of course, the Minterm function that we derived from our

Truth Table was not in simplest terms.
▶ That’s
what we started with in this example.
▶ We can, however, reduce our complicated expression to its
simplest terms by finding adjacent 1s in the K-map that can
be collected into groups that are powers of two.

• In our example, we have two

such groups.
– Can you find them?
K-Map Rules

The rules of K-map simplification are:

• Groupings can contain only 1s; no 0s.
• The number of 1s in a group must be a power of 2 – even if
it contains a single 1.
• Nearby 1s are to be grouped.
• Corner 1s are to be grouped.
• Group that wraps around the sides of a K-map.
• Diagonal groups are not allowed.
• The groups must be made as large as possible.
• Groups can overlap.
 K-Map Rules

▶ The best way of selecting two groups of 1s form our simple

K-map is shown.
▶ We see that both groups are powers of two and that the
groups overlap.
K-Map Simplification for Two Variables

2-variable Karnaugh maps are trivial but can be used to introduce the
methods you need to learn. The map for a 2-input OR gate looks like this:
A
A 0 1
B
B 0 1 A
A B Y 1 1 1
0 0 0
0 1 1 B
1 0 1
1 1 1 A+B
K-Map Simplification for Three Variables

▶ A K-map for three variables is constructed as shown in the diagram below.

▶ We have placed each Minterm in the cell that will hold its value.
▶ Notice that the values for the yz combination at the top of the matrix
form a pattern that is not a normal binary sequence.
▶ Consider the function:
F (X, Y, Z) = X’Y’Z + X’YZ + XY’Z + XYZ
▶ Its K-map is given below.
▶ What is the largest group of 1s that is a power of 2?
▶ This grouping tells us that changes in the variables x and y have no influence
upon the value of the function: They are irrelevant.
▶ This means that the function, F (X, Y, Z) = X’Y’Z + X’YZ + XY’Z +
XYZ reduces to F = Z.

You could verify

this reduction
with Boolean
Algebra
▶ Now for a more complicated K-map. Consider the function:

▶ Its K-map is shown below. There are (only) two groupings of 1s.
▶ Can you find them?
▶ In this K-map, we see an example of a group that wraps around
the sides of a K-map.
 f (0,4) BC f (4,5) A B f (0,1,4,5) B f (0,1,2,3) A

BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
01000 00000 01100 0 1 1 1 1
1 0 0 0 0
1 1 0 0 0 1 1 1 0 0 1 1 1 0 0

f = ∑ (1,3) = A’C
f (0,4) AC f (4,6) A C f (0,2) AC f (0,2,4,6) C

0 BC 0 BC
BC
11 10
A 00 01 111 10 A 00 1 A 00
0 1 1 0 01
0 0 0 0 0 0 1
1
0
1 01 11 10 BC 01
A 00
0 1 1 1 0 0 1
1 0 1 1 0 0 1
K-Map Simplification for Four Variables

▶ The K-map can be extended to accommodate the 16 Minterms that

are produced by a four-input function.
▶ This is the format for a 16-minterm K-map.
▶ Wehave populated the K-map shown below with the nonzero minterms
from the function:

▶ Can you identify (only) three groups in this K-map?

▶ Our three groups consist of:
▶ A purple group entirely within the K-map at the right.
▶ A pink group that wraps the top and bottom.
▶ A green group that spans the corners.
▶ Thus we have three terms in our final function:
▶ It is possible to have a choice as to how to pick groups within a K-map, while
keeping the groups as large as possible.
▶ The (different) functions that result from the groupings below are logically
equivalent.
 CD 00 CD 00 CD 00 CD 00
AB 01 11 10 AB 01 11 10 AB 01 11 10 AB 01 11 10

00 1 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

01 0 0 0 0 01 0 1 0 0 01 0 0 0 0 01 1 0 0 1

11 0 0 0 0 11 0 1 0 0 11 0 1 1 0 11 0 0 0 0

10 1 0 0 0 10 0 0 0 0 10 0 0 0 0 10 0 0 0 0

f(0,8)B C D f(5,13) B C D f (13,15) A B D f (4,6) A B D

CD CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
0 0 0 0

00 0 0 1 1 00 1 0 0 1
10 10
01 0 0 1 1 01 1 0 0 1

11 0 0 0 0 11 0 0 0 0

0 0 0 0
 11 11

00 00 0 0 1 1 1 0 0 1
10 10
01 01 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0
f(2,3,6,7) A C f(4,6,12,14)B D f (2,3,10,11)B C f (0,2,8,10) B D
0 0 1 1 1 0 0 1
 CD CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 0 0 0 0 00 0 0 1 0 00 1 0 1 0 00 0 1 0 1

01 1 1 1 1 01 0 0 1 0 01 0 1 0 1 01 1 0 1 0

11 0 0 0 0 11 0 0 1 0 11 1 0 1 0 11 0 1 0 1

10 0 0 0 0 10 0 0 1 0 10 0 1 0 1 10 1 0 1 0

f(4, 5, 6, 7)A B f(3, 7,11,15) C D f(0, 3, 5, 6, 9,10,12,15) f(1, 2, 4, 7, 8,11,13,14)

fABCD fABCD
CD CD

CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10

00 0 1 1 0 1 0 0 1 00
1 f(1, 3,5, 7, 01 f(0,2,4,6,8,10,12,14)
01 0 1 1 0 0 0 1
9,11,13,15)
11 0 1 1 0 1 0 0 1 11

10 0 1 1 0 1 0 0 1 10
 00 00 0 0 0 0 1 1 1 1
01 01 1 1 1 1
0 0 0 0
11 11 1 1 1 1
0 0 0 0
10 10 0 0 0 0
1 1 1 1
f(4,5,6,7,12,13,14,15) f(0,1,2,3,8,9,10,11)

fD fD
f B f B
Don’t Care Conditions

▶ Real circuits don’t always need to have an output defined for every
possible input.
▶ For example, some calculator displays consist of 7-segment LEDs. These
7
LEDs can display 2 patterns but all patterns are not used.
▶ If a circuit is designed so that a particular set of inputs can never happen,
we call this set of inputs a don’t care condition.
▶ They are very helpful to us in K-map circuit simplification.
▶ In a K-map, a don’t care condition is identified by an X in the cell of
the minterm(s) for the don’t care inputs, as shown below.
▶ In performing the simplification, we are free to include or ignore the
X’s when creating our groups.
▶ In one grouping in the K-map below, we have the function:
▶
F=W’X’+YZ
▶ A different grouping gives us the function:
▶ The truth table of:
F (W, X, Y, Z) = W’X’ + YZ
differs from the truth table of:

▶ However, the values for which they differ, are the inputs for which we
have don’t care conditions.
Redundancy
Design of combinational digital circuits

▶ Steps to design a combinational digital circuit:

▶ From the problem statement derive the truth table
▶ From the truth table derive the unsimplified logic expression
▶ Simplify the logic expression
▶ From the simplified expression draw the logic circuit

▶ Example: Design a 3-input (A,B,C) digital circuit that will give at its
output (X) a logic 1 only if the binary number formed at the input
has more ones than zeros.
 Inputs Output
A B C X X(3, 5, 6, 7)
0 0 0 0 0 BC X
1 0 0 1 0
11 10
2 0 1 0 0 A 00 01
3 0 1 1 1 0 0 0 1 0
4 1 0 0 0 1 0 1 1 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1
X AC AB BC
A B C
▶ Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a
logic 1 only if the binary number formed at the input is between 2 and 9 (including).
Inputs Output
A B C D X X
0 0 0 0 0 0 (2,3,4,5,6,7,8,9)
1 0 0 0 1 0
X
2 0 0 1 0 1
3 0 0 1 1 1
CD 01 11 10
4 0 1 0 0 1
AB 00
5 0 1 0 1 1 Same
00 0 0 1 1
6 0 1 1 0 1
1 1 1 1
7 0 1 1 1 1
01
8 1 0 0 0 1 0 0 0 0
9 1 0 0 1 1 11
1 1 0 0
10 1 0 1 0 0 10
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0 X AC AB ABC
X
A B C D
Conclusion

▶ K-maps provide an easy graphical method of simplifying Boolean

expressions.
▶ A K-map is a matrix consisting of the outputs of the minterms of a
Boolean function.
▶ In this section, we have discussed 2- 3- and 4-input K-maps. This
method can be extended to any number of inputs through the use of
multiple tables.
Recapping the rules of K-map simplification:
• Groupings can contain only 1s; no 0s.
• Groups can be formed only at right angles; diagonal groups are not
allowed.
• The number of 1s in a group must be a power of 2 – even if it contains a
single 1.
• The groups must be made as large as possible.
• Groups can overlap and wrap around the sides of the K-map.
• Use don’t care conditions when you can.
• Redundancy must be reduced