Digital System Design
Verilog HDL Tasks and Functions
Maziar Goudarzi
Today program
Reusing code
Tasks and Functions
2005
Verilog HDL
Introduction
Procedures/Subroutines/Functions in SW programming languages
The same functionality, in different places
Verilog equivalence:
Tasks and Functions Used in behavioral modeling Part of design hierarchy Hierarchical name
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Contents
Functions Tasks Differences between tasks and functions
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Tasks and Functions
Functions
Functions
Keyword: function, endfunction Can be used if the procedure
does not have any timing control constructs returns exactly a single value has at least one input argument
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Verilog HDL
Functions (contd)
Function Declaration and Invocation
Declaration syntax:
function <range_or_type> <func_name>; <input declaration(s)> <variable_declaration(s)> begin // if more than one statement needed <statements> end // if begin used endfunction
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Functions (contd)
Function Declaration and Invocation
Invocation syntax:
<func_name> (<argument(s)>);
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Verilog HDL
Functions (contd)
Semantics
much like function in Pascal An internal implicit reg is declared inside the function with the same name The return value is specified by setting that implicit reg <range_or_type> defines width and type of the implicit reg
<type> can be integer or real default bit width is 1
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Function Examples Parity Generator
module parity; reg [31:0] addr; reg parity; initial begin end always @(addr) begin parity = calc_parity(addr); $display("Parity calculated = %b", calc_parity(addr) ); end function calc_parity; input [31:0] address; begin calc_parity = ^address; end endfunction endmodule
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Function Examples Controllable Shifter
module shifter; `define LEFT_SHIFT 1'b0 `define RIGHT_SHIFT 1'b1 reg [31:0] addr, left_addr, right_addr; reg control; initial begin end function [31:0] shift; input [31:0] address; input control; begin shift = (control==`LEFT_SHIFT) ? (address<<1) : (address>>1); end endfunction endmodule
always @(addr) begin left_addr =shift(addr, `LEFT_SHIFT); right_addr =shift(addr,`RIGHT_SHIFT); 2005 Verilog HDL end
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Tasks and Functions
Tasks
Tasks
Keywords: task, endtask Must be used if the procedure has
any timing control constructs zero or more than one output arguments no input arguments
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Tasks (contd)
Task declaration and invocation
Declaration syntax
task <task_name>; <I/O declarations> <variable and event declarations> begin // if more than one statement needed <statement(s)> end // if begin used! endtask
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Tasks (contd)
Task declaration and invocation
Task invocation syntax
<task_name>; <task_name> (<arguments>);
input and inout arguments are passed into the task output and inout arguments are passed back to the invoking statement when task is completed
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Tasks (contd)
I/O declaration in modules vs. tasks
Both used keywords: input, output, inout In modules, represent ports
connect to external signals
In tasks, represent arguments
pass values to and from the task
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Task Examples Use of input and output arguments
module operation; parameter delay = 10; reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR; initial $monitor( ); initial begin end always @(A or B) begin bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end
2005
task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; input [15:0] a, b; begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask endmodule
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Task Examples Use of module local variables
module sequence; reg clock; initial begin end initial init_sequence; always asymmetric_sequence;
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task init_sequence; clock = 1'b0; endtask task asymmetric_sequence; begin #12 clock = 1'b0; #5 clock = 1'b1; #3 clock = 1'b0; #10 clock = 1'b1; end endtask endmodule
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Tasks and Functions
Differences between Tasks and Functions
Differences between...
Functions
Can enable (call) just another function (not task) Execute in 0 simulation time No timing control statements allowed At lease one input Return only a single value
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Tasks
Can enable other tasks and functions May execute in nonzero simulation time May contain any timing control statements May have arbitrary input, output, or inout Do not return any value
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Differences between (contd)
Both
are defined in a module are local to the module can have local variables (registers, but not nets) and events contain only behavioral statements do not contain initial or always statements are called from initial or always statements or other tasks or functions
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Differences between (contd)
Tasks can be used for common Verilog code Function are used when the common code
is purely combinational executes in 0 simulation time provides exactly one output
Functions are typically used for conversions and commonly used calculations
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Today Summary
How to define tasks and functions Where to use each of them
The same purpose as subroutines in SW Provide more readability, easier code management Are part of design hierarchy Tasks are more general than functions
Can represent almost any common Verilog code
Functions can only model purely combinational calculations
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Other Notes
Homework 7
Chapter 8, all exercises Due date: Next Sunday (Azar 20th)
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