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IEEE 754 Floating Point Multiplier

This document summarizes the design of a floating point multiplier that follows the IEEE 754 standard. It describes the key components of the floating point format, including the sign bit, exponent, and significand. It then outlines the main steps in multiplying two floating point numbers, including adding the exponents, subtracting the bias, multiplying the significands, and detecting overflow or underflow. The design sections explain how the multiplier calculates the sign bit, adds the exponents, normalizes the result, and handles overflow and underflow conditions. In conclusion, the document presents the floating point multiplier design and simulation to support the IEEE 754 standard.

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Rutul Patel
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270 views15 pages

IEEE 754 Floating Point Multiplier

This document summarizes the design of a floating point multiplier that follows the IEEE 754 standard. It describes the key components of the floating point format, including the sign bit, exponent, and significand. It then outlines the main steps in multiplying two floating point numbers, including adding the exponents, subtracting the bias, multiplying the significands, and detecting overflow or underflow. The design sections explain how the multiplier calculates the sign bit, adds the exponents, normalizes the result, and handles overflow and underflow conditions. In conclusion, the document presents the floating point multiplier design and simulation to support the IEEE 754 standard.

Uploaded by

Rutul Patel
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Floating Point Multiplier

By Patel Rutul J. Mtech Student (EMS) Under Guidance of Mr. Dayanand B.M.

Floating Point Presentation :


The IEEE-745 standard presents the floating point format.

It consist of
- 1 sign bit (S) - 8-bit exponent (E) - 23-bit mantissa (M)

An extra bit is added to the fraction to form what is called the significand.
If the exponent is greater than 0 and smaller than 255, and there is 1 in MSB of the significand then a number is said to be a normalized number.

IEEE- 754single precision floating point format :

Lets suppose a multiplication of 2 floating point numbers A & B, where A= -18.0 and B=9.5 Binary representation of the operands: A=-10010.000 B=+1001.1 Normalized representation of the operands: A=-1.001x24 B=+1.0011x23 IEEE representation of the operands :

A=1 10000011 00100000000000000000000


B=0 10000010 00110000000000000000000

Multiplication Steps :
Multiplying two numbers in floating point format is done by adding the exponent of he two numbers. Then subtracting the bias from their results. Multiplying the significand of the two numbers . Calculating the sign bit.

Design of Floating Point Multiplier :


Sign Bit Calculation :

- Multiplying Result is a negative sign if one of the multiplied number is of a negative value.

Design of Floating Point Multiplier :


Exponent Addition:

The result of this stage is called the intermediate exponent.

Design of Floating Point Multiplier :


Bias Subtraction:

Subtract the bias constant T=127 (001111111) from the adder result. Bias subtractor result is R=S-T.

Normalizer:
The result of the significand multiplication must be normalized to have a leading 1 just to the left of the decimal point.

The intermediate product has the leading one at bit 46 or 47.


If the leading 1 is at 46 then the result is already normalized.

It the leading 1 is at 47 then the intermediate product is sifted to the right


and the exponent is incremented by 1.

Overflow/Underflow Detection:
Overflow/Underflow means that the results exponent is too large/small to be represented in the exponent field.

The exponent of the result must be 8-bits in size, must be between 1 to


254. Overflow may occur while adding the two exponents or during

normalization.
Underflow may occur while subtracting the bias to form intermediate exponent.

If the intermediate exponent <= 0 then its an underflow and result turns to
Zero with sign determined by the multiplier. If the overflow occurs, results turns to infinity with sign determined by the

multiplier.

Simulation Result:

Conclusion :
This Seminar presents format, design and simulation of a floating point multiplier that supports the IEEE 754-2008 binary

Thank You

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