CHAPTER 5
ARITHMETIC CIRCUITS
MISS
GEOGIANA
BUJA
RECAP
RECAP
5.6 T WO’S COMPLEMENT ARITHMETIC
5.6 T WO’S COMPLIMENT ARITHMETIC
There are cases when an operation produces a result
that exceeds the range of the number system,
producing a condition known as overflow. When we
add two numbers with the same sign, which produce
a sum that is larger than the largest representable
number, we can obtain an incorrect result. As a rule,
addition overflow occurs whenever the sign of the
sum is different from the signs of both addends.
CASE 1 A+B TWO POSITIVE NUMBERS
CASE 1 A+B TWO POSITIVE NUMBERS
CASE 1 A+B TWO POSITIVE NUMBERS
CASE 1 A+B TWO POSITIVE NUMBERS
CASE 1 A+B TWO POSITIVE NUMBERS
TAKE 5
CASE 2 -A-B TWO NEGATIVE NUMBERS
CASE 2 -A-B TWO NEGATIVE NUMBERS
CASE 2 -A-B TWO NEGATIVE NUMBERS
CASE 3 A-B
CASE 3 A-B
CASE 3 A-B
CASE 4 -A+B
TAKE 5
5.7 SUBTRACTOR CIRCUIT
5.7 SUBTRACTOR CIRCUIT
Sign Bit
1 7 4 2 1
4321 4321
74LS83A
A4
A3
A2
A1 s4
B4 s3
B3 s2
B2 s1
B1
Cin Cout Ignore C4
5V
5.7 SUBTRACTOR CIRCUIT
5.7 SUBTRACTOR CIRCUIT
74LS83A
A4
A4..A1 A3
A2
A1 s4
B4 s3 S4..S1
B3 s2
B2 s1
B1
B4..B1
Cin Cout
5V 74LS83A
A4 S8:Bit tanda
A8..A5 A3
A2
A1 s4
B4 s3 S8..S5
B3 s2
B2 s1
B1
B8..B5
Cin Cout Abaikan
5.7 SUBTRACTOR CIRCUIT
5.8 ADDER-SUBTRACTOR CIRCUIT
5.8 ADDER-SUBTRACTOR CIRCUIT
5.8 ADDER-SUBTRACTOR CIRCUIT