Inclusive Language Commitment
• Arm is committed to making the language we use inclusive, meaningful, and respectful. Our goal is to
remove and replace non-inclusive language from our vocabulary to reflect our values and represent our
global ecosystem.
• Arm is working actively with our partners, standards bodies, and the wider ecosystem to adopt a
consistent approach to the use of inclusive language and to eradicate and replace offensive terms. We
recognise that this will take time. This course may contain references to non-inclusive language; it will be
updated with newer terms as those terms are agreed and ratified with the wider community. We
recognise that some of you will be accustomed to using the previous terms and may not immediately
recognise their replacements. Please refer to the following examples:
• When introducing the AMBA AXI Protocols, we will use the term ‘Manager’ instead of ‘Master’ and ‘Subordinate’
instead of ‘Slave’.
• When introducing the architecture, we will use the term ‘Requester’ instead of ‘Master’ and ‘Completer’ instead of
‘Slave’.
• Contact us at [email protected] with questions or comments about this course. You can also report
non-inclusive and offensive terminology usage in Arm content at [email protected].
1 © 2021 Arm
Introduction to Arm-
based System on Chip
Design
© 2021 Arm
Learning Outcomes
At the end of this module, you will be able to:
• Explain the motivations for the development of a System on Chip (SoC).
• Define what an SoC is and its characteristics.
• Outline the advantages and limitations of SoCs.
• Describe the main steps in an SoC design flow.
• Define what a Programmable SoC (PSoC) and its characteristics.
3 © 2021 Arm
Why the SoC Design Concept Developed
• We are living in a post-PC era, with:
• Smartphones and tablets
• The Internet of Things, wearable computing, and cyber-physical systems
• Industry 4.0
• The silicon transistor is still at the heart of this revolution.
• The primary metrics of silicon chips have changed: from clock-frequency to cost, form-
factor, and power.
• On-chip integration of functional hardware is now more important than ever.
• How and why have we reached this point?
4 © 2021 Arm
Moore’s Law
Moore’s Law
(*)
Prediction of Moore’s Law
(*) Data are based on international semiconductor technology road map (http://www.itrs.net/)
5 © 2021 Arm
Why Scaling?
The virtuous circle of the semiconductor industry
6 © 2021 Arm
The Design Productivity Gap
T he design gap
Productivity (transistors /staff m onth)
1.00E+07 1.00E+08
58% per year compound
1.00E+06 1.00E+07
Logic transistors per chip complexity growth
1.00E+05 1.00E+06
1.00E+04 1.00E+05
1.00E+03 1.00E+04
1.00E+02 1.00E+03
21% per year compound
1.00E+01 productivity growth 1.00E+02
1.00E+00 1.00E+01
1981 1986 1991 1996 2001 2006
Complexity outpaces design productivity
7 © 2021 Arm
Bridging the Design Productivity Gap
• Several strategies exist to reduce the design productivity gap exist, namely:
Design
Abstraction
Standard
Tools and Design
Hardware Automation
Platforms
SoCs
Design Fast
Reuse Prototyping
8 © 2021 Arm
What Is an SoC?
• An SoC is an integrated circuit that packages basic computing components into a single
chip.
• An SoC may have most or even all of the components to power a computer.
Arm cores
arm AMBA buses
Physical IPs
Motherboard of a PC SoC
Picture source: http://thecustomizewindows.com/, http://www.adafruit.com/
9 © 2021 Arm
What Is Inside an SoC?
• The basic components of an SoC include:
• A system Requester, such as a microprocessor or DSP
• System peripherals, such as memory blocks, timers, and external digital/analog interfaces
• A system bus that connects Requester and peripherals using a specific bus protocol
• More sophisticated s are integrated in modern SoCs, such as multicores, DSPs, GPUs,
and multiple buses connected by bus bridges.
A simple SoC System Requester
(Processor)
System Bus
Program Data
Timer DAC GPIO Watchdog
Memory Memory
10 © 2021 Arm
Example Arm-based SoC
Clock Power
Generator Management Unit
Watchdog
JTAG/Serial wire
DMA
Low Latency Arm Cortex-M0
Microprocessor Timers
APB Bus
AHB IOP
Mux
AHB to APB UART
Arm AMBA
ARM AMBA33AHB-Lite
AHB-LiteSystem
SystemBus
Bus
Bus Bridge
System Boot ROM 7-segment
AHB APB
RAM UART
ROM VGA GPIO
RAM Timer
Control ROM Table Peripheral
Display Peripheral
An example of an Arm-based SoC
11 © 2021 Arm
Advantages of SoCs
Higher
performance
Lighter
Low cost
footprint
SoC
Advantages
Higher Power
reliability efficiency
12 © 2021 Arm
Limitations of SoCs
Less
flexibility
SoC
limitations
Application
Complexity
specific
13 © 2021 Arm
SoC v Microcontroller v Processor
SoC CPU MCU
Can have a single or multiple
processor cores
Is a single processor core Typically has a single processor core
Has larger memory blocks, a variety
of IOs, and other peripherals
Integrated with more powerful Has memory blocks, basic IOs, and
Used for general purposes
blocks, e.g., GPU, DSP other basic peripherals
Capable of running OSs
Mainly used for basic control
It needs to be supported with
Mainly used for advanced purposes, such as embedded
memories and IOs
applications (e.g., smartphones, applications
tablets).
14 © 2021 Arm
Commercialized SoCs
• Benefiting from its power efficiency, SoCs have been widely used in mobile devices,
such as smartphones, tablets, and digital cameras.
• A number of SoCs have been developed by a large ecosystem of design companies:
• Snapdragon by Qualcomm
• Tegra by Nvidia
• OMAP by Texas Instruments
Most mobile SoCs use Arm-based microprocessors since they deliver high performance
with less power consumption.
15 © 2021 Arm
SoC Example: NVIDIA Tegra 2
Designer NVIDIA
Year 2010
Processor Arm Cortex-A9
(dual-core)
Frequency Up to 1.2 GHz
Memory 1 GB 667 MHz LP-DDR2
Graphics ULP GeForce
Process 40 nm
Package 12 × 12 mm (Package on Package)
Used in tablets Acer Iconia Tab A500
Asus Eee Pad Transformer
Motorola Xoom
Motorola Xoom Family Edition
Samsung Galaxy Tab 10.1
Toshiba Thrive
16 © 2021 Arm
SoC Design Flow
IP Vendors:
Hardware Software
IP Cores Purchase SW Drivers Core Design
Purchase HW
cores drivers
SoC
Integrated Design Specifics Integrated
Hardware Software
HW/SW partitioning
Fabless Vendors: SoC
Functional Prototype on Platforms Software Design
Simulation e.g., FPGA Simulation
Physical Optimization HW/SW Application Development
and Fabrication Co-verification and Test
Foundries:
Volume Manufacture Chip Fabrication
and Ship
Device Vendors:
PCB Manufacture
and Device Assembly Final Products
17 © 2021 Arm
SoC Design Flow
IP Vendors:
Hardware Software
IP Cores Purchase SW Drivers Core Design
Purchase HW
cores drivers
SoC
Integrated Design Specifics Integrated
Hardware Software
HW/SW partitioning
Fabless Vendors: SoC
Functional Prototype on Platforms Software Design
Simulation e.g., FPGA Simulation
Physical Optimization HW/SW Application Development
and Fabrication Co-verification and Test
Foundries:
Volume Manufacture Chip Fabrication
and Ship
Device Vendors:
PCB Manufacture
and Device Assembly Final Products
18 © 2021 Arm
SoC Design Flow
IP Vendors:
Hardware Software
IP Cores Purchase SW Drivers Core Design
Purchase HW
cores drivers
SoC
Integrated Design Specifics Integrated
Hardware Software
HW/SW partitioning
Fabless Vendors: SoC
Functional Prototype on Platforms Software Design
Simulation e.g., FPGA Simulation
Physical Optimization HW/SW Application Development
and Fabrication Co-verification and Test
Foundries:
Volume Manufacture Chip Fabrication
and Ship
Device Vendors:
PCB Manufacture
and Device Assembly Final Products
19 © 2021 Arm
SoC Design Flow
IP Vendors:
Hardware Software
IP Cores Purchase SW Drivers Core Design
Purchase HW
cores drivers
SoC
Integrated Design Specifics Integrated
Hardware Software
HW/SW partitioning
Fabless Vendors: SoC
Functional Prototype on Platforms Software Design
Simulation e.g., FPGA Simulation
Physical Optimization HW/SW Application Development
and Fabrication Co-verification and Test
Foundries:
Volume Manufacture Chip Fabrication
and Ship
Device Vendors:
PCB Manufacture
and Device Assembly Final Products
20 © 2021 Arm
SoC Design Flow
IP Vendors:
Hardware Software
IP Cores Purchase SW Drivers Core Design
Purchase HW
cores drivers
SoC
Integrated Design Specifics Integrated
Hardware Software
HW/SW partitioning
Fabless Vendors: SoC
Functional Prototype on Platforms Software Design
Simulation e.g., FPGA Simulation
Physical Optimization HW/SW Application Development
and Fabrication Co-verification and Test
Foundries:
Volume Manufacture Chip Fabrication
and Ship
Device Vendors:
PCB Manufacture
and Device Assembly Final Products
21 © 2021 Arm
SoC Design Flow
IP Vendors:
Hardware Software
IP Cores Purchase SW Drivers Core Design
Purchase HW
cores drivers
SoC
Integrated Design Specifics Integrated
Hardware Software
HW/SW partitioning
Fabless Vendors: SoC
Functional Prototype on Platforms Software Design
Simulation e.g., FPGA Simulation
Physical Optimization HW/SW Application Development
and Fabrication Co-verification and Test
Foundries:
Volume Manufacture Chip Fabrication
and Ship
Device Vendors:
PCB Manufacture
and Device Assembly Final Products
22 © 2021 Arm
Programmable SoC
• SoCs can be prototyped and tested on FPGAs.
• Two options:
• Use soft cores to embed a processor in the logic fabric (soft processor) and use device interconnect
resources to implement a bus that communicates with other custom design blocks.
• Use modern programmable SoCs (PSoCs; e.g., Xilinx Zynq), which include hard processors (e.g., Arm)
connected to peripherals and to the logic fabric through a bus (e.g., AXI bus).
• PSoCs can overcome ASIC SoC limitations in some application areas by providing:
• Flexibility for upgrading and functionality modification
• Faster time-to-market for low to medium production volumes
23 © 2021 Arm
Architecture of a PSoC
Processing System (PS) Programmable Logic (PL)
Memory
Custom Custom
Peripheral Peripheral
AXI A B
AXI
Microprocessor
(Arm Cortex-A9)
AXI Custom Custom
Peripheral Peripheral
C X
Hard Silicon
Peripherals
24 © 2021 Arm
Example: Xilinx Zynq-7000
• Dual-core Arm Cortex-A9 processor
• On-chip memory
• Memory interfaces
• Integrated peripherals: timers, USB, UART,
I2C, SPI
• AXI buses and AXI ports
• Programmable logic
Picture source: http://www.xilinx.com/publications/prod_mktg/zynq-7000-generation-
25 ahead-backgrounder.pdf
© 2021 Arm
Design a Simple Arm-based SoC
• Design Arm-based SoCs and prototype them onto a Zynq chip.
• The SoCs will consist of:
• An Arm Cortex-A9 microprocessor
• An AXI bus
• Different customer-made physical IPs
Arm Cortex-A9
Microprocessor
Arm
ARM AMBA
AMBA 4 AXI System
3 AHB-Lite BusBus
System
System Boot ROM AHB
DDR RAM UART
ROM GPIO HDMI
RAMinput HDMI output …
Control ROM Table Peripheral
A simplified Arm-based SoC
26 © 2021 Arm
