ANURAG GROUP OF INSTITUTIONS

(An Autonomous Institution)

(Affiliated to JNTU-HYD, Approved by AICTE and NBA Accredited)
Venkatapur, Ghatkesar, Medchal–Malkajgiri district,
Hyderabad,Telangana,
India. 500 08
(2020-21)

Department of Computer Science & Engineering

Computer Organization
II B.Tech II semester
Unit-I PPT Slides
Text Books:
1. M. Morris Mano, Computer System Architecture, Third Edition,
Pearson/PHI, 2017.
2. Douglas V Hall, Microprocessor and Interfacing, Second Edition, Tata
McGraw Hill, 2017.
 INDEX
UNIT-I PPT SLIDES

SNo. Module as per Session planner Lecture No

1. Instruction Definition L1
2. Instruction Cycle L2
3. Flow chart for instruction cycle L3
4. Instruction storage L4
5. Types of instruction formats L5
6. Addressing Modes L6
7. Numerical examples and problems. L7
BLOCK DIAGRAM OF A COMPUTER
 BASIC COMPUTER
 The Basic Computer has two components, a processor and
memory
 The memory has 4096 words in it
 4096 = 212, so it takes 12 bits to select a word in memory
 Each word is 16 bits long
CPU RAM

15 0

4095
 Instruction codes

INSTRUCTION
 An instruction is an order/command given to a computer processor
by a computer program. At the lowest level, each instruction is a
sequence of 0s and 1s that describes a physical operation the
computer is to perform
 Program
 A sequence of (machine) instructions
 (Machine) Instruction
 A group of bits that tell the computer to perform a specific operation (a
sequence of micro-operation)
 The instructions of a program, along with any needed data are stored
in memory
 The CPU reads the next instruction from memory
 It is placed in an Instruction Register (IR)
 Control circuitry in control unit then translates the instruction into
the sequence of microoperations necessary to implement it
 Instructions

BASIC COMPUTER INSTRUCTIONS

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0

I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0

0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0

1 1 1 1 I/O operation
 COMMON BUS Registers
SYSTEM
 A bus is a high-speed internal connection. Buses are used to send
control signals and data between the processor and other
components.
Three types of bus are used.
1. Address bus - carries memory addresses from the processor to
other components such as primary storage and input/output
devices. The address bus is unidirectional.
2. Data bus - carries the data between the processor and other
components. The data bus is bidirectional.
3. Control bus - carries control signals from the processor to other
components. The control bus also carries the clock's pulses. The
control bus is unidirectional.
 The registers in the Basic Computer are connected using a bus

 This gives a savings in circuitry over complete connections

between registers
 Instruction codes

CONTROL UNIT
 Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations that
implement them

 Control units are implemented in one of two ways

 Hardwired Control
 CU is made up of sequential and combinational circuits to generate the control
signals
 Microprogrammed Control
 A control memory on the processor contains microprograms that activate the
necessary control signals
 We will consider a hardwired implementation of the control
unit for the Basic Computer
 INSTRUCTION CYCLE
 In Basic Computer, a machine instruction is executed in the
following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction
has an indirect address
4. Execute the instruction

 After an instruction is executed, the cycle starts again at step 1,

for the next instruction

 Note: Every different processor has its own (different)

instruction cycle
 Instrction Cycle
INSTRUCTION CYCLE FLOW CHART
Start
SC  0

T0
AR  PC

T1
IR  M[AR], PC  PC + 1

T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
TYPES OF INSTRUCTION FORMATS
(ZERO, ONE, TWO AND THREE ADDRESS)
 Instructions may be classified by the number of operands and the
number of addresses which they use.
 Instructions are executed sequentially using a Program Counter to
hold the address of the next instruction.
 Control instructions are used to change the program counter
based on flags set by a previous instruction.
 Transfer instructions may be used to move data without
performing any operation on it.
 Registers may be used to hold temporary results or frequently
used operands.
 Sometimes stack operations are useful for storing temporary data
which may not fit in registers. A stack is also useful for
implementing recursion.
 Instruction Format
INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor
register(s)
Mode field - specifies the way the operand or the
effective address is determined

An instruction is of various length depending upon the number of

addresses it contain.
Generally CPU organization are of three types on the basis of
number of address fields:

1. Single Accumulator organization

2. General register organization
3. Stack organization
 Instruction Format
INSTRUCTION FORMAT

- The three most common CPU organizations:

Single accumulator organization:

ADD X /* AC  AC + M[X] */

General register organization:

ADD R1, R2, R3 /* R1  R2 + R3 */

ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */

Stack organization:
PUSH X /* TOS  M[X] */
ADD
 Instruction Format
THREE, AND TWO-ADDRESS INSTRUCTIONS
Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */
- Results in short programs
- Instruction becomes long (many bits)
Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1  M[A] */
ADD R1, B /* R1  R1 + M[A] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
 Instruction Format
ONE, AND ZERO-ADDRESS INSTRUCTIONS
• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */

• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :

PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
 Addressing Modes

ADDRESSING MODES
Addressing Modes

Specifies a rule for interpreting or modifying the address

field of the instruction (before the operand is actually
referenced)

Variety of addressing modes

- to give programming flexibility to the user.

- to use the bits in the address field of the instruction
efficiently
TYPES OF ADDRESSING MODES

1. Implied / Implicit Addressing Mode

2. Immediate Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode
5. Register Direct Addressing Mode
6. Register Indirect Addressing Mode
7. Relative Addressing Mode
8. Indexed Addressing Mode
9. Base Register Addressing Mode
10. Auto-Increment Addressing Mode
11. Auto-Decrement Addressing Mode
1. IMPLIED ADDRESSING MODE

 The definition of the instruction itself specify the operands

implicitly.
 It is also called as implicit addressing mode.

Examples
 The instruction “Complement Accumulator (CMA) ” is an
implied mode instruction.
 In a stack organized computer, Zero Address Instructions
are implied mode instructions.
 2. IMMEDIATE ADDRESSING MODE
In this addressing mode,
 The operand is specified in the instruction explicitly.

 Instead of address field, an operand field is present that

contains the operand.

Examples

ADD 10  will increment the value stored in the accumulator by 10.

MOV R #20  initializes register R to a constant value 20.
 3.DIRECT ADDRESSING MODE
In this addressing mode,
 The address field of the instruction contains the effective
address of the operand.
 Only one reference to memory is required to fetch the operand.

 It is also called as absolute addressing mode.

Examples

ADD X  will increment the value stored in the accumulator by the

value stored at memory location X.
AC ← AC + [X]
 4. INDIRECT ADDRESSING MODE
In this addressing mode,
 The address field of the instruction specifies the address of
memory location that contains the effective address of the
operand.
 Two references to memory are required to fetch the operand.

Examples

ADD X  will increment the value stored in the accumulator by the

value stored at memory location specified by X.
AC ← AC + [[X]]
 5. REGISTER DIRECT ADDRESSING MODE
In this addressing mode,
 The operand is contained in a register set.

 The address field of the instruction refers to a CPU register that

contains the operand.
 No reference to memory is required to fetch the operand.

Examples

ADD R  will increment the value stored in the accumulator by the

content of register R.
AC ← AC + [R]
 6. REGISTER INDIRECT ADDRESSING MODE
In this addressing mode,
 The address field of the instruction refers to a CPU register that
contains the effective address of the operand.
 Only one reference to memory is required to fetch the operand.

Examples

ADD R  will increment the value stored in the accumulator by the

content of memory location specified in register R.
AC ← AC + [[R]]
 7. RELATIVE ADDRESSING MODE
In this addressing mode,
 Effective address of the operand is obtained by adding the
content of program counter with the address part of the
instruction
Effective Address = Content of Program Counter + Address part of the instruction

Note:
• Program counter (PC) always
contains the address of the next
instruction to be executed.
• The value increases irrespective of
whether the fetched instruction has
completely executed or not
 8. INDEXED ADDRESSING MODE
In this addressing mode,
 Effective address of the operand is obtained by adding the
content of index register with the address part of the instruction.

Effective Address = Content of Index Register + Address part of the instruction

 9. BASE REGISTER ADDRESSING MODE
In this addressing mode,
 Effective address of the operand is obtained by adding the
content of base register with the address part of the instruction.

Effective Address = Content of Base Register + Address part of the instruction

 10. AUTO-INCREMENT ADDRESSING MODE
In this addressing mode,
 After accessing the operand, the content of the register is
automatically incremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.

 Only one reference to memory is required to fetch the operand.

This addressing mode is a special case of Register Indirect Addressing

Mode .Where,
Effective Address = Content of Base Register + Step Size

NOTE-
In auto-increment addressing mode,
• First, the operand value is fetched.
• Then, the instruction register RAUTO value is incremented by step
size ‘d’.
10. AUTO-INCREMENT ADDRESSING MODE
Example

Assume operand size = 2 bytes.

Here,
• After fetching the operand 6B, the instruction register RAUTO will be
automatically incremented by 2.
• Then, updated value of RAUTO will be 3300 + 2 = 3302.
• At memory address 3302, the next operand will be found.
 10. AUTO-DECREMENT ADDRESSING MODE
In this addressing mode,
 First, the content of the register is decremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 After decrementing, the operand is read.
 Only one reference to memory is required to fetch the operand

This addressing mode is a special case of Register Indirect Addressing

Mode .Where,
Effective Address = Content of Base Register – Step Size

NOTE-
In auto-decrement addressing mode,
• First, the instruction register RAUTO value is decremented by step
size ‘d’.
• Then, the operand value is fetched.
10. AUTO-DECREMENT ADDRESSING MODE
Example

Assume operand size = 2 bytes.

Here,
• First, the instruction register RAUTO will be decremented by 2.

• Then, updated value of RAUTO will be 3302 – 2 = 3300.

• At memory address 3300, the operand will be found.
APPLICATIONS OF VARIOUS ADDRESSING MODES

 Immediate addressing mode: Used to set an initial

value for a register. The value is usually a constant
 Register addressing mode/direct addressing
mode: Used to implement variables and access static
data
 Register indirect addressing mode/indirect
addressing mode: Used to pass an array as a parameter
and to implement pointers
APPLICATIONS OF VARIOUS ADDRESSING MODES

 Index addressing mode: Used to implement arrays

 Base register addressing mode: Used to write codes
that are relocatable and for handling recursion
 Auto-increment/decrement addressing mode: Used to
implement loops and stacks
 Relative addressing mode: Used to relocate programs
at run time and to change the execution order of
instruction
 Addressing Modes
TYPES OF ADDRESSING MODES
Implied Mode
Address of the operands are specified implicitly in the definition of the
instruction
- No need to specify address in the instruction
EA = AC, or EA = Stack[SP]
- Examples instructions from Basic Computer
CLA, CME, INP
Immediate Mode
Instead of specifying the address of the operand, operand itself is
specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
 Addressing Modes
TYPES OF ADDRESSING MODES
Direct Address Mode
Instruction specifies the memory address which can be used directly to
access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large
physical memory space
EA = IR(addr) (IR(addr): address field of IR)
Indirect Addressing Mode
The address field of an instruction specifies the address of a memory
location that contains the address of the operand.
- When the abbreviated address is used large physical memory
can
be addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory
access
EA = M[IR(address)]
 Addressing Modes
TYPES OF ADDRESSING MODES
Register Mode: Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
EA = IR(R) (IR(R): Register field of IR)
Register Indirect Mode
Instruction specifies a register which contains the memory address of the
operand.
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
EA = [IR(R)] ([x]: Content of x)
Autoincrement or Autodecrement Mode
When the address in the register is used to access memory, the value in the
register is incremented or decremented by 1 automatically.
 Addressing Modes
TYPES OF ADDRESSING MODES

Relative Addressing Modes

The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated register to
calculate the address of the operand.
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of address
bits
EA = f(IR(address), R), R is sometimes implied
3 different Relative Addressing Modes depending on R;
 PC Relative Addressing Mode (R = PC)
EA = PC + IR(address)
 Indexed Addressing Mode (R = IX, where IX: Index Register)
EA = IX + IR(address)
 Base Register Addressing Mode (R = BAR, where BAR: Base Address
Register)
EA = BAR + IR(address)
 Addressing Modes

ADDRESSING MODES - EXAMPLES -

Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900

702 325

800 300
Addressing Effective Content
Mode Address of AC

Direct address 500 /* AC  (500) */

800
Immediate operand - /* AC  500 */
500
Indirect address 800 /* AC  ((500)) */
300
Relative address 702 /* AC  (PC+500) */ 325
Indexed address 600 /* AC  (RX+500) */ 900
Register - /* AC  R1 */ 400
Register indirect 400 /* AC  (R1) */
700
Auto increment 400 /* AC  (R1)+ */
700
ADDRESSING MODES PROBLEM
 An instruction is stored at address 300 with its
address field at location 301. Address field has
the value 400. Processor R1 contains 200.
Evaluate Effective Address for the following.
a. Immediate b. Direct
c. Register Indirect d. Relative
e. Auto Increment f. Auto Decrement
 PROS&CONS OF EACH ADDRESSING MODES
Immediate Mode
-No need to specify address in the instruction
-However, operand itself needs to be specified
-Sometimes, require more bits than the address
-Fast to acquire an operand
Direct Address Mode
-Faster than the other memory addressing modes
-Too many bits are needed to specify the address for a large
physical memory space
Indirect Addressing Mode
-When the abbreviated address is used large physical memory
can be addressed with a relatively small number of bits
-Slow to acquire an operand because of an additional
memory access
 PROS&CONS OF EACH ADDRESSING MODES
Register Mode
-Designated operand need to be in a register

-Shorter address than the memory address

-Saving address field in the instruction

-Faster to acquire an operand than the memory addressing

Register Indirect Mode

-Saving instruction bits since register address is shorter than the memory address

- Slower to acquire an operand than both the register addressing or memory

addressing

Relative Addressing Modes

- Address field of the instruction is short

- Large physical memory can be accessed with a small number of address bits