1
DIGITAL LOGIC DESIGN
( CE_118 )
CHAPTER 4:
PROCESSOR DESIGN
(part_2)
2
Outline
We introduced new concepts:
Instruction sets
Instruction types
Addressing modes
Instruction-execution cycle
Processor design flow
Including
instruction set design,
instruction set flowcharts,
component allocation,
ASM charts
processor architecture
We have demonstrated processor design
16-bit CISC design
32-bit RISC design
o data-forwarding
o
3
CISC Design: Instruction-set flowchart
Instruction-set flowchart
Does not presume any architectural details
Does not have any particular processor datapath
Does not consider any timing constraints or clock cycle
duration
Purpose:
Give the order in which the operations specified by
each instruction will be executed.
Design process
4
CISC Design:
Instruction-set
flowchart
Design process
5
CISC Design:
Instruction-set
flowchart
(cont.)
Design process
6
Component allocation for the 16-bit processor
Components: 64K x 16 Memory
RF 8 x 16 Register File (RF)
ALSU (S: shift)
Instruction register ( IR )
Program counter ( PC )
Address register ( AR )
Data register ( DR )
Status register ( Status )
Control unit
ASIC
AR, DR: needed to shorten clock period
and improve the performance of the
processor
Processor ASM chart
(scheduled IS chart)
Design process
7
Processor ASM chart
(scheduled IS chart)
Design process
8
9
Processor
schematic
Design process
Schematic is obtained by connecting the processor components
according to the ASM chart, that is, by adding a connection whenever
data or an instruction is moved from one component to another.
Components with several connections at the same input port require
selectors for that particular input port.
10
Reduced instruction-set cycle
(RISC design)
Register and misc. instructions do not
need address fetch and effective
address computation
Memory and control instructions do
not need operand fetch and operation
Instruction-execution cycle
execution
Share operand fetch and address fetch
Share operand execution and effective
address computation
Thus, instruction cycle reduced to
4 steps
Pipelined execution
11
Reduced instruction-set for a 32-bit processor
(RISC type)
a) Register Instructions
arithmetic, logic, move
and shift Name Action
Op Dest, Src1, Src2 RF (Dest) RF[Src1] Op RF[Src2]
Op Dest, Src1, Src2 RF (Dest) RF[Src1] Op Constant
Move Dest, Src1 RF (Dest) RF[Src1]
Shift Dest, Src1, Constant RF (Dest) RF[Src1] shift Constant
b) Memory instructions
load and store
Name Action
L immU Dest RF [Dest(31…16)] Offset
2 addressing mode:
- Immediate L immL Dest RF [Dest(15…0)] Offset
- Relative
L rel Dest, Src2, Offset RF [Dest] Mem[RF[Src2] + Offset]
S rel Src1, Src2, Offset Mem[RF[Src2] + Offset] RF [Src1]
12
Reduced instruction-set for a 32-bit processor
(RISC type)
c) Control instructions
jump and branch
Beq (=) Name Action
Bgre (>) Jump Offset PC PC + offset
Bgoeq (≥) Jump Src2, Offset PC RF[Src2] + offset
Bless (<)
Bloeq (≤) Brel Src1, Src2, Offset PC PC+1 if RF[Src1] not rel RF[Src2]
Bneq (≠) PC PC+Offset if RF[Src1] rel RF[Src2]
d) Miscellaneous
instructions
no-op, clear, Name Action
set and reset No-op Do nothing
Clear Dest RF [Dest] 0
Sstat Dest status [Dest] 1
Rstat Dest status [Dest] 0
13
Four-stage pipeline
RISC Separate instruction and data memories
block diagram Add control register in each pipeline stage
Pipeline stalling (flushing) for control instructions
2-stage forward path
1-stage forward path
Stage 2 Stage 3
Stage 1 Stage 4
14
RISC operation for a 3-line program
x=a+b
y=b–c
z=c+d
Source program
Assembly program
Concurrently:
n+3 clock cycles to execute n instructions
Sequentially:
4n clock cycles for n instructions (no pipeline)
Timing diagram
15
RISC operation for a 2-line program with data dependencies
sum = a + b
total = sum + c
Source program
Assembly program
Data dependence:
5 (or 45%) of 11 instructions are No-op
instrucsions decrease substantially
performance of pipelined processor
Timing diagram
16
RISC operation for a 2-line program with data-forwarding
sum = a + b
total = sum + c Assembly program
Source program
Timing diagram
17
RISC operation for a 2-line program with data-forwarding
2-stage
forward path
1-stage
forward path
sum = a + b
total = sum + c
18
RISC operation without branch prediction
If a≥b then
begin
max = a
min = b
end
else
begin
max = b
min = a
end Timing diagram when branch is not taken
endif
Source program Assembly program
Timing diagram when branch is taken
19
RISC operation with branch prediction
If a≥b then
begin
max = a
min = b
end
else result of
jump inst
begin
max = b
min = a Assembly program
end Timing diagram when branch is not taken
endif
Source program
result of
Bgoeq inst
Timing diagram when branch is taken
20
Chapter Summary
We introduced new concepts:
Instruction sets
Instruction types
Addressing modes
Instruction-execution cycle
Processor design flow
Including
instruction set design,
instruction set flowcharts,
component allocation,
ASM charts
processor architecture
We have demonstrated processor design:
16-bit CISC design
32-bit RISC design
o data-forwarding
o branch prediction
21
Bài tập
Biểu diễn lệnh sau:
a = b + c;
x=y+z
Viết lệnh assembly
Biểu diễn lược đồ thời gian.
Thêm lệnh
a=b+z
Viết lệnh assembly
Biểu diễn lược đồ thời gian
22
Bài tập
Biểu diễn lệnh sau trong 2 trường hợp:
- Dùng kỹ thuật data forwarding
- Không dùng kỹ thuật data forwarding.
a = b + c;
x = y + z;
t = x + z
Viết lệnh assembly
Biểu diễn lược đồ thời gian.
23
Bài tập
Biểu diễn lệnh sau trong 2 trường hợp:
- Dùng kỹ thuật tiên đoán
- Không dùng kỹ thuật tiên đoán.
if(a < b)
max = a
else
max = b
Viết lệnh assembly
Biểu diễn lược đồ thời gian
