Polymers, Nano-material for
Electronic and Photonic Packaging
Application I
C.P. Wong Regents’
Professor
and the Charles Smithgall Institute-Endowed
Chair School of Materials Science & Engineering
Georgia Institute of Technology
Atlanta, GA 30332-0245 Email:
[email protected] TA: Yu-Chieh Lin 1
2
Outline
• Introduction
• Trends in Semiconductor and Electronic
Encapsulation, Heterogenous Package
Integration
• Fundamentals of Materials Science &
Engineering
• Inorganic and Organic Polymers
• Interconnect Materials and Processes
• Reliability Test Methods
• Recent Advances in FC, BGA, CSP,
SIP, WLP 3
4
5
7
LECTURE 1 INTRODUCTION
7
Polymers for Electronic and Photonic
Applications
Passive Active
s s
Resists (Positive and Negative tones) Intrisic Conductive
Polymers
Dielectrics (Insulator) Integrated
Optics
Interconnects (ICA and OLE
ACA) D
Packaging (Encapsulants, Coatings, Molecular
EMC,...) Electronics
Substrate (Circuit Display
Boards) Devices
Non-Linear Optics (Χ2, Χ
3)
C.P.Wong,Ed., ”Polymers for Electronic & Photonic Applications”, Academic Press(1993) 8
Trends in Microelectronics
Year 2007 2010 2013 2016
2004
DRAM 1/2 pitch (nm) 90 65 45 32 22
Chip Size DRAM
(mm2) 383 662 563 560 464
Max Substrate
Diameter (mm) 300 300 300 450 450
Max No. of I/O MPU 3072 3072 3840 4224 4416
Flip-Chip Pitch
(micron) Area Array 150 120 100 90 80
On-Chip Frequency
(MHz) 4171 9285 15079 22980 39683
Allowable Max Power
(W) MPU 158 189 218 251 288
Source: ITRS 2004
9
Levels of Integrated Circuit
Complexity
Integration Number of Equivalent Typical Functions Typical
Level Transistors Gates or Systems Number L/O’s
SSI 1-40 1-10 Single Circuit Function 1
(e.g., Transistors)
MSI 40-400 10-100 Functional Network 24
LSI 400-4,500 100-1,000 Hand Calculator or 48
Digital Watch
VLSI 4,500-300,000 1,000-80,000 Microprocessor 64-300
ULSI Over 300,000 Over 80,000 Computer on a Chip >200-40100+
VLSI Limitation [<1nm]
-Moore’s Law-More Moore-More than Moore(HI)
• Not Physics or Chemistry
Gated oxide （ based on SiO2 k~4-6) with
>10Å could prevent electron tunneling
=> HfO2 (k~11)
But Economics
<0.02 μm needs step and repeat lithographic
techniques, such as direct electron beam, X-ray
exposures– very expensive (ASML-EB high
cost) 11
Limitation of Silicon Integrated Circuitry
• Feature Size < ~(1nm) –Economic
• Chip Size ~(35mm2) –
Manufacturability
• Speed ~(10 x 10-12 sec.) –Electron
» Mobility
III-V Compounds(6-10X)
(GaAs, InP are opto-active)
Increase Scale of Integration Leads to:
• Low cost per function
• Fast speed
• Low power
• High Reliability
• Smaller size
12
Definition of Electronic Packaging, HI
Design:
DFX
System Test
Four Functions, plus Design & System Test => From Semiconductor ICs( and
Electronic Packaging Discrete Passives) to
Systems
13
Introduction
Electronic Packaging (Old concept-too narrow, HI)
Electronic Packaging is defined as bridge that interconnects
integrated circuits and other components into system-level
board to form electronic products.
Packaging Hierarchy
First-Level Package
(Mutichip Module)
Second-Level Package
(Printed Wiring Board Assembly or PWBA)
Third-Level Package
(Motherboard or Backplane)
14
Surface Mount Assembly Process
Assembly Components
Surface Mount PWB
Electronic Components
Surface Mount Assembly Processes
Screen Printing Placement Reflow
Assembly is heated in
Solder paste is dispensed Electronic components
oven above solder
onto copper pads on PWB are automatically placed
liquidus temperature
on PWB
and cooled to attach
15
components to PWB
Trends in Electronic Products
W/S
PC Computer
100000
• High
performance
10000 Notebook • Small
Volume(cm3)
profile
1000
Cellular • Multi-
function
100
Analog Digital • Low
cost
1970 1980 1990 2000
16
Int
Overall Packaging Evolution
Array
Direct Chip
Peripheral Attach MCM
Chip Scale
I/O Density
MCM
Ball Grid
Array
Fine Pitch
SMT
Surface
Mount
Through
Hole
1980 1985 1990 1995 2000 2005
Source: Motorola
17
Trends in IC Packages
Wafer Level
Silicon efficiency = Si area / Package area Packages (Stacked Thin
3D stack,
TSV)
Conventional
CSP
Density
QFP
BGA
1970 1980 1990 2000
18
19
21
22
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Summary: Next Generation Electronics
and Electronics Packaging
• Integrated packaging critical for next generation electronics
systems:
Characteristics Technical Approach
• Thin, light portable • Integrated passives
• High performance • Flip-chip
• Low dielectric constant, low loss
and low resistance materials
• High function • Optoelectronics, mixed signal
• VERY low-cost • Large area processing assembly
• VERY high reliability • Minimum packaging levels
RF Wireless Portable Electronics
Mass Storage
Navigation
Optic
Fax
Connectivity
Cellular Phone
Fax
Transaction
Transaction
Transportation Logistics
Navigation
Potential Attributes Radio
Communication TV
Handwriting
LCDs Cellular Phone
recognition
Fax
800 MHz Voice RF Tolling
Recognition Paging
Si
Paging
Navigation Home Shopping
3+ GHz RF/Optic/Cable Video on Demand
Fax Modem
GaAs Interactive
Phone Programming
Text to Speech
Land Based
Front End Batteries
Stage
Organizer
E-mail
Point of Sale Fax
Security
Satellite Based
Transaction Navigation
Stage
Phone
Paging
25
Steam Engine
Railway
Electric Power
Telephone & Telegram
Time
Petroleum, Automobile,
Airplanes
Information Technology
（ Transistors, IC tech)
Nanotechnology
Nanotechnology and Biotechnology
The Next Technological Revolution is
Biotechnology
,Energy
Why Nano?
Beyond Silicon for Semiconductor
Technology
Secrets of Bio Cell
Superior Electrical, Chemical,
Mechanical and Optical Properties
New Chemistry, Physics,….
Nanotechnology:
Tools: electron microscopy and scanning
Why Now?
probe microscopy: “eyes + hands”
Technology and industry needs, microelectronics
meets these challenges
Discovery of novel structures, nanocrystals,
nanotubes, ..…
New phenomena and properties: size
induced quantum phenomena
· ·New understanding: powerful
computer simulation and modeling
Carbon: An extraordinary
element
3D semiconducting diamond;
2D semimetallic graphite;
1D metallic and semiconducting
nanotubes; 0D fullerenes
Nanotechnology
Much More Than
Just Small!
Transmission electron microscope
image of a typical black carbon
chain collected in a smoke plume.
Small is different! But small particles in smoking is a silent
KILLER !!!!
Demand for Better Energy
Storage
High-power battery
technologies in EV
Renewable Energy
High-power density Energy Storage
technologies in
31 31
mobile devices
Packaging Evolution
1970’s 1980’s 1990’s 2000 2010
Chip-Level TA B and Wafer-le vel
red istrib uti Flip-chip area arr ay
Conne ction wir ebond
on t o area area array redistributi on
( 0 to 1st array
level
DIP
connection)
PGA QFP BGA CSP/WLCSP
First-Level Package System-Level
(Single Chip Module) Integra ted
packa ging
First -L evel Packa ge Thi n film Thi n film on
(Multi-Chip Module) Cer amic on ceramic PWB/cera mmi c
Optimizing IC
Packaging for:
PT H Periph eral Fine-pitch BGA CSP * Cost
1st to 2 n d Level SM T SMT SM T SM T
Connection * Performance
PWB-Dri ll PWB-Dri ll PWB-M icro Via * Reliability
* Design
Boar d
flexibility
* Time to m
Discre tes
arket
1005 080 5 0603 040 2 0 201
32
Georgia Tech
Microelectronics Systems
Technologies Medical
Telecom
Computer
Aerospace
US A
Consumer
Software, Applications, Services
Transportation
Ba
c tt
pti ies er
y
r O og Te
be ol ch
Fi chn no
lo
Te s Sy M
a gi
y ies on
ic s
Te tem Sto gne es
la og ctr es ch r t
si p nol s
no Pa age c/O i
Sy chn
le i ge
D ch oe og ka log ck pt
ste ol
T
Te
Te icr nol ac ies agi ech ical
m ogy
M ch -P n ng nol
IC esig 33
De
o
Te gi
si g
es
D
MPA
n
Georgia Tech
&
Paradigm Shifts in Electronics Systems
2000s
Software Services
• Electronic systems 1990-2000s Server
Wireless
– Paradigm shift: Mainframe Internet
Router/
Switch
Internet
• Digital computing PC PC Broad
Band
to
digital communications MPS
Video
• Mainframe to PC to Cell
Phone
internet(2000s)
• Digital consumer/ Mainframe
PC Internet
medical products.
1970s-1980s 34
Georgia Tech
Fundamental Limits
Technolog MOSFET Intrinsic Response
y Switching Time RC
Generatio Delay(ps) Delay*
n
1.0 ~20 ~1 ps
m ~5 ~30 ps
100n ~2. ~250
m 5 ps
35nm
*Source: Prof. Jim Meindl
35
Georgia Tech
Fundamental Limits
Interconnect
Technolog MOSFET Intrinsic
Switching
y Switching
Energy(fJ) L int =
Generatio Energy(fJ)
1mm*
n
1.0m ~ ~
100n 300 400
m ~2 ~ 10
35nm ~ ~3
@ 0.1
@ 35nm Technology Masking
Level FEOL = 8-14 *Source: Prof. Jim Meindl
BOFL = 26-34 Front-end-of-line vs back-end-of-line 36
Georgia Tech
37
Challenges in IC
Today Future
0.25u High-end
Microprocessor
Technology 0.1u High-end Microprocessor
Aluminum Copper
Conductors Conductors
(5 Levels) (8 levels)
Low-k
Oxide Dielectric
Dielectric
Copper
Plugs
Tungston
Plugs
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The Device The Device
Georgia Tech
Microelectronic Systems
Based onSOC/Wafer
SOP/mSIP Level Packaging
Thermal Management
-- ---- --
Ga-As Si-Ge MS CMOS MEMS MEMS Sensors
Termination Resistor Flip-Chip Assembly
Integral R
High Bandwidth
Integrated O Optical
Integral L
Integral C RF and Analog
Decoupling Cap
Dielectric
Filled/Stacked High Speed
RF Microvia Digital/Global
Conductor Interconnect
Low TCE, High E
Base Substrate
39
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Microelectronic Systems
Based on SOP/mSIP • Global
Future Interconnect
0.1u High-end Microprocessor
Ga-As
--------
Si-Ge MS CMOS
MEMS in SOP
Termination Resistor
• Mixed Signal Ics
Copper
Conductors in SOP
(8 levels) Decoupling Cap
• Decoupling
Capacitor in SOP
RF
Low-k
Dielectric • Clock, Power
Low TCE, High & Ground in
Copper E Base
Plugs Substrate SOP
• High Q Inductors
• Optical Wave-
in SOP
guides
in SOP
The Device
40
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Two Components of
SOP 300-400mm Wafer
RF,
Process Bump/Flex Lead Process Digital,
Wafer
Analog,
Semiconductor Wafer Underfill Test &
Optical,
Wafer MEMS Burn-in
Wafer Level Packaging
Wafer Level Packaging 3-D Memory
1
)
2 SOP Substrate Package with RF, Digital, Analog, Optical, MEMS
)
Place Underfilled SOP
or Compliant Lead Die
41
Georgia Tech
Material Needs in Electronics
Current Future
IC 300 mm wafer 400 mm
15-25 mm IC > 35 mm
300-1000 I/Os 5000-10,000+ I/Os
SiO dielectric, Al/Cu metal CNT?, Low K-polymer
Display C Large LCD,
R plasma FET
T Low-cost: $30 (4-6”)
L Large: 40-60”
C
D
Pl
as
m
a
Batteries NiCd Li-Ion (SPE)
NiMH Li-M (SPE)
Zn-air
Storage MR Technology 15 GB/In2 @ $0.03/MB
1.3 GB/In2 @ $0.25/MB
Material Challenges for Each Function
Material Current Property Future Property
Dielectric (Er) 3.5-2.5 (polymer), 5.0 (LTCC) <2 (polymer)
Copper Wiring Electroless/electroplate High speed electroless
Capacitor Ceramic, Er ~=10,000, Cp=20-200 nF/cm2 Nanocomposites, Er=
100-300, same Cp=20-
200 nF/cm2
Resistor Ceramic/glass, 50-100,000 ohm/SQ Nanocomposites,
electroplated, R = 50-
200,000 ohm/SQ
Inductor Ceramic, Q = 20-500, L = 10-1000 (nh) Nanocomposites, Q =
100, L = 10-1000 (nh)
Optical Fiber Embedded, polymer
waveguide
Flip-Chip Pb-Sn Solder Lead-free solders,
conductive adhesives
repairable, CNT,
Graphenes, underfills
Thermal Metal & ceramic heat sinks Single & multiphase
