POSTS & TELECOMMUNICATIONS INSTITUTE OF TECHNOLOGY

DIGITAL
ELECTRONICS

PhD. Trần Thúy Hà

Phone/E-mail: 0912166577 / [email protected]

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 Chapter 0: Number Systems

 Chapter 1: Boolean algebra and logic

gates
 Chapter 2: Combinational logic circuits

 Chapter 3: Sequential logic circuits

 Chapter 4: Semiconductor Memory
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Chapter 2:
Combinational logic
circuits

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 2.1. Binary Codes

 1. Binary Coded Decimal – BCD

 The binary coded decimal (BCD) is a type of binary code used to

represent a given decimal number in an equivalent binary form. BCD-
to-decimal and decimal-to-BCD conversions are very easy.
 The BCD equivalent of a decimal number is written by replacing each
decimal digit in the integer and fractional parts with its four-bit binary
equivalent. As an example, the BCD equivalent of (23.15)10 is written
as (0010 0011.0001 0101)BCD.
 The BCD code described above is more precisely known as the 8421
BCD code, with 8, 4, 2 and 1 representing the weights of different bits
in the four-bit groups, starting from MSB and proceeding towards LSB.

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 Excess-3 Code

 The excess-3 code is another important BCD code. It is

particularly significant for arithmetic operations as it overcomes
the shortcomings encountered while using the 8421 BCD code
to add two decimal digits whose sum exceeds 9. The excess-3
code has no such limitation, and it considerably simplifies
arithmetic operations.
 The excess-3 code for a given decimal number is determined by
adding ‘3’ to each decimal digit in the given number

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 Gray Code

 The Gray code was designed by Frank Gray at Bell Labs and
patented in 1953. It is an unweighted binary code in which two
successive values differ only by 1 bit.
 Binary–Gray Code Conversion

 Method 1: To the right of the adjacent 1's of the binary code,

inverting the bits is gray code
 Method 2: The process of generation of Gray codes using the
reflect and prefixing: Begin 2 bit: 00,01,11,10, we add prefixes
00, next with prefixes 01 we write in reverse order…

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 BCD Codes

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 2.2.

 A combinational circuit consists of logic gates, where outputs are

at any instant and are determined only by the present combination
of inputs without regard to previous inputs or previous state of
outputs

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 2.3. DESIGN PROCEDURE

 Any combinational circuit can be designed by the following steps of design

procedure.
 1. The problem is stated.

 2. Identify the input variables and output functions.

 3. The input and output variables are assigned letter symbols.

 4. The truth table is prepared that completely defines the relationship between
the input variables and output functions.
 5. The simplified Boolean expression is obtained by any method of
minimization—algebraic method, Karnaugh map method, or tabulation method.
 6. A logic diagram is realized from the simplified expression using logic gates

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2.4. ENCODERS
 Decimal-to-binary encoder

Encoder Diagram Truth table Truth table

1 Inputs Outputs Inputs Outputs
A
2 A B C D A B CD
8
3 1 0 0 0 1
Deci 4 ENCODER
B 1 0 0 0 1
4 Outputs
mal 5
C 8421 2 2
0 0 1 0
Input 6
7
2 3 3 0 0 1 1
D
8
1 4 4
0 1 0 0
9
5
0 1 0 1
5

6
0 1 1 0
6

7
0 1 1 1
7
8
1 0 0 0
8
9
1 0 0 1
9

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Truth table  Outputs Functions:

Inputs Outputs
A B CD  A = 8 +9 =  (8,9)
1 0 0 0 1
2
0 0 1 0  B=4+5+6+7 =  ( 4,5,6,7)
3 0 0 1 1
0 1 0 0  C=2+3+6+7 =  (2,3,6,7)
4

0 1 0 1
5  D = 1 + 3 + 5 + 7 + 9 =  (1,3,5,7,9)
6
0 1 1 0
7
0 1 1 1
8
1 0 0 0
9
1 0 0 1

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 Using DeMorgan Laws and using diode

matrics (AND gate) for design curcuit: +5V
R4 R3 R2 R1

A 8  9 8 . 9
1
B  4 5 6  7  4 . 5 . 6 . 7
2
C  2 3 6  7  2 . 3 . 6 . 7
3
D  1 3  5  7  9  1 . 3 . 5 . 7 . 9
4
5
6
7
8
9

A B C D

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 Design a combinational circuit for a BCD-to-seven-segment

decoder:
 Visual display is one of the most important parts of an electronic
circuit. Various types of display devices are commercially
available. Light Emitting Diode or LED is one of the most
widely used display devices and it is economical, low-power-
consuming, and easily compatible in electronic circuits.
 Decimal digits 0 to 9 can be displayed by glowing some
particular LED segments.

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a
a a a
a a

f b f b f b f b f b
f b
g g g g g
c e c e c e c e c
g
e c d d d d d

a a a
a a
d
f b f b f b f b f b
Seven-segment LED display
g g g g g
e c e c e c e c e c

d d d d d

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 Two types of seven-segment display modules are available—

common cathode type and common anode type, the equivalent
electronic circuits are shown in Figures (a) and (b).
 From the equivalent circuit, it is clear that to glow a particular
LED of common cathode type, logic 1 is to be applied at the
anode of that LED as all the cathodes are grounded.
Alternatively, logic 0 is to be applied to glow certain LEDs of
common anode type, as all the anodes are connected to high-
voltage Vcc.

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a a a a
a a a a a a

f b f b f b f b f b f b f b f b f b f b

g g g g g g g g g g
c e c e c e c e c e c e c e c e c e c

d d d d d d d d d d

Truth table for a common anode display

a Deci
mal
A B C D a b c d e f g
f b Num
bers
g
e 0 c 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1
d 0 0 1 0 2
Seven-segment LED display0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9

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Deci
mal
A B C D a b c d e f g
Num
bers
0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 0 0 1 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0 2
0 0 1 1 0 0 0 0 1 1 0 3
0 1 0 0 1 0 0 1 1 0 0 4
0 1 0 1 0 1 0 0 1 0 0 5
0 1 1 0 0 1 0 0 0 0 0 6
0 1 1 1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 0 0 0 8
1 0 0 1 0 0 0 0 1 0 0 9

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 The Boolean expressions for a to g are given as:

a  (0, 2,3,5, 6, 7,8,9)
 Similarly:

b  (0,1,3, 4, 7,8,9)
c  (0,1,3, 4,5, 6, 7,8,9)

 IC 7447, 74247 (common Anode), 7448 (common cathode) is

BCD-to-seven-segment decoder IC

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 2.5. DECODERS

 In a digital system, discrete quantities of information are

represented with binary codes. A binary code of n bits can
represent up to 2n distinct elements of the coded information. A
decoder is a combinational circuit that converts n bits of binary
information of input lines to a maximum of 2n unique output
lines. Usually decoders are designated as an n to m lines decoder,
where n is the number of input lines and m (=2n) is the number of
output lines.

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DECODERS
 The 2-to-4 line decoder consists of two input variables and four
output lines.
D0
A0
2 TO 4 D1
A1
DECODER
D2

D3

The 2-to-4 line decoder Diagram

A1 A0 D0 D1 D2 D3
0 0
0 1
1 0
1 1
Truth Table
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DECODERS

A1 A0 D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
True Table

D0  A1.A 0 

D1  A1 .A 0 

D 2  A1.A 0 
D3 A1.A 0 


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 IC 74154 is 4:16 decoder

D0  Example
D1
A0
D2
A1 D3 a) Construct a 5-to-32 line
A2 Inputs
A3
D4 decoder with the use of a
D5
D6 4-to-16 line decoder.
74154 D7
Lối ra
D8
E1 D9 b) Construct a 6-to-64 line
Inputs D10 decoder with the use of a
Control D11
E2 D12 4-to-16 line decoder.
D13
D14
D15

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2.6. CODE CONVERSION
 To convert from one binary code A to binary code B, the input
lines must provide the bit combination of elements as specifi ed
by A and the output lines must generate the corresponding bit
combinations of code B. A combinational circuit consisting of
logic gates performs this transformation operation.

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 2.6.1 Binary-to-gray Converter

 The bit combinations 3-bit binary code and its equivalent bit
combinations of gray code are listed in the table in Figure
Deci Deci Binary Gray
Binary Gray
mal mal
B2 B1 B0 G2 G1 G0 B2 B1 B0 G2 G1 G0

0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 1 0 0 1
2 0 1 0 2 0 1 0 0 1 1
3 0 1 1 3 0 1 1 0 1 0
4 1 0 0 4 1 0 0 1 1 0
5 1 0 1 5 1 0 1 1 1 1
6 1 1 0 6 1 1 0 1 0 1
7 1 1 1 7 1 1 1 1 0 0
Truth Table Truth Table
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Binary-to-gray Converter

G 2 B2 

G1 B2  B1 
G 0 B1  B0 
B2 G2

B1 G1

B0 G0

Circuit diagram
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 2.6.2 Gray-to-Binary Converter

 The bit combinations 3-bit binary code and its equivalent bit
combinations of gray code are listed in the table in Figure
Deci Gray Binary Deci Gray Binary
mal mal
G2 G1 G0 B2 B1 B0 G2 G1 G0 B2 B1 B0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 1 0 0 1
2 0 1 1 2 0 1 1 0 1 0
3 0 1 0 3 0 1 0 0 1 1
4 1 1 0 4 1 1 0 1 0 0
5 1 1 1 5 1 1 1 1 0 1
6 1 0 1 6 1 0 1 1 1 0
7 1 0 0 7 1 0 0 1 1 1
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Binary-to-gray Converter

B2 G 2 

B1 G1  B2 
B0 G 0  B1 
G2 B2

G1 B1

G0 B0

Circuit diagram
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2.7. MULTIPLEXERS AND DEMULTIPLEXERS
 2.7.1. MULTIPLEXERS OR DATA SELECTORS
 A multiplexer or MUX, also called a data selector, is a
combinational circuit with more than one input line, one output
line and more than one selection line.
 The term multiplex means “many into one.”
 A digital multiplexer of 2n input channels can be controlled by n
numbers of select lines and an input line is selected according to
the bit combinations of select lines

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 Example: Design a 4-to-1 line multiplexer

D0
EN A1 A0 Y

D1 4-to-1 0 x x 0
MULTIPLEXER Y
1 0 0
D2
1 0 1
D3 1 1 0

1 1 1

EN A1 A0 Truth Table of 4-to-1 line multiplexer

Block diagram

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MUX 4:1

D0
EN A1 A0 Y

D1 4-to-1 0 x x 0
MULTIPLEXER Y
1 0 0 D0
D2
1 0 1 D1

D3 1 1 0 D2

1 1 1 D3

EN A1 A0 Truth Table of 4-to-1 line multiplexer

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 Output function:

Y E(D 0 .A1.A 0  D1 . A1.A 0 

 D 2 . A1.A 0  D3 .A1.A 0 )

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74151 is 8:1 multiplexer .

74LS151 a)To design a 16 -to-1 MUX by 8:1
12 I7 E 97
MUX
13 I6 b)To design a 32 -to-1 MUX by 8:1
14 I5 S2 10 MUX
15 I4 S1 11
S0
1 I3
2 I2
3 I1 Y5
4 I0 YN 6

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DEMULTIPLEXERS OR DATA DISTRIBUTORS
 The term “demultiplex” means one into many. Demultiplexing is
the process that receives information from one channel and
distributes the data over several channels.
 A demultiplexer is the logic circuit that receives information
through a single input line and transmits the same information
over one of the possible 2n output lines. The selection of a
specific output line is controlled by the bit combinations of the
selection lines.

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Example: Design 1-to-4 demultiplexer

A1 A0 Y0 Y1 Y2 Y3
0 0
0 1
1 0
1 1
Truth Table – DEMUX 1:4

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A1 A0 Y0 Y1 Y2 Y3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
Truth Table – DEMUX 1:4

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Y0 A1 .A 0 .D
Y1 A1 .A 0 .D
Y2 A1 .A 0 .D
Y3 A1 .A 0 .D

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74138 is DEMUX 1:8. To construct

of a 1-to-16 demultiplexer

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1
D

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Boolean Function New Roman Black 36pt.) DIGITAL ELECTRONICS

 Ex 1: Implement the 3-variable function F (A, B, C)

=  (1, 2, 6, 7). with a multiplexer 4:1
 Solution: MUX 4: 1  need 2 seclector line

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Boolean Function Implementation

Selector inputs Output

A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Truth Table

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Boolean Function Implementation

Selector inputs Output

A B F
0 0 C
0 1 C
1 0 0
1 1 1
Truth table

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Boolean Function Implementation
 Ex: Implement the 3-variable function F (A, B, C) =  (1, 2, 6,
7) with a decoder 3:8

Selector inputs Output

A (A2) B(A1) C(A0) F
0 0 0 0 D0
0 0 1 1 D1
0 1 0 1 D2
0 1 1 0 D3
1 0 0 0 D4
1 0 1 0 D5
1 1 0 1 D6
1 1 1 1
TRẦN THÚY HÀ D7
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Boolean Function Implementation

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 Implement the product-of-sums Boolean function expressed

by (1,2,5) by a suitable multiplexer.

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 Ex: Implement the 4-variable function

 F(A,B,C,D) =  (0,3,5,7,11,12,13,15) with:

 MUX 16:1.
 MUX 8:1 (selection inputs: A,B,C).
 MUX 4:1 (selection inputs: A,B).
 MUX 4:1 (selection inputs: A,B,C).
 MUX 2:1 (selection inputs: A,B,C,D).
 Decoder 4:16.
 Decoder 3:8
 Decoder 2:4
 Decoder 1:2

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A B C D F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0 1
D0
0 0 1 1 1 D1
0
0 1 0 0 0 0
D2 MUX
0 1 0 1 1 D3
0 1 1 0 0
1
D4 16:1
0 Y
0 1 1 1 1 1
D5 F
1 0 0 0 0 0
D6
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1 1 A 3 A2 A 1 A0
D15
1 1 0 0 1
1 1 0 1 1 A B C D
1 1 1 0 0
1 1 1 1 1

Bảng 4-22.
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A B C F
D D0
0 0 0 D
D1
0 0 1 D D
0 1 0 D D
D2 MUX
D3
0 1 1 D
D
D4 8:1
0 Y
1 0 0 0 D
D5 F
1 0 1 D 1
D6
1 1 0 1 D
D7
1 1 1 D A2 A 1 A0

A B C
Truth table

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 Selection Inputs: A,B

AB 00  F C  D
AB 01  F C D  C D D
AB 10  F CD
AB 11  F C D  C D  CD C  CD C  D
C D0
D Y
D1 F

MUX
D2
4:1
D3
A1 A0

A B

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 Selection Inputs: A,B,C

D D0
Y
D D1 F1

D D2 MUX
4:1
D D3
A F
A1 A0
E

B C

“0” D4 A1 A0
Y
D5 F2
D
D6 MUX
“1”
D7
4:1
D

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 Decoder 4:16

D0
A A3
MUX
16:1 D3
F
B D5
A2
D7

C A1

D11
A0 D12
D D13

D15

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 Decoder 3:8

D0

Giải
D3
mã
D5
3:8
D7
A
A2 A1 A0
E
B C D
F
A2 A1 A0

Giải D11
mã D12
D13
3:8
D15
E

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2.8. ADDERS.
 Addition of two binary digits is the most basic arithmetic
operation. The simple addition consists of four possible
elementary operations, which are 0+0 = 0, 0+1 = 1, 1+0 = 1, and
1+1 = 10.
 The first three operations produce a sum of one digit, but the
fourth operation produces a sum consisting of two digits. The
higher significant bit of this result is called the carry.
 A combinational circuit that performs the addition of two bits as
described above is called a half-adder.

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2.8. ADDERS.
1. Design of Half-adder

a0 b0 S0 C0
0 0
0 1
1 0
1 1
Truth table of Half-adder

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Design of Half-adder
.

a0 b0 S0 C0
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
True table of Half-adder
S0 a 0  b0
C0 a 0 .b 0

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a0 S0
a)
HA
b0 C0

a0
S0
b0
b)

C0

a) Block diagram, b) Logic diagram

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2. Design of Full-adders

Truth Table
ai bi Ci S0 C0
0 0 0 0 0
0 1 0
1 0 0
1 1 0
0 0 1
0 1 1
1 0 1
1 1 1

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Truth Table
ai bi Ci S0 C0
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1

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Truth Table
ai bi Ci S0 C0
0 0 0 0 0
S0 ai bi Ci  ai bi Ci  ai bi Ci  ai bi Ci 
0 1 0 1 0
1 0 0 1 0
 Ci (ai bi  ai bi )  Ci (ai bi  ai bi ) 
1 1 0 0 1  Ci (ai  bi )  Ci (ai  bi ) ai  bi  Ci
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1 C0 ai bi Ci  ai bi Ci  ai bi Ci  ai bi Ci
1 1 1 1 1
C0 ai bi (Ci  Ci )  Ci (ai bi  ai bi )
ai bi  ai  bi Ci

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Ci
ai S0
bi
C0

a) Logic diagram
Si

C0 FA Ci

ai bi
b) Block diagram

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FOUR-BIT BINARY PARALLEL ADDER

A3 B3 A2 B2 A1 B1 A0 B0

C3
FA C2
FA C1
FA C0
FA C-1

S3 S2 S1 S0

Carry out ( 23 ) ( 22 ) ( 21 ) ( 20 )

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 Example . Design a BCD-to-Excess-3 code converter.

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2.9. SUBTRACTORS.
 1. Design of Half-subtractors.

a0 b0 S0 B0
0 0
0 1
1 0
1 1
Truth table of Half-subtractors

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a0 b0 S0 B0
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Truth table of Half-subtractors
S0 a 0  b 0
B0 a 0 .b 0

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a0 S0
a)
HS
b0 B0

a0
S0
b0
b)

B0

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a0
S0
b0

C0 / B 0

M=0: a + b
M=1: a - b

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2. Design of Full-subtractors

Truth table
ai bi Bi S0 B0
0 0 0 0 0
0 1 0
1 0 0
1 1 0
0 0 1
0 1 1
1 0 1
1 1 1

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Truth table
ai bi Bi S0 B0
0 0 0 0 0
0 1 0 1 1
1 0 0 1 0
1 1 0 0 0
0 0 1 1 1
0 1 1 0 1
1 0 1 0 0
1 1 1 1 1

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 Outputs function:
Truth table

ai bi Bi S0 B0 S0 ai bi Bi  ai bi Bi  ai bi Bi  ai bi Bi 
0 0 0 0 0  Bi (ai bi  ai bi )  Bi (ai bi  ai bi ) 
0 1 0 1 1
 Bi (ai  bi )  Bi (ai  bi ) ai  bi  Bi
1 0 0 1 0
1 1 0 0 0
B0 ai bi Bi  ai bi Bi  ai bi Bi  ai bi Bi
0 0 1 1 1
0 1 1 0 1
B0 ai bi ( Bi  Bi )  Bi (ai bi  ai bi )
1 0 1 0 0 ai bi  ai  bi  Bi
1 1 1 1 1

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2.9. MAGNITUDE COMPARATOR
 A magnitude comparator is one of the useful combinational
logic networks and has wide applications. It compares two
binary numbers and determines if one number is greater than,
less than, or equal to the other number.
 If two binary numbers are considered as A and B, the magnitude
comparator gives three outputs for A > B, A < B, and A = B.

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2.9.1. Design a 1-bit magnitude comparator

Truth table
ai bi f< f= f>
0 0
0 1
1 0
1 1

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2.9.1. Design a 1-bit magnitude comparator

Truth table
ai bi f< f= f>
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

 Outputs function: f  a i . b i
f   a i  bi
f  a i . b i
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2.9.1. Design a 1-bit magnitude comparator

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2.9.2. Design a 4-bit magnitude comparator
 Design a 4-bit magnitude comparator

 A = a3a2a1a0 với B = b3b2b1b0.

 A > B if:

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2.9.2. Design a 4-bit magnitude comparator
 Design a 4-bit magnitude comparator

 A = a3a2a1a0 với B = b3b2b1b0.

 A > B if:
 or a3 > b3,
 or a3 = b3, and a2 > b2,
 or a3 = b3, and a2 = b2, and a1 > b1,
 or a3 = b3, and a2 = b2, and a1 = b1, and a0 > b0.

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2.9.2. Design a 4-bit magnitude comparator
 Output function:

f  a3 .b3  a3  b3 .a2 .b2  a3  b3 .a2  b2 .a1.b1  a3  b3 .a2  b2 .a1  b1.a0 .b0

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2.9.2. Design a 4-bit magnitude comparator

a3
b3

a2
b2

f>
a1
b1

a0
b0

Logic diagram

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2.10. PARITY GENERATOR AND CHECKER

 Parity is a very useful tool in information processing in digital

computers to indicate any presence of error in bit information.
 To indicate any occurrence of error, an extra bit is included with
the message according to the total number of 1s in a set of data,
which is called parity.
 If the extra bit is considered 0 if the total number of 1s is even
and 1 for odd quantities of 1s in a set of data, then it is called
even parity.
 On the other hand, if the extra bit is 1 for even quantities of 1s
and 0 for an odd number of 1s, then it is called odd parity

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2.10.1. Parity Generator
 A table illustrates even parity as
well as odd parity for a message
consisting of three bits.
True table
 If the message bit combination is
Inputs Outputs
designated as D3 D2 D1, and Pe ,
D3 D2 D1 Pe Po
Po are the even and odd parity 0 0 0 0 1
respectively, then it is obvious 0 0 1 1 0
from the table that the Boolean 0 1 0 1 0
expressions of even parity and odd 0 1 1 0 1
parity are: 1 0 0 1 0
Pe D3  D2  D1 1 0 1 0 1
Po D3  D2  D1 1 1 0 0 1
1 1 1 1 0

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Even parity generator

Odd parity generator.

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 Parity Checker

 The message bits with the parity bit are transmitted to their
destination, where they are applied to a parity checker circuit.
The circuit that checks the parity at the receiver side is called the
parity checker.
 The parity checker circuit produces a check bit and is very
similar to the parity generator circuit. If the check bit is 1, then it
is assumed that the received data is incorrect. The check bit will
be 0 if the received data is correct

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Parity Checker
True table

Even
Even
Inputs Parity Parity
Checker
D3 D2 D1 Pe Ce
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
Ce D3  D2  D1  Pe
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 Logic diagram:

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Parity Checker
True table

Odd
Odd
Inputs Parity Parity
Checker
D3 D2 D1 Po Co
0 0 0 1 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 0
1 1 0 1 0
1 1 1 0 0

C0 D3  D2  D1  Po

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 Logic diagram:

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74LS180
8 9 10 11 12 13 1 2

I0 I1 I2 I3 I4 I5 I6 I7
4 OI
54/74180
3 EI
SE SO

5 6
VCC = 14
GND = 7

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Error-correcting Codes
 For correction of errors we will now discuss a code called the
Hamming code.
 Hamming Code

 This coding had been developed by R. W. Hamming where one

or more parity bits are added to a data character methodically in
order to detect and correct errors.

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2.11. Hamming Code
 P: Parity bit ; D: Data bit
D  P  1 2 P
2.11.1. Encode a Hamming code
We can see from the generalized form of the code that all bit
positions that are powers of 2 (positions 1, 2, 4, 8, 16, … ) are used
as parity bits.
All other bit positions (positions 3, 5, 6, 7, 9, 10, 11, …) are used to
encode data
Each parity bit is allotted a group of bits from the data bits in the
code word, and the value of the parity bit (0 or 1) is used to give it
certain parity.

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Encode a Hamming code
 Ex: D= 5  P= 4  The 5-bit Hamming (5, 4) code word:

9 8 7 6 5 4 3 2 1
D5 P8 D4 D3 D2 P4 D1 P2 P1
 Bits P1 produce parity bits for the bit fields: 1,3,5,7,9…

 Bits P2 produce parity bits for the bit fields: 1,2,3,6,7,10…

 Bits P4 produce parity bits for the bit fields: 4,5,6,7,11,…

 Bits P8 produce parity bits for the bit fields: 8,9,10,11,12…

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Encode a Hamming code
 The Boolean expressions of Even parity and odd parity are:

Pe D1  D2  D3  ....
Po D1  D2  D3  ....

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Encode a Hamming code
 Ex: Encode data bits 101101 into a even parity Hamming
code
 Do D = 6 => P = 4

10 9 8 7 6 5 4 3 2 1
1 0 P8 1 1 0 P4 1 P2 P1
 P?

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Ex:

 P1:

 P1 = position 3  position 5  position 7 position 9

 P1 = 1  0  1 0 → P1 = 0

 P2:

 P2 = pos. 3  pos. 6  pos.7  pos. 10

 P2 = 1  1  1 1 → P2 = 0

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Ex:
 P4:

 P4 = pos. 5  pos. 6  pos. 7

 P4 = D2  D3 D4

 P4 = 0  1 1 → P4 = 0

 P8:

 P8 = pos. 9  pos. 10

 P8 = D5  D6

 P8 = 0  1 → P8 = 1
 =>>
1 0 1 1 1 0 0 1 0 0
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 Ex: Encode data bits 11001 into a odd parity Hamming code
9 8 7 6 5 4 3 2 1
1 P8 1 0 0 P4 1 P2 P1

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 P1 = 0

 P2 = 1

 P4 = 0

 P8 = 0

  odd parity Hamming code: 1 0100 0110

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Ex:

D6 D5 D4 D3 D2 D1 P1 P2 P4 P8

+
+
+
+

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2.11.2. Decode a Hamming code
 To decode a Hamming code, checking needs to be done for odd
parity over the bit fields in which even parity was previously
established.

 S1 = P1  pos. 3  pos. 5  pos. 7 pos. 9 ...

 S2 = P2  pos. 3  pos. 6  pos. 7 pos. 10 ...

 S4 = P4  pos. 5  pos. 6  pos. 7 ...

 S8 = P8  pos. 9  pos. 10 ...

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  For Even parity Hamming code: DIGITAL ELECTRONICS

 If S8S4S2S1 = 0000, we conclude there is no error in the Hamming

code. On the other hand, if it has a nonzero value, it indicates the
bit position in error.

 For example, if S8S4S2S1 = 0110, then bit 6 is in error. To correct

this error, bit 6 has to be complemented.
 For Odd parity Hamming code:

 If S8S4S2S1 = 1111, we conclude there is no error in the Hamming

code. On the other hand, if it different 1111, then
SSSS
indicates the bit position in error: 8 4 2 1

 For example, if S8S4S2S1 = 0110, then bit 9 is in error. To correct

this error, bit 9 has to be complemented.
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2.11.2. Decode a Hamming code
 Ex: A 10-bit even Hamming code is received as 10 0110 0100.
What is its correct code?

1 0 0 1 1 0 0 1 0 0

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2.11.2. Decode a Hamming code

 Si

10 9 8 7 6 5 4 3 2 1
1 0 0 1 1 0 0 1 0 0

S1 = 0
S2 = 0
S4 = 0
S8 = 1

S8S4S2 S1 = 10002 = 810

Bit position in error: 8.
1 0 1 1 1 0 0 1 0 0
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2.11.2. Decode a Hamming code

D6 D5 P8 D4 D3 D2 P4 D1 P2 P1 S1 S2 S4 S8

+
+
+
+

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 Ex: A 10-bit odd Hamming code is received as 1 1100 0110.

What is its correct code?

9 8 7 6 5 4 3 2 1
1 1 1 0 0 0 1 1 0
S1 = 1
S2 = 1
S4 = 1
S8 = 0

S8S4S2 S1 = 01112
S8 S 4 S 2 S1 10002 810
Bit position in error:

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