Microprocessors, Microcontrollers

and Embedded Systems

Basic I/O Interface

Introduction
• This chapter outlines some of the basic
methods of communications, both serial and
parallel, between humans or machines and
the microprocessor.
• We first introduce the basic I/O interface and
discuss decoding for I/O devices.
• Then, we provide detail on parallel and serial
interfacing, both of which have a variety of
applications.
11–1 INTRO TO I/O INTERFACE
• I/O instructions (IN, INS, OUT, and OUTS) are
explained.
• Also isolated (direct or I/O mapped I/O) and
memory-mapped I/O, the basic input and output
interfaces, and handshaking.
• Knowledge of these topics makes it easier to
understand the connection and operation of the
programmable interface components
and I/O techniques.
The I/O Instructions
• One type of instruction transfers information
to an I/O device (OUT).
• Another reads from an I/O device (IN).
• Instructions are also provided to transfer
strings of data between memory and I/O.
– INS and OUTS, found except the 8086/8088
• Instructions that transfer data between an I/O
device and the microprocessor’s accumulator
(AL, AX, or EAX) are called IN and OUT.
• The I/O address is stored in register DX as a
16-bit address or in the byte (p8) immediately
following the opcode as an 8-bit address.
– Intel calls the 8-bit form (p8) a fixed address
because it is stored with the instruction, usually
in a ROM
• The 16-bit address is called a variable
address because it is stored in a DX, and
then used to address the I/O device.
• Other instructions that use DX to address
I/O are the INS and OUTS instructions.
• I/O ports are 8 bits in width.
– a 16-bit port is actually two consecutive 8-bit
ports being addressed
– a 32-bit I/O port is actually four 8-bit ports
• When data are transferred using IN or OUT,
the I/O address, (port number or simply
port), appears on the address bus.
• External I/O interface decodes the port
number in the same manner as a memory
address.
– the 8-bit fixed port number (p8) appears on
address bus connections A7–A0 with bits
A15–A8 equal to 000000002
– connections above A15 are undefined for
I/O instruction
• The 16-bit variable port number (DX)
appears on address connections A15–A0.
• The first 256 I/O port addresses (00H–FFH)
are accessed by both fixed and variable I/O
instructions.
• INS and OUTS instructions address an I/O
device using the DX register.
– but do not transfer data between accumulator
and I/O device as do the IN/OUT instructions
– Instead, they transfer data between memory
and the I/O device
• Pentium 4 and Core2 operating in the 64-bit
mode have the same I/O instructions.
• There are no 64-bit I/O instructions in the 64-
bit mode.
– most I/O is still 8 bits and likely will remain so
Isolated and Memory-Mapped I/O
• Two different methods of interfacing I/O:
isolated I/O and memory-mapped I/O.
• In isolated I/O, the IN, INS, OUT, and OUTS
transfer data between the microprocessor’s
accumulator or memory and the I/O device.
• In memory-mapped I/O, any instruction that
references memory can accomplish the
transfer.
• The PC does not use memory-mapped I/O.
Isolated I/O
• The most common I/O transfer technique
used in the Intel-based system is isolated I/O.
– isolated describes how I/O locations are isolated
from memory in a separate I/O address space
• Addresses for isolated I/O devices, called
ports, are separate from memory.
• Because the ports are separate, the user can
expand the memory to its full size without
using any of memory space for I/O devices.
• A disadvantage of isolated I/O is that data
transferred between I/O and microprocessor
must be accessed by the IN, INS, OUT, and
OUTS instructions.
• Separate control signals for the I/O space are
developed (using M/IO and W/R ), which
indicate an I/O read (IORC) or an I/O write
(RD) operation.
• These signals indicate an I/O port address,
which appears on the address bus, is used
to select the I/O device.
Figure 11–1 The memory and I/O maps for the 8086/8088 microprocessors. (a)
Isolated I/O. (b) Memory-mapped I/O.
– in the PC, isolated I/O
ports are used to control
peripheral devices
– an 8-bit port address is
used to access devices
located on the system
board, such as the timer
and keyboard interface
– a 16-bit port is used to
access serial and parallel
ports, video and disk drive
systems
Memory-Mapped I/O
• Memory-mapped I/O does not use the IN, INS,
OUT, or OUTS instructions.
• It uses any instruction that transfers data between
the microprocessor and memory.
– treated as a memory location in memory map
• Advantage is any memory transfer instruction can
access the I/O device.
• Disadvantage is a portion of memory system is
used as the I/O map.
– reduces memory available to applications
Personal Computer I/O Map
– the PC uses part of I/O map for
dedicated functions, as shown here
– I/O space between ports 0000H and
03FFH is normally reserved for the
system and ISA bus
– ports at 0400H–FFFFH are generally
available for user applications, main-
board functions, and the PCI bus
– 80287 coprocessor uses 00F8H–00FFH,
so Intel reserves I/O ports 00F0H–00FFH

Figure 11–2 I/O map of a personal computer illustrating many of the fixed I/O areas.
Basic Input and Output Interfaces
• The basic input device is a set of three-state
buffers.
• The basic output device is a set of data
latches.
• The term IN refers to moving data from the
I/O device into the microprocessor and
• The term OUT refers to moving data out of
the microprocessor to the I/O device.
The Basic Input Interface
• Three-state buffers are used to construct the
8-bit input port depicted in Figure 11–3.
• External TTL data are connected to the inputs
of the buffers.
– buffer outputs connect to the data bus
• The circuit of allows the processor to read the
contents of the eight switches that connect to
any 8-bit section of the data bus when the
select signal becomes a logic 0.
Figure 11–3 The basic input interface illustrating the connection of eight switches.
Note that the 74ALS244 is a three-state buffer that controls the application of the
switch data to the data bus.
• When the IN instruction executes, contents
of the switches copy to the AL register.
• Sometimes it appears as a discrete part of the
circuit, as shown in Figure 11–3.
– also built into a programmable I/O devices
• Sixteen- or 32-bit data can also be interfaced
but is not nearly as common as 8-bit data.
The Basic Output Interface
• Receives data from the processor and usually
must hold it for some external device.
– latches or flip-flops, like buffers in the input
device, are often built into the I/O device
• Fig 11–4 shows how eight light-emitting diodes
(LEDs) connect to the processor through a set
of eight data latches.
• The latch stores the number output by the
microprocessor from the data bus so that the
LEDs can be lit with any 8-bit binary number.
Figure 11–4 The basic output interface connected to a set of LED displays.
• Latches hold the data because when the
processor executes an OUT, data are only
present on the data bus for less than 1.0 µs.
– the viewer would never see the LEDs illuminate
• When the OUT executes, data from AL, AX,
or EAX transfer to the latch via the data bus.
• Each time the OUT executes, the SEL signal
activates, capturing data to the latch.
– data are held until the next OUT
• When the output instruction is executed, data
from the AL register appear on the LEDs.
Handshaking
• Many I/O devices accept or release information
slower than the microprocessor.
• A method of I/O control called handshaking or
polling, synchronizes the I/O device with the
microprocessor.
• An example is a parallel printer that prints a few
hundred characters per second .
• The processor can send data much faster.
– a way to slow the microprocessor down to match
speeds with the printer must be developed
10–2 ADDRESS DECODING
• In order to attach a memory device to the
microprocessor, it is necessary to decode
the address sent from the microprocessor.
• Decoding makes the memory function at a unique
section or partition of the memory map.
• Without an address decoder, only one
memory device can be connected to a
microprocessor, which would make it
virtually useless.
Simple NAND Gate Decoder
• When the 2K  8 EPROM is used, address
connections A10–A0 of 8088 are connected
to address inputs A10–A0 of the EPROM.
– the remaining nine address pins (A19–A11)
are connected to a NAND gate decoder
• The decoder selects the EPROM from one of the
2K-byte sections of the 1M-byte memory system in
the 8088 microprocessor.
• In this circuit a NAND gate decodes the memory
address, as seen in Figure 10-13.
Figure 10–13 A simple NAND gate decoder that selects a 2716 EPROM for
memory location FF800H–FFFFFH (refer to the figure in the book ).
• If the 20-bit binary address, decoded by the
NAND gate, is written so that the leftmost nine
bits are 1s and the rightmost 11 bits are don’t
cares (X), the actual address range of the
EPROM can be determined.
– a don’t care is a logic 1 or a logic 0, whichever
is appropriate
• Because of the excessive cost of the NAND
gate decoder and inverters often required,
this option requires an alternate be found.
The 3-to-8 Line Decoder (74LS138)

– a common integrated circuit decoder found

in many systems is the 74LS138 3-to-8 line
decoder.
Figure 10–14 The 74LS138 3-to-8 line decoder and function table.
Figure 10–15 A circuit that uses eight 2764 EPROMs for a 64K  8 section of
memory in an 8088 microprocessor-based system. The addresses selected in this
circuit are F0000H–FFFFFH.
– all address connections from the
8088 are connected to this circuit.
– the decoder’s outputs are
connected to the CE inputs of the
EPROMs,
– the RD signal from the 8088 is
connected to the OE inputs of the
EPROMs
• In this circuit, a three-input NAND gate is
connected to address bits A19–A17.
• When all three address inputs are high, the
output of this NAND gate goes low and
enables input G2B of the 74LS138.
• Input G1 is connected directly to A16.
• In order to enable this decoder, the first four
address connections (A19–A16) must all be
high.
• Address inputs C, B, and A connect to
microprocessor address pins A15–A13.
• These three address inputs determine which
output pin goes low and which EPROM is
selected whenever 8088 outputs a memory
address within this range to the memory
system.
11–2 I/O PORT ADDRESS
DECODING
• Very similar to memory address decoding,
especially for memory-mapped I/O devices.
• The difference between memory decoding
and isolated I/O decoding is the number of
address pins connected to the decoder.
• In the personal computer system, we always
decode all 16 bits of the I/O port address.
Decoding 8-Bit I/O Port Addresses
• Fixed I/O instruction uses an 8-bit I/O port address
that on A15–A0 as 0000H–00FFH.
– we often decode only address connections
A7–A0 for an 8-bit I/O port address
• The DX register can also address I/O ports 00H–
FFH.
• If the address is decoded as an 8-bit address, we
can never include I/O devices using a 16-bit
address.
– the PC never uses or decodes an 8-bit address
• Figure 11–10 shows a 74ALS138 decoder
that decodes 8-bit I/O ports F0H - F7H.
– identical to a memory address decoder except
we only connect address bits A7–A0 to the
inputs of the decoder
• Figure 11–11 shows the PLD version, using a
GAL22V10 (a low-cost device) for this
decoder.
• The PLD is a better decoder circuit because
the number of integrated circuits has been
reduced to one device.
Figure 11–10 A port decoder that decodes 8-bit I/O ports. This decoder generates
active low outputs for ports F0H–F7H.
Figure 11–11 A PLD that generates part selection signals
Decoding 16-Bit I/O Port Addresses
• PC systems typically use 16-bit I/O addresses.
– 16-bit addresses rare in embedded systems
• The difference between decoding an 8-bit and
a 16-bit I/O address is that eight additional
address lines (A15–A8) must be decoded.
• Figure 11–12 illustrates a circuit that contains
a PLD and a 4-input NAND gate used to
decode I/O ports EFF8H–EFFFH.
• PLD generates address strobes for I/O ports
Figure 11–12 A PLD that decodes 16-bit I/O ports EFF8H through EFFFH.
• I/O reads don’t require separate strobes.
– as with memory, the processor reads only the
byte it expects and ignores the other byte
– a read can cause problems when an I/O device
responds incorrectly to a read operation
11–3 THE PROGRAMMABLE
PERIPHERAL
• 82C55 programmable peripheral interface
(PPI) is a popular, low-cost interface
component found in many applications.
• The PPI has 24 pins for I/O, programmable in
groups of 12 pins and groups that operate in
three distinct modes of operation.
• 82C55 can interface any TTL-compatible
I/O device to the microprocessor.
• The 82C55 (CMOS version) requires wait
states if operated with a processor using
higher than an 8 MHz clock.
• Because I/O devices are inherently slow, wait
states used during I/O transfers do not impact
significantly upon the speed of the system.
• The 82C55 still finds application even in the
latest Core2-based computer system.
• 82C55 is used for interface to the keyboard
and parallel printer port in many PCs.
– found as a function within an interfacing chip set
– also controls the timer and reads data from the
keyboard interface
• An experimentation board is available that
plugs into the parallel port of a PC, to allow
access to an 8255 located on the board.
• The 8255 is programmed in either assembly
language or Visual C++ through drivers
available with the board.
Basic Description of the 82C55
• Fig 11–18 shows pin-outs of the 82C55 in
DIP and surface mount (flat pack) format.
• The three I/O ports (labeled A, B, and C) are
programmed as groups.
– group A connections consist of port A (PA7–PA0) and
the upper half of port C (PC7–PC4)
– group B consists of port B (PB7–PB0) and the lower half
of port C (PC3–PC0)
• 82C55 is selected by its CS pin for programming
and reading/writing to a port.
Figure 11–18 The pin-out of the 82C55 peripheral interface adapter (PPI).
• Table 11–2 shows I/O port assignments used
for programming and access to the I/O ports.
• In the PC, a pair of 82C55s, or equivalents,
are decoded at I/O ports 60H–63H and also
at ports 378H–37BH.
• The 82C55 is a fairly simple device to
interface to the microprocessor and program.
• For 82C55 to be read or written, the CS input
must be logic 0 and the correct I/O address
must be applied to the A1 and A0 pins.
• Remaining port address pins are don’t cares.
• Fig 11–19 shows an 82C55 connected to the
80386SX (microprocessor) so it functions at 8-
bit addresses C0H (port A), C2H (port B), C4H
(port C),
and C6H (command register).
– this interface uses the low bank of the I/O map
• All 82C55 pins are direct connections to the
80386SX, except the CS pin. The pin is
decoded/selected by a 74ALS138 decoder.
• A RESET to 82C55 sets up all ports as
simple input ports using mode 0 operation.
– initializes the device when the processor is reset
Figure 11–19 The 82C55 interfaced to the low bank of the 80386SX microprocessor.
• After a RESET, no other commands are
needed, as long as it is used as an input
device for all three ports.
• 82C55 is interfaced to the PC at port
addresses 60H–63H for keyboard control.
– also for controlling the speaker, timer, and other
internal devices such as memory expansion
• It is also used for the parallel printer port at
I/O ports 378H–37BH.
Programming the 82C55
• 82C55 is programmed through two internal
command registers shown in Figure 11–20.
• Bit position 7 selects either command byte A
or command byte B.
– command byte A programs functions of group
A and B
– byte B sets (1) or resets (0) bits of port C only
if the 82C55 is programmed in mode 1 or 2
• Group B (port B and the lower part of port C)
are programmed as input or output pins.
Figure 11–20 The command byte of the command register in the 82C55. (a)
Programs ports A, B, and C. (b) Sets or resets the bit indicated in the select a bit field.

– group B operates in mode 0 or

mode 1
– mode 0 is basic input/output mode
that allows the pins of group B to
be programmed as simple input
and latched output connections
– Mode 1 operation is the strobed
operation for group B connections
– data are transferred through port B
– handshaking signals are provided
by port C
• Group A (port A and the upper part of port C)
are programmed as input or output pins.
• Group A can operate in modes 0, 1, and 2.
– mode 2 operation is a bidirectional mode of
operation for port A
• If a 0 is placed in bit position 7 of the
command byte, command byte B is selected
• This allows any bit of port C to be set (1) or
reset (0), if the 82C55 is operated in either
mode 1 or 2.
– otherwise, this byte is not used for programming
Mode 0 Operation
• Mode 0 operation causes 82C55 to function:
– as a buffered input device
– as a latched output device
• Fig 11–21 shows 82C55 connected to a
set of eight seven-segment LED displays.
• These are standard LEDs.
– the interface can be modified with a change
in resistor values for an organic LED (OLED)
display or high-brightness LEDs
Key Matrix Interface
• Keyboards come in a variety of sizes, from
standard 101-key QWERTY keyboards to
special keyboards that contain 4 to 16 keys.
• Fig 11–25 is a key matrix with 16 switches
interfaced to ports A and B of an 82C55.
– the switches are formed into a 4  4 matrix,
but any matrix could be used, such as a 2  8
• The keys are organized into four rows and
columns: (ROW0–ROW3) (COL0–COL3)
Figure 11–25 A 4  4 keyboard matrix connected to an 8088 microprocessor through
the 82C55 PIA.

– port A is programmed as an
input port to read the rows
– port B is programmed as an
output port to select a column
Mode 1 Strobed Input
• Causes port A and/or port B to function as
latching input devices.
– allows external data to be stored to the port
until the microprocessor is ready to retrieve it
• Port C is used in mode 1 operation—not for
data, but for control or handshaking signals.
– to help operate either or both port A and B as
strobed input ports
• Fig 11–27 shows how both ports are structured
for mode 1 strobed input operation.
Figure 11–27 Strobed input operation (mode 1) of the 82C55. (a) Internal structure
and (b) timing diagram.
Signal Definitions for Mode 1
Strobed Input
STB
• The strobe input loads data to the port latch,
which holds the information until it is input to
the microprocessor via the IN instruction.

IBF
• Input buffer full is an output indicating that
the input latch contains information.
INTR
• Interrupt request is an output that requests an interrupt. The
INTR pin becomes a logic 1 when STB returns to a logic 1.
Cleared when data are input from the port by the processor.

INTE
• Interrupt enable signal is neither input nor output; it is an internal
bit programmed via
port PC4 (port A) or PC2 (port B) bit position.
PC7, PC6
• The port C pins 7 and 6 are general-purpose
I/O pins that are available for any purpose.
Difference between TEST and
AND operation
• TEST (Test) performs the logical "and" of the
two operands, clears OF and CF, leaves AF
undefined, and updates SF, ZF, and PF. The
flags can be tested by conditional control
transfer instructions or by the byte-set-on-
condition instructions. The operands may be
doublewords, words, or bytes.
Difference between TEST and
AND operation
• The difference between TEST and AND is that
TEST does not alter the destination operand.
The TEST instruction performs a bitwise AND
on two operands. The flags SF, ZF, PF, CF,
OF and AF are modified while the result of
the AND is discarded.
Difference between CMP and SUB
operation
• Cmp versus Sub - Recall that the Sub subtracts producing a result but also
setting flags (CF, OF, SF, ZF). The Cmp instruction is identical to the Sub but
only sets flags. To see the difference consider the following example noticing that the
value of the Ah register changes with the Sub but not the Cmp.
Introduction
• The DMA (Direct Memory Access) I/O
technique provides direct access to the
memory while the microprocessor is
temporarily disabled.
• Some disk memory systems and video
systems that are often DMA-processed.
• Disk memory includes floppy, fixed, and
optical disk storage. Video systems include
digital and analog monitors.

66
Basic DMA Definitions
• Direct memory accesses normally occur
between an I/O device and memory without
the use of the microprocessor.
– a DMA read transfers data from the memory
to the I/O device
– A DMA write transfers data from an I/O device
to memory
• Memory & I/O are controlled simultaneously.
– which is why the system contains separate
memory and I/O control signals

67
13–1 BASIC DMA OPERATION
• Two control signals are used to request and
acknowledge a direct memory access (DMA)
transfer in the microprocessor-based system.
– the HOLD pin is an input used to request a
DMA action
– the HLDA pin is an output that acknowledges
the DMA action
• Figure 13–1 shows the timing that is typically
found on these two DMA control pins.

68
Figure 13–1 HOLD and HLDA timing for the microprocessor.

– HOLD is sampled in any clocking cycle

– when the processor recognizes the hold, it stops
executing software and enters hold cycles
– HOLD input has higher priority than INTR or NMI
– the only microprocessor pin that has a higher
priority than a HOLD is the RESET pin

69
• HLDA becomes active to indicate the
processor has placed its buses at high-
impedance state.
– as can be seen in the timing diagram, there are
a few clock cycles between the time that HOLD
changes and until HLDA changes
• HLDA output is a signal to the requesting
device that the processor has relinquished
control of its memory and I/O space.
– one could call HOLD input a DMA request
input and HLDA output a DMA grant signal

70
• A DMA read causes the MRDC and IOWC
signals to activate simultaneously.
– transferring data from memory to the I/O device
• A DMA write causes the MWTC and IORC
signals to both activate.
• The DMA controller provides memory with its
address, and controller signal (DACK) selects
the I/O device during the transfer.

71
DMA Cycle stealing and
interleaved DMA
• DMA transfers can either occur one word at a time or all at once in burst
mode. If they occur a word at a time, this can allow the CPU to access
memory on alternate bus cycles - this is called cycle stealing since the
DMA controller and CPU contend for memory access. In burst mode DMA,
the CPU can be put on hold while the DMA transfer occurs and a full block
of possibly hundreds or thousands of words can be moved. When memory
cycles are much faster than processor cycles, an interleaved DMA cycle is
possible, where the DMA controller uses memory while the CPU cannot.