MICROPROCESSORS AND

MICROCONTROLLERS
B. Tech – CSE (IOT)
III Year II Semester
 UNIT - III

Interfacing with 8086: Interfacing with RAMs,

ROMs along with the explanation of timing diagrams.
8255 PPI – various modes of operation. Interfacing
with key boards, ADCs, and DACs Stepper Motor.
Interrupt structure of 8086. Vector interrupt table.
Interrupt service routines. 8259 PIC Architecture and
interfacing cascading of interrupt controller and its
importance.
Applications: Interfacing of a Temperature
sensor with 8086

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8086 Microprocessor
Interfacing I/O and peripheral devices

I/O devices

 For communication between microprocessor and

outside world

 Keyboards, CRT displays, Printers, Compact Discs

etc.

 Ports / Buffer IC’s

Microprocessor I/ O devices
(interface circuitry)

 Data transfer types

Memory mapped
Programmed I/ O
Data transfer is accomplished I/O mapped
through an I/O port
controlled by software

Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 3
bypassing the microprocessor
 Accessing I/O Devices

Processor Memory

BUS

I/O Device 1 I/O Device 2

 Parallel I/O

• I/O devices connect to processor through

PORTS
• Ports are:
 registers (part of the I/O interface)
 8, 16, or 32 bits wide
Addressed in the range 0000-FFFFh
Accessed with 2 instructions – IN, OUT
 Modes of I/O Instructions

• Direct I/O – the port address is one of the

operands.
– Address must be 00-FFh.
• IN AL, 27h
– Data flows through the accumulator
• MOV AX, BX
• OUT 26h, AX ; move 16-bit data from AX to port
; 26h (AL to 26h and AH to
27h)
• Indirect I/O – the port address is preloaded
into DX
– Address can be 0000-FFFFh
• String I/O – allows data to pass directly
through the accumulator (from I/O device to
 80x86 I/O Instructions

Type Instruction Description

Direct IN AL, port input data to accumulator
IN AX, port port must be in range 00-FFh
IN EAX, port

OUT port, AL output data from accumulator

OUT port, AX port must be in range 00-FFh
OUT port, EAX

Indirect IN AL, DX input data to accumulator

IN AX, DX port address in DX must be in range 0000-FFFFh
IN EAX, DX

OUT DX, AL output data from accumulator

OUT DX, AX port address in DX must be in range 0000-FFFFh
OUT DX, EAX

String INSB input data to memory location DS:SI or DS:ESI

INSW port address in DX must be in range 0000-FFFFh
INSD

OUTSB output data from memory location DS:SI or DS:ESI

OUTSW port address in DX must be in range 0000-FFFFh
OUTSD
Ways to Differentiate I/O

• Memory-Mapped versus I/O-Mapped Ports

 address of 80x86 processors is divided into 1MB of
memory space and 64K of I/O space.
Memory
Space
20 bit address

I/O Space

address
16-bit

M/IO’ = 0
M/IO’ = 1

 With memory-mapped I/O, because I/O ports are

mapped to a memory address, any of the memory
read/write instructions are available to use. Address
can be computed using any of the addressing
modes.
 With I/O mapped ports, restricted to simple IN/OUT
instructions. Address must be in DX.
Memory-Mapped I/O
• I/O Devices and memory share the
same address space.
– Each I/O Device is assigned a unique set of
addresses.
– When the processor places a particular
address on the address lines, the device
recognizing this address responds to the
commands on the control lines.
– The processor requests either a read or a
write operation, and the requested data is
transferred over the data lines.
– Any machine instruction that can access
memory can be used to transfer data
to/from I/O devices.
• Mov datain, R0
 Three types of I/O Strategies

• Polled I/O

• Interrupt Driven I/O

• DMA I/O
Polled IO versus Interrupt Driven I/O

• Polled IO – processor continually checks

IO device to see if it is ready for data
transfer
– Inefficient, processor wastes time checking for
ready condition
• Interrupt Driven IO – IO device
interrupts processor when it is ready for
data transfer
– Processor can be doing other tasks while
waiting for last data transfer to complete –
very efficient.
 82C55
Programmable Peripheral Interface

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 About 82C55

• It is used to interface 8 bit

parallel I/O device to a
microprocessor.
• It is used to interface to the
keyboard and a parallel printer
port in PCs.
• PPI has 24 pins for I/O that are
programmable in groups of 12
pins and has three distinct modes
of operation.
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 8255 Block Diagram

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 82C55 : Pin Layout

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 Control register for mode
Programming 82C55

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 8255 operating modes

There are 2 operating modes of 8255 :

1. Bit set reset (BSR) mode
2. Input/output mode (I/O)
Mode 0 – Simple or basic I/O mode
Mode 1 – Handshake or strobed I/O
Mode 2 – Bidirectional I/O

Bit set reset (BSR) mode – This mode is used to set or reset the bits of
port C only, and selected when the most significant bit (D7) in the control
register is 0.

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 Input/output mode (I/O)

Mode 0

Port A Upper C Lower C Port B

• This mode provides simple input and output

operations for each of the three ports.
• No “handshaking” is required, data is simply
written to or read from a specified port.
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C D E F

8 9 A B

4 5 6 7

0 1 2 3

0 on Port A
selects the row

If a key is pressed,
The corresponding
Column bit will
Make Port B bit 1

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82C55: Mode 0, Interfacing of Stepper motor with 8086

Step angle,

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Winding number 1
1

a b
1
N
One
6 pole rotor S step
N N
2 2
S S
N
Winding number 2 S
1
a b

2
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82C55: Mode 0, 7 segment Multiple digit Display

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82C55: Mode 0, 7 segment multiple digit Display

• Port A provides the segment data

inputs to display and port B provides
a means of selecting one display
position at a time.
• Different values are displayed in each
digit via fast time division
multiplexing.

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 Mode 1

Group
Group A
A Group
Group B
B

Port A Upper C Lower C Port B

Hand shaking
signals

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 Mode 1 Basic functional Definitions

• Two Groups (Group A and Group B).

• The 8-bit data port can be either input or
output.
• Pins of port C provide Hand shaking
signals.

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 82C55: Mode 1 Input Exam.

• Keyboard encoder encodes the key-switch

into 8 bit ASCII code whenever a key is
depressed.
• DAV (Data Available) is activated on a key
press, strobing the ASCII-coded key code into
Port A.

8086

INT
R
PC 3
IBF (input buffer
PC 5 full)
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 Mode 2

Uni directional port

with or without
handshaking

Port A C7-C3 Port B

Hand shaking
Bidirectional 8 signals
bit I/O port

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 82C55: Mode 2 Bi-directional Operation

• In this mode data is transmitted in both

directions between the 8255 & the
peripheral devices on port A.
• “Handshaking” signals are provided to
maintain proper bus flow discipline in a
similar manner to MODE 1.
• Port B can be only configured for mode 0
or 1.

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Interfacing of ADC with 8086

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8086 Microprocessor
Memory

Processor Memory
 Registers inside a microcomputer
 Store data and results temporarily
 No speed disparity
 Cost 

Primary or Main Memory

 Storage area which can be directly
Memory accessed by microprocessor
 Store programs and data prior to
Store
execution
Programs
 Should not have speed disparity with
and Data
processor  Semi Conductor
memories using CMOS technology
 ROM, EPROM, Static RAM, DRAM

Secondary Memory
 Storage media comprising of slow
devices such as magnetic tapes and
disks
 Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 54
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8086 Microprocessor
Memory organization in 8086

Memory IC’s : Byte oriented

8086 : 16-bit

Word : Stored by two consecutive

memory locations; for LSB and
MSB

Address of word : Address of LSB

Bank 0 : A0 = 0  Even
addressed memory bank

Bank 1 : = 0  Odd
addressed memory bank

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8086 Microprocessor
Memory organization in 8086

Operation A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D 0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation

byte from odd bank is
transferred
1 1 D7 – D0 in first operation
byte from odd bank is 57
transferred
8086 Microprocessor
Memory organization in 8086

Available memory space = EPROM + RAM

Allot equal address space in odd and even

bank for both EPROM and RAM

Can be implemented in two IC’s (one for

even and other for odd) or in multiple IC’s

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8086 Microprocessor
Interfacing SRAM and EPROM

Memory interface  Read from and write in

to a set of semiconductor memory IC chip

EPROM  Read operations

RAM  Read and Write

In order to perform read/ write operations,

Memory access time  read / write time of

the processor

Chip Select (CS) signal has to be generated

Control signals for read / write operations

Allot address for each memory location

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8086 Microprocessor
Interfacing SRAM and EPROM

Typical Semiconductor IC Chip

No of Memory capacity Range of

Address address in
pins In Decimal In kilo In hexa hexa

20 220= 10,48,576 1024 k = 1M 100000 00000

to
FFFFF

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8086 Microprocessor
Interfacing SRAM and EPROM

Memory map of 8086

EPROM’s are mapped at FFFFFH

 Facilitate automatic execution of monitor programs
and creation of interrupt vector table

RAM are mapped at the beginning; 00000H is allotted to RAM

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 MEMORY INTERFACE USING RAMS, EPROMS AND EEPROMS

The general procedure of static memory interfacing with 8086 is briefly

described as follows:
1. Arrange the available memory chips so as to obtain 16-bit data bus
width. The upper 8-bit bank is called ‘odd address memory bank’ and
the lower 8-bit bank is called ‘even address memory bank’.
2. Connect available memory address lines of memory chips with those
of the microprocessor and also connect the memory RD and WR
inputs to the corresponding processor control signals. Connect the
16-bit data bus of the memory bank with that of the microprocessor
8086.
3. The remaining address lines of the microprocessor, BHE and A0 are
used for decoding the required chip select signals for the odd and
even memory banks. CS of memory is derived from the O/P of the
decoding circuit. The address map of the system should be
continuous as far as possible, i.e. there should be no windows in the
map. A memory location should have a single address corresponding
to it, i.e. absolute decoding should be preferred, and minimum
hardware should be used for decoding. Mostly, linear decoding are
used to minimise the required hardware.
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Interrupts of 8086

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Interrupt Vector Table (IVT) of 8086 69
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 8259

• 8259 is Programmable Interrupt Controller

(PIC)
• It is a tool for managing the interrupt
requests.
• 8259 is a very flexible peripheral
controller chip:
– PIC can deal with up to 64 interrupt inputs
– interrupts can be masked
– various priority schemes can also
programmed.
 Pin description
• 8-bit bi-directional data bus, one address line is
needed,
PIC has two control registers to be programmed, you can think of them
as two output ports or two memory location.
• The direction of data flow is controlled by RD and WR.
• CS is as usual connected to the output of the address
decoder.
• Interrupt requests are output on INT which is
connected to the INTR of the processor. Int.
acknowledgment is received by INTA.
• IR0-IR7 allow 8 separate interrupt requests to be
inputted to the PIC.
• sp/en=1 for master , sp/en=0 for slave.
• CAS0-3 inputs/outputs are used when more than one
PIC to cascaded.
FIGURE 9-4 Block diagram and pin definitions for the 8259A Programmable Interrupt Controller
(PIC). (Courtesy of Intel Corporation.)

John Uffenbeck Copyright ©2002 by Pearson Education,

The 80x86 Family: Design, Inc.
Programming, and Interfacing, 3e Upper Saddle River, New Jersey 07458
Example of two cascaded PICs
 MS-DOS and BIOS Programming

Software interrupts will call interrupt service

routines (ISRs) either in DOS or BIOS
• INT 21h MS-DOS Services
• INT 10h Video Services
• INT 11H: DETERMINE THE TYPE OF
EQUIPMENT INSTALLED
• INT 14H: CONTROL THE SERIAL
COMMUNICATION PORT
• INT 16h Keyboard Services
• INT 17h Printer Services
• INT 1Ah Time of Day
• INT 1Ch User Timer Interrupt
INT 21H- MS-DOS INTERRUPTS
•FUNCTION CALL 01: READ THE KEY BOARD
• INPUT PARAMETER AH = 01
• READ A CHARACTER FROM KEYBOARD. ECHO IT ON
CRO SCREEN AND
RETURN THE ASCII CODE OF THE KEY PRESSEDIN AL
• OUTPUT PARAMETER: AL = ASCII CODE OF CHARACTER

•FUNCTION CALL 02H: DISPLAY ON CRT SCREEN

• INPUT PARAMETER: AH = 02
• DL = ASCII CHARACTER TO BE DISPLAYED ON CRT
SCREEN

•FUNCTION CALL 03: READ CHARACTER FROM COM1

• INPUT PARAMETER: AH = 03H
• FUNCTION: READS DATA FROM COM PORT
• OUTPUT PARAMETER: AL = ASCII CODE OF CHARACTER

•FUNCTION CALL 04: WRITE CHARACTER TO COM1

• INPUT PARAMETER: AH = 04H
 INT 21H- MS-DOS INTERRUPTS
•FUNCTION CALL 05: WRITE TO LPT1
• INPUT PARAMETER: Al = 05H
• DL = ASCII CODE OF CHARACTER TO BE PRINTTED
• FUNCTION: PRINT THE CHARACTER AVAILABLE IN DL ON
PRINTER ATTACHED TO LPT1

•FUNCTION CALL 09: DISPLAY A CHARACTER STRING

• INPUT PARAMETER: AH = 09,DS:DX= ADDRESS OF
CHARACTER STRING
• FUNCTION: DISPLAYS THE CHARACTERS AVAILABLE IN THE
STRING TO CRT TILL A $
•FUNCTION CALL 0AH: BUFFERED KEY BOARD INPUT
• INPUT PARAMETER: AH = 0AH
• DS:DX = ADDRESS OF KEYBOARD INPUT BUFFER
• FUNCTION: THE ASCII CODES OF THE CHARACTERS
RECEIVED FROM KEYBOARD ARE STORED IN KEYBOARD
BUFFER FROM 3RD BYTE. 1ST BYTE OF BUFFER = SIZE OF
BUFFER UPTO 255.
IT RECEIVES THE CHARACTERS TILL SPECIFIED NO.OF
 BIOS INTERRUPTS

0H: VIDEO SERVICE INPERRUPT

NTROLS THE VEDIO DISPLAY
UNCTION CALL 00: SELECT VEDIO MODE
PARAMETER: AL = MODE NUMBER
AH = 00H
TION: IT CHANGES THE DISPLAY MODE AND CLEARS THE SCREEN
00 40 X 25 BLACK AND WHITE
04 320 X 200 COLOR
10H 640 X 350 X 16 COLOR

UNCTION CALL 03: READ CURSOR POSITION

PARAMETER: AH = 03
PAGE NUMBER
TION: READS CURSOR POSITION ON SCREEN
UT PARAMETERS: CH = STARTING LINE
CL = ENDING LINE
DH = CURRENT ROW
DL = CURRENT COLUMN
 BIOS INTERRUPTS

( C) FUNCTION CALL 0E: WRITE CHARACTER ON CRT SCREEN AND

ADVANCE CURSOR
INPUT PARAMETER: AH = 0EH
AL = ASCII CODE OF THE CHARACTER
BH = PAGE(TEXT MODE)
BL = COLOR(GRAPHICS)
FUNCTION: DISPLAY CHARACTER AVAILABLE IN AL ON SCREEN

INT 11H: DETERMINE THE TYPE OF EQUIPMENT INSTALLED.

REGISTER AX SHOULD CONTAIN FFFFH AND INSTRUCTION INT
11H TO BE EXECUTED. ON RETURN, REGISTER AX WILL INDICATE
THE EQUIPMENTS ATTACHED TO COMPUTER

INT 14H: CONTROL THE SERIAL COMMUNICATION PORT ATTACHED

TO THE COMPUETR.
AH SHOULD CONTAIN THE FUNCTION CALL
(a) FUNCTION CALL 00:INITIALIZE THE COM PORT
(b) FUNCTION CALL 01: SEND A CHARACTER
(c) FUNCTION CALL 02:RECEIVE A CHARACTER

INT 16H: KEYBOARD INTERRUPT

AH SHOULD CONTAIN THE FUNCTION CALL
(d) FUNCTION CALL 00: READ KEYBOARD CHARACTER, IT WILL RETURN
ASCII CODE OF THE CHARACTER
 ALP to display given string (using BIOS)

• Data segment
• Message db 0AH,0DH, ‘ MICROPROCESSOR’ 0AH,0DH, “$”
• Date ends

• Code segment
• Assume DS: Data, CS: Code
• Start:
– Mov AX, Data
– MOV DS,AX
– MOV DX, offset message
– MOV AH, 09H
– INT 21H
– Int 3H
• Code ends
• End start