SASURIE COLLEGE OF ENGINEERING, VIJAYAMANGALAM.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

Academic Year 2011 2012 Odd Semester
INTERNAL TEST I ANSWER KEY
PART A
1. Categories of 8085 instructions.
Data transfer group MOV, MVI, LXI.
Arithmetic group ADD, SUB, INR.
Logical group ANA, XRA, CMP.
Branch group JMP, JNZ, CALL.
Stack I/O and Machine control group PUSH, POP, IN, HLT.
2. Flags.
The flags are used to reflect the data conditions in the accumulator. The 8085 flags are
S-Sign flag, Z-Zero flag, AC-Auxiliary carry flag, P-Parity flag, CY- Carry flag.
D7

D6

S
Z
3. Priority interrupts of 8085.

D5

D4

D3

D2

D1

D0

AC

2
P

CY

The 8085 microprocessor has five interrupt inputs. They are TRAP, RST 7.5, RST 6.5,
RST 5.5, and INTR. These interrupts have a fixed priority of interrupt service.
If two or more interrupts go high at the same time, the 8085 will service them on priority
basis. The TRAP has the highest priority followed by RST 7.5, RST 6.5, RST 5.5. The priority
of interrupts in 8085 is shown in the table.
Interrupts

Priority

TRAP

RST 7.5

RST6.5

RST 5.5

INTR

4. Function of IO/M signal in the 8085?

It is a status signal. It is used to differentiate between memory locations and I/O
operations. When this signal is low (IO/M = 0) it denotes the memory related operations. When
this signal is high (IO/M = 1) it denotes an I/O operation.
5. Instruction cycle:
Instruction cycle is defined as the time required for completing the execution of an
instruction.
Machine cycle: Machine cycle is defined as the time required for completing one operation of
accessing memory, I/O or acknowledging an external request.
T-state: T- cycle is defined as one subdivision of the operation performed in one clock period.
6. Comparison of Memory mapped I/O and I/O mapped I/O.
S.No
1.
2.
3.

Memory mapped I/O

In this device address is 16-bit. Thus
A0-A15 lines are used to generate the
device address.
MEMR and MEMW control signals
are used to control read and write I/O
operations
Instructions available are LDA, STA,
MOV R, M, ADD M, etc

I/O mapped I/O

In this device address is 8-bit. Thus A0A7 or A8-A15 lines are used to generate
the device address.
IOR and IOW control signals are used to
control read and write I/O operations
Instructions available are IN and OUT.

4.

Data transfer is between any register Data transfer is between accumulator

and I/O device.
and I/O device.

5.

Decoding 16-bit address may require Decoding 8-bit address will require less
more hardware
hardware

7. Applications of microprocessor-based system.

It is used:
For

measurements,

display

and

control

temperature, pressure, etc.

For traffic control and industrial tool control.
For speed control of machines.

of

current,

voltage,

8. Different instruction formats with examples

The instruction set is grouped into the following formats
Type

Example

One byte

MOV C,A

Two byte

MVI A,39H

Three byte

JMP 2345H

9. 8085 machine cycles:

The 8085 have seven machine cycles. They are
Opcode fetch
Memory read
Memory write
I/O read
I/O write
Interrupt acknowledge
Bus idle
10. Drawback in machine language and assembly language programs?
The machine language and assembly language programs are machine dependent. The
programs developed using these languages for a particular machine cannot be directly run on
another machine.

PART B
11. Assembly Language Program:
ASCENDING

Repeat
Loop

Skip

LXI H, 4200
MOV C,M
DCR C
MOV D,C
LXI H, 4201
MOV A, M
INX H
CMP M
JC Skip
MOV B,M
MOV M,A
DCX H
MOV M,B
INX H
DCR D
JNZ Loop
DCR C
JNZ Repeat
HLT

16 BIT
ADDITION
LXI H, 4500
MOV A, M
INX H
MOV B, M
INX H
MOV C, M
INX H
MOV D, M
ADD C
MOV L, A
MOV A, B
ADD D
MOV H, A
SHLD 4150
HLT

12. 8255 PPI:

Data Bus Buffer:
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data
bus. Data is transmitted or received by the buffer upon execution of input or output instructions
by the CPU.
Read/Write and Control Logic:

The
function of this block is to manage all of the internal and external transfers of both Data and
Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn,
issues commands to both of the Control Groups.
Chip Select: A "low" on this input pin enables the communcation between the 8255 and the
CPU.
Read: A "low" on this input pin enables 8255 to send the data or status information to the CPU
on the data bus. In essence, it allows the CPU to "read from" the 8255.
Write: A "low" on this input pin enables the CPU to write data or control words into the 8255.
A0 and A1: Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and
WR inputs, control the selection of one of the three ports or the control word register. They are
normally connected to the least significant bits of the address bus (A0 and A1).
A1
0
0
1
1

A0
0
1
0
1

SELECTION
PORT A
PORT B
PORT C
CONTROL

RESET: Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B,
C) are set to the input mode.
Group A and Group B Controls:
The functional configuration of each port is programmed by the systems software. In
essence, the CPU "outputs" a control word to the 8255. The control word contains information
such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255.
Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write
Control logic, receives "control words" from the internal data bus and issues the proper
commands to its associated ports.
Ports A, B, and C:
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety
of functional characteristics by the system software but each has its own special features or
"personality" to further enhance the power and flexibility of the 8255.
Port A: One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and
"pull-down" bus-hold devices are present on Port A.
Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).
This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a
4-bit latch and it can be used for the control signal output and status signal inputs in conjunction
with ports A and B.
13. Instructions:
i.

STC
Set Carry.
The Carry flag is set to 1.
No other flags are affected.
Example: STC

ii.

EI
The interrupt enable flip-flop is set and all interrupts are enabled.
No flags are affected.

 After a system reset or the acknowledgement of an interrupt, the interrupt

enable flipflop is reset, thus disabling the interrupts.
This instruction is necessary to reenable the interrupts (except TRAP).
Example: EI
iii.

STA address
The contents of the accumulator are copied into the memory location specified
by the operand.
This is a 3-byte instruction, the second byte specifies the low-order address and
the third byte specifies the high-order address.
STA 16-bit address
Example: STA 4350H

14. Addressing modes in 8085:

The method of specifying the data to be operated by the instruction is called Addressing.

The 8085 has the following 5 different types of addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing

1. Immediate Addressing:

In immediate addressing mode, the data is specified in the instruction itself. The data will
be a part of the program instruction.

EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP,
2700H.

2. Direct Addressing:

In direct addressing mode, the address of the data is specified in the instruction. The data
will be in memory. In this addressing mode, the program instructions and data can be
stored in different memory.

EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator;
SHLD 3000H

3. Register Addressing:

In register addressing mode, the instruction specifies the name of the register in which the
data is available.

EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.

4. Register Indirect Addressing:

In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. Here the data will be in memory and the
address will be in the register pair.

EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX
B.

5. Implied Addressing:

In implied addressing mode, the instruction itself specifies the data to be operated.

EX. CMA - Complement the content of accumulator; RAL

15. Instructions:
i.

LXI Rp,data
The instruction loads 16-bit data in the register pair designated in the operand.
LXI Reg. pair, 16-bit data
Example: LXI H, 2034H

ii.

DAD Rp
The 16-bit contents of the specified register pair are added to the contents of the
HL register and the sum is stored in the HL register.
The contents of the source register pair are not altered. If the result is larger than
16 bits, the CY flag is set.
No other flags are affected.
DAD Reg. pair
Example: DAD H

iii.

POP PSW
The contents of the memory location pointed out by the stack pointer register
are copied to the low-order register (C, E, L, status flags) of the operand.
The stack pointer is incremented by 1 and the contents of that memory location
are copied to the high-order register (B, D, H, A) of the operand.
The stack pointer register is again incremented by 1.

POP Reg. pair

Example: POP H