SystemVerilog: Functions and
Tasks
Defined by: Sumedha IT | Format:
VLSIPoint, ChipVerify, TestBench.in
Functions vs Tasks – Overview
• • Functions and Tasks encapsulate reusable
logic.
• • Functions are used for calculations (no time
delay).
• • Tasks are used for operations involving time
control.
• • Both can be automatic or static (default:
static).
Differences Between Function and
Task
• • Functions return a value; Tasks do not.
• • Functions cannot contain time-consuming
constructs.
• • Tasks can include delay (#), event (@), or
wait.
• • Functions are called in expressions; Tasks are
not.
• • Tasks can have input, output, inout;
Functions have only input.
Function – Syntax & Example
• function [automatic] return_type name (input
args);
• // statements
• endfunction
• Example:
• function int get_parity(input bit [7:0] data);
• get_parity = ^data;
• endfunction
Task – Syntax & Example
• task [automatic] name (input/output/inout
args);
• // statements with delays
• endtask
• Example:
• task send_data(input bit [7:0] data);
• @(posedge clk);
• bus <= data;