4-1 DIGITAL-TO-DIGITAL CONVERSION

In this section, we see how we can represent digital

data by using digital signals. The conversion involves
three techniques: line coding, block coding, and
scrambling. Line coding is always needed; block
coding and scrambling may or may not be needed.

Topics discussed in this section:

 Line Coding
 Line Coding Schemes
 Block Coding
 Scrambling
4.1
 Line Coding
 Converting a string of 1’s and
0’s (digital data) into a
sequence of signals that
denote the 1’s and 0’s.
 For example a high voltage
level (+V) could represent a
“1” and a low voltage level (0
or -V) could represent a “0”.

4.2
 Figure 4.1 Line coding and decoding

4.3
 Mapping Data symbols
onto Signal levels
 A data symbol (or element) can
consist of a number of data bits:
 1 , 0 or
 11, 10, 01, ……
 A data symbol can be coded into a
single signal element or multiple
signal elements
 1 -> +V, 0 -> -V
 1 -> +V and -V, 0 -> -V and +V
 The ratio ‘r’ is the number of data
elements carried by a signal element.
4.4
 Figure 4.4 Line coding schemes

4.5
 Unipolar
 All signal levels are on one side of
the time axis - either above or below
 NRZ - Non Return to Zero scheme is an
example of this code. The signal
level does not return to zero during
a symbol transmission.
 Scheme is prone to baseline wandering
and DC components. It has no
synchronization or any error
detection. It is simple but costly in
power consumption.

4.6
 Figure 4.5 Unipolar NRZ scheme

4.7
 Polar - NRZ
 The voltages are on both sides of the
time axis.
 Polar NRZ scheme can be implemented
with two voltages. E.g. +V for 1 and
-V for 0.
 There are two versions:
 NZR - Level (NRZ-L) - positive voltage
for one symbol and negative for the other
 NRZ - Inversion (NRZ-I) - the change or
lack of change in polarity determines the
value of a symbol. E.g. a “1” symbol
inverts the polarity a “0” does not.
4.8
 Figure 4.6 Polar NRZ-L and NRZ-I schemes

4.9
 Note

In NRZ-L the level of the voltage

determines the value of the bit.
In NRZ-I the inversion
or the lack of inversion
determines the value of the bit.

4.10
 Note

NRZ-L and NRZ-I both have an average

signal rate of N/2 Bd.

4.11
 Note

NRZ-L and NRZ-I both have a DC

component problem and baseline
wandering, it is worse for NRZ-L. Both
have no self synchronization &no error
detection. Both are relatively simple to
implement.

4.12
 Example 4.4

A system is using NRZ-I to transfer 1-Mbps data. What

are the average signal rate and minimum bandwidth?

Solution
The average signal rate is S= c x N x R
= 1/2 x N x 1 = 500 kbaud. The minimum
bandwidth for this average baud rate is
Bmin = S = 500 kHz.

Note c = 1/2 for the avg. case as worst

case is 1 and best case is 0
4.13
 Polar - RZ
 The Return to Zero (RZ) scheme uses
three voltage values. +, 0, -.
 Each symbol has a transition in the
middle. Either from high to zero or
from low to zero.
 This scheme has more signal transitions
(two per symbol) and therefore requires
a wider bandwidth.
 No DC components or baseline wandering.
 Self synchronization - transition
indicates symbol value.
 More complex as it uses three voltage
level. It has no error detection
capability.
4.14
 Figure 4.7 Polar RZ scheme

4.15
 Polar - Biphase:
Manchester and
Differential

Manchester
Manchester coding consists
the NRZ-L and RZ schemes.
of combining

 Every symbol has a level transition in the

middle: from high to low or low to high.
Uses only two voltage levels.
 Differential Manchester coding consists
of combining the NRZ-I and RZ schemes.
 Every symbol has a level transition in the
middle. But the level at the beginning of
the symbol is determined by the symbol
value. One symbol causes a level change the
other does not.

4.16
 Figure 4.8 Polar biphase: Manchester and differential Manchester schemes

4.17
 Note

In Manchester and differential

Manchester encoding, the transition
at the middle of the bit is used for
synchronization.

4.18
 Note

The minimum bandwidth of Manchester

and differential Manchester is 2 times
that of NRZ. The is no DC component
and no baseline wandering. None of
these codes has error detection.

4.19
 Bipolar - AMI and
Pseudoternary
Code uses 3 voltage levels: - +, 0,
-, to represent the symbols (note not
transitions to zero as in RZ).
 Voltage level for one symbol is at
“0” and the other alternates between
+ & -.
 Bipolar Alternate Mark Inversion
(AMI) - the “0” symbol is represented
by zero voltage and the “1” symbol
alternates between +V and -V.
 Pseudoternary is the reverse of AMI.

4.20
 Figure 4.9 Bipolar schemes: AMI and pseudoternary

4.21
 Bipolar C/Cs
 It is a better alternative to
NRZ.
 Has no DC component or baseline
wandering.
 Has no self synchronization
because long runs of “0”s results
in no signal transitions.
 No error detection.

4.22
 Multilevel Schemes
 In these schemes we increase the
number of data bits per symbol
thereby increasing the bit rate.
 Since we are dealing with binary data
we only have 2 types of data element
a 1 or a 0.
 We can combine the 2 data elements
into a pattern of “m” elements to
create “2m” symbols.
 If we have L signal levels, we can
use “n” signal elements to create Ln
signal elements.
4.23
 Code C/Cs
 Now we have 2m symbols and Ln signals.
 If 2m > Ln then we cannot represent the
data elements, we don’t have enough
signals.
 If 2m = Ln then we have an exact mapping
of one symbol on one signal.
 If 2m < Ln then we have more signals than
symbols and we can choose the signals
that are more distinct to represent the
symbols and therefore have better noise
immunity and error detection as some
signals are not valid.

4.24
 Note

In mBnL schemes, a pattern of m data

elements is encoded as a pattern of n
signal elements in which 2m ≤ Ln.

4.25
 Representing
Multilevel Codes
 We use the notation mBnL, where
m is the length of the binary
pattern, B represents binary
data, n represents the length of
the signal pattern and L the
number of levels.
 L = B binary, L = T for 3
ternary, L = Q for 4 quaternary.

4.26
 Figure 4.10 Multilevel: 2B1Q scheme

4.27
 Redundancy
 In the 2B1Q scheme we have no redundancy
and we see that a DC component is
present.
 If we use a code with redundancy we can
decide to use only “0” or “+” weighted
codes (more +’s than -’s in the signal
element) and invert any code that would
create a DC component. E.g. ‘+00++-’ ->
‘-00--+’
 Receiver will know when it receives a “-”
weighted code that it should invert it as
it doesn’t represent any valid symbol.

4.28
 Figure 4.11 Multilevel: 8B6T scheme

4.29
 Multilevel using
multiple
In some cases, channels
we split the signal
transmission up and distribute it over
several links.
 The separate segments are transmitted
simultaneously. This reduces the signalling
rate per link -> lower bandwidth.
 This requires all bits for a code to be
stored.
 xD: means that we use ‘x’ links
 YYYz: We use ‘z’ levels of modulation where
YYY represents the type of modulation (e.g.
pulse ampl. mod. PAM).
 Codes are represented as: xD-YYYz

4.30
 Figure 4.12 Multilevel: 4D-PAM5 scheme

4.31
 Multitransition Coding
 Because of synchronization requirements we
force transitions. This can result in very
high bandwidth requirements -> more
transitions than are bits (e.g. mid bit
transition with inversion).
 Codes can be created that are differential
at the bit level forcing transitions at bit
boundaries. This results in a bandwidth
requirement that is equivalent to the bit
rate.
 In some instances, the bandwidth requirement
may even be lower, due to repetitive
patterns resulting in a periodic signal.

4.32
 Figure 4.13 Multitransition: MLT-3 scheme

4.33
 MLT-3
 Signal rate is same as NRZ-I
 But because of the resulting
bit pattern, we have a
periodic signal for worst
case bit pattern: 1111
 This can be approximated as
an analog signal a frequency
1/4 the bit rate!
4.34
 Table 4.1 Summary of line coding schemes

4.35
 Block Coding
 For a code to be capable of error
detection, we need to add redundancy,
i.e., extra bits to the data bits.
 Synchronization also requires redundancy -
transitions are important in the signal
flow and must occur frequently.
 Block coding is done in three steps:
division, substitution and combination.
 It is distinguished from multilevel coding
by use of the slash - xB/yB.
 The resulting bit stream prevents certain
bit combinations that when used with line
encoding would result in DC components or
poor sync. quality.

4.36
 Note

Block coding is normally referred to as

mB/nB coding;
it replaces each m-bit group with an
n-bit group.

4.37
 Figure 4.14 Block coding concept

4.38
 Figure 4.15 Using block coding 4B/5B with NRZ-I line coding scheme

4.39
Table 4.2 4B/5B mapping codes

4.40
 Figure 4.16 Substitution in 4B/5B block coding

4.41
 Redundancy
 A 4 bit data word can have 24
combinations.
 A 5 bit word can have 25=32
combinations.
 We therefore have 32 - 26 = 16
extra words.
 Some of the extra words are
used for control/signalling
purposes.
4.42
 Example 4.5

We need to send data at a 1-Mbps rate. What is the

minimum required bandwidth, using a combination of
4B/5B and NRZ-I or Manchester coding?

Solution
First 4B/5B block coding increases the
bit rate to 1.25 Mbps. The minimum
bandwidth using NRZ-I is N/2 or 625
kHz. The Manchester scheme needs a
minimum bandwidth of 1.25 MHz. The
first choice needs a lower bandwidth,
but has a DC component problem; the
second choice needs a higher bandwidth,
4.43
 Figure 4.17 8B/10B block encoding

4.44
 More bits - better error
detection
 The 8B10B block code adds
more redundant bits and can
thereby choose code words
that would prevent a long run
of a voltage level that would
cause DC components.

4.45
 Scrambling
 The best code is one that does not
increase the bandwidth for
synchronization and has no DC components.
 Scrambling is a technique used to create
a sequence of bits that has the required
c/c’s for transmission - self clocking,
no low frequencies, no wide bandwidth.
 It is implemented at the same time as
encoding, the bit stream is created on
the fly.
 It replaces ‘unfriendly’ runs of bits
with a violation code that is easy to
recognize and removes the unfriendly c/c.

4.46
 Figure 4.18 AMI used with scrambling

4.47
 For example: B8ZS substitutes eight
consecutive zeros with 000VB0VB.
The V stands for violation, it violates the
line encoding rule
B stands for bipolar, it implements the
bipolar line encoding rule

4.48
 Figure 4.19 Two cases of B8ZS scrambling technique

4.49
 HDB3 substitutes four consecutive
zeros with 000V or B00V depending
on the number of nonzero pulses after
the last substitution.
If # of non zero pulses is even the
substitution is B00V to make total # of
non zero pulse even.
If # of non zero pulses is odd the
substitution is 000V to make total # of
non zero pulses even.
4.50
 Figure 4.20 Different situations in HDB3 scrambling technique

4.51