Computer Aided Design for VLSI
(CAD for VLSI), MAVLD601
Introduction
Harish Kittur,
Diagrams from Sherwani, Kia Bazargan, Andrew
Kahng
Copyrights acknowledged
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Course Evaluation
1. Quiz-1- 10 marks
2. Quiz-2- 10 marks
3. Quiz-3- 10 marks
4. CAT-1 -15 marks (QP of 50 marks)
5. Cat-2 – 15 marks (QP of 50 marks)
6. FAT – 40 marks (QP of 100 marks)
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Text Books
• “VLSI Physical Design”, Kahng, Lienig, Markov
and Hu (http://vlsicad.eecs.umich.edu/KLMH/)
• “Algorithms for VLSI Physical Design
Automation”, Naveed Sherwani
• “An Introduction to VLSI Physical Design”,
Sarrafzadeh and Wong
• “VLSI Physical Design Automation”, Sadiq Sait
and Habib Youssef
• “Handbook of Algorithms for Physical Design
Automation”, Alpert. Mehta and Sapatnekar
• Algorithms for VLSI Design Automation, Sabih
Gerez
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• This lecture refer chapter 1 of Kahng
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VLSI Design Flow
High-level
High-level Functional
Functional
Specifications
Specifications Description
Description Description
Description
Behavioral Structural
VHDL, C VHDL
Figs. [©Sherwani] I-5
VLSI Design Steps (cont.)
High-level
High-level Functional
Functional
Specifications
Specifications Description
Description Description
Description
Synthesis
Physical Technology
Design Mapping
Placed
Placed Logic
& Gate-level
Gate-level Logic
& Routed
Routed Design Description
Description
Design
Design Design
Packaging Fabri- X=(AB*CD)+
cation (A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
Figs. [©Sherwani] I-6
VLSI Design Flow
System Specification
Partitionin
Architectural Design g
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip
and Logic Design Planning
Circuit Design Placemen
t
Physical Design
Clock Tree
Synthesis
Physical Verification
DRC
LVS
and Signoff Signal
ERC
Routing
Fabrication
Timing
© 2011 Springer Verlag
Closure
Packaging and
Testing
Chip
7
VLSI Design Flow
• System Specifications
• Architectural Design
• Functional Design and Logic Design
• Circuit Design
• Physical Design
• Physical Verification and Signoff
• Fabrication
• Packaging and Testing
• Chip
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Physical Design
• Partitioning
• Floorplanning
• Power and Ground Routing
• Placement
• Clock Network Synthesis
• Global Routing
• Detailed Routing
• Timing Closure
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Design Styles - FPGA
Field-programmable gate array
(FPGA)
Logic Element
LB LB LB
Switchbox Connection
SB SB
LB LB LB
SB SB
© 2011 Springer Verlag
LB LB LB LB
10
Full Custom Design
Structural/RTL Description Component Design
Ctrl
Mem Reg Comp.
File Unit
Place & Route
comp
PLA
I/O
RAM
...
A/D
Floorplan [©Sherwani]
Layouts [© Prentice Hall]
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Full Custom Design Example
I/O Pad
Via
comp
Metal2
PLA I/O
Metal1
Macro
cell RAM
design
Glue logic
(standard
A/D cell design)
[©Sherwani]
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SEMI CUSTOM(standard cell based) Design
Structural/ HDL Programming
RTL Description
P_Inp: process (Reset, Clock)
Ctrl begin
if (Reset = '1') then
sum <= ( others => '0' );
input_nums_read <= '0';
Reg Comp. sum_ready <= '0';
Mem
File Unit
add82 : kadd8 port map (
a => add_i1, b => add_i2,
ci => carry, s => sum_o);
Mult_i1 <= sum_o(7 downto 0);
D C C B
A C C
D C D B
Cell library
C C C B
A B
C D
Floorplan [©Sherwani]
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Standard Cell Design Example
VDD Metal1 Cell GND
Metal2
D C C B
A C C
Cell library
A B
D C D B
C D
C C C B
Placement [©Sherwani]
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Fall 2006 EE 5301 - VLSI Design Automation I
• End
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