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1. Madhu-Krishnan-A-P.github.io Madhu-Krishnan-A-P.github.io Public

2. 4bitadder 4bitadder Public

   Verilog implementations of a 4-bit adder using behavioral, dataflow, and structural modeling styles, along with corresponding testbenches and block diagrams. This project demonstrates the design an…

   Verilog

3. mux mux Public

   This repository contains the Verilog design and testbench for a 8x1 Multiplexer. It uses three select lines to choose one of the eight inputs (A0–A7) and drive it to a single output based on the lo…

   Verilog

4. decoder decoder Public

   Implements a 3-to-8 line decoder using gate-level logic in Verilog. Converts a 3-bit binary input into a corresponding one-hot output across 8 lines (D0–D7). Features: Gate-level realization, Truth…

   Verilog

5. priority_encoder priority_encoder Public

   Verilog-based priority encoder that takes 8 input lines (D0–D7) and produces a 3-bit binary output indicating the highest priority active input. Features: Priority logic ensures higher-priority sig…

   Verilog

6. demux demux Public

   Implements a hierarchical 1-to-16 demultiplexer using a 1x2 and two 1x8 demux blocks in Verilog. Directs a single input signal to one of 16 outputs based on select lines. Features: Hierarchical Ver…

   Verilog 1