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Implements a 3-to-8 line decoder using gate-level logic in Verilog. Converts a 3-bit binary input into a corresponding one-hot output across 8 lines (D0–D7). Features: Gate-level realization, Truth table-based logic equations, Behavioral simulation with 8 input combinations

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Experiment 3.pdf		Experiment 3.pdf
decoder.v		decoder.v
testbench.v		testbench.v

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Implements a 3-to-8 line decoder using gate-level logic in Verilog. Converts a 3-bit binary input into a corresponding one-hot output across 8 lines (D0–D7). Features: Gate-level realization, Truth table-based logic equations, Behavioral simulation with 8 input combinations

decoder verilog vlsi testbench digital-design structural-design behavioural-simulation behavioural-design

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Verilog 100.0%