🎓 Computer and Communication Engineering Student | 💻 Electronics & Verification Enthusiast
📧 [email protected]
Bachelor's Degree in Computer and Communication Engineering
Cairo University (Expected 2027)
| Project | Duration | Technologies |
|---|---|---|
| UVM Verification on AXI4 | 08/2025 – 09/2025 | UVM, AXI4, QuestaSim, SystemVerilog |
| Verification on AXI4-Compliant Memory-Mapped Slave | 07/2025 – 08/2025 | AXI4, QuestaSim, Verilog |
| Project | Duration | Technologies |
|---|---|---|
| 32-Bit Single-Cycle RISC-V Processor | 07/2025 – 08/2025 | Verilog, Vivado, RISC-V |
| 2-Bit Binary Calculator | 03/2024 – 04/2024 | Verilog, Logic Design |
| Project | Duration | Technologies |
|---|---|---|
| Process Scheduler - Operating Systems | 04/2025 – 05/2025 | C, Linux, CPU Scheduling Algorithms |
| Restaurant Management System | 10/2024 – 12/2024 | .NET, C#, Windows Forms, MVC |
| Smartwatch Desk Clock (STM32 - Assembly) | 10/2024 – 12/2024 | ARM Assembly, STM32, I2C |
- 🎓 Pursuing my Bachelor's degree in Computer and Communication Engineering at Cairo University
- 📚 Learning Verilog, SystemVerilog, and advanced problem-solving techniques
- 🤝 Looking to collaborate on innovative electronics and software projects
- 🔍 Seeking opportunities in software engineering and digital design verification