New Features

• Added axi4lite_VersionRegister module and necessary files:
  • Entity axi4lite_GitVersionRegister
  • Package mem_GitVersionRegister
  • Synthesis pre-TCL script tools/git/preSynth_GitVersionRegister_Vivado.tcl
  • Entity xil_DNAPort
• Use sync_Bits for CDC in fifo_ic_got (code reruse and apply constraints automatically).
• Added empty/fill-level output for fifo_shift
• Add chunk-enable feature for comm_crc
• Support for fraction of one for type T_FRACTIONAL
• Entity list_expire
• Entity misc_Sequencer
• Entity misc_StrobeGenerator
• Entity misc_StrobeLimiter
• Entity misc_StrobeStretcher
• Entity mac_TX_Type_Prepender

Changes

• Check if Init value fits in downcounter; changed Init value's type a natural.
• Updated my_config template with GENERIC as device example

Bug Fixes

• bus_Arbiter: Throw failure when unimplemented lottery strategy is selected.
• Added missing VHDL sources to *.pro files for analyzing in simulators:
  • syntax check
  • instantiation check
• arith_scaler: Initialize arrays with '0' instead of '-' for better/easier simulation
• remote_terminal_control: Fix package name

Tests

• Run simulations additionally with GHDL mcode backend and NVC for better simulation coverage.
• axi4lite_Register (see #20)
  • updated register definition
  • added testcase for
    • checking initial values on all registers
    • simple read write

Clean-Up

• Remove all *.files, since they are outdated and the compile order is now defined by the *.pro files usable with OSVVM-Scripting.
• Remove old and unused VHDL files
  • sim/ obsoleted by OSVVM
  • Xilinx ISE related files

Related Issues and Pull-Requests

• #20
• #21

Co-authored-by: Adrian Weiland <[email protected]>
Co-authored-by: Asif Iqbal <[email protected]>
Co-authored-by: Max Kraft-Kugler <[email protected]>
Co-authored-by: Jonas Schreiner <[email protected]>
Co-authored-by: Patrick Lehmann <[email protected]>
Co-authored-by: Patrick Lehmann <[email protected]>
Co-authored-by: Patrick Lehmann <[email protected]>

New Features

• New AXI4Lite components
  • AXI4Lite_Register
  • AXI4Lite_FIFO
  • AXI4Lite_FIFO_CDC
  • AXI4Lite_Termination_*
• New AXI4 components
  • AXI4_to_AXI4Lite-Adapter
  • AXI4_FIFO
  • AXI4_FIFO_CDC
  • AXI4_Termination_*
• New AXI4Stream components
  • AXI4Stream_FIFO
  • AXI4Stream_FIFO_CDC
  • AXI4Stream_FIFO_tempgot
  • AXI4Stream_FIFO_tempput
  • AXI4Stream_Stage
  • AXI4Stream_Mux (Arbiter)
  • AXI4Stream_DeMux
• TerosHDL Project file
• Added ocram_sdp_optimized
• Added new RAM_TYPE for AMD/Xilinx UltraRAMs.

Changes

• Renamed fifo_glue to fifo_stage.

Tests

• AXI4Lite_Register

New Features

• arith_convert_bin2bcd with Register-Output as generic
• Add AXI packages for AXI4-Lite, AXI4-Stream and AXI4-MM

Changes

• Moved synchronizer modules from PoC.misc.sync to PoC.sync as a first-class citizen of PoC.

Bug Fixes

• arith_convert_bin2bcd fix for Reset
• bus_Arbiter.vhdl change pointer to 0 if one-hot code is broken

/cc @Asif71, @weilanad, @JonasSchreiner, @stefanunrein

The PoC-Library 1.3.0

Published from Verify PoC and Generate Documentation workflow triggered by @Paebbels on 2025-08-27 21:50:46 UTC.