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v2.0.0

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@Paebbels Paebbels released this 27 Aug 21:46
· 50 commits to master since this release
v2.0.0
0d27753
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Learn about vigilant mode.

New Features

  • New AXI4Lite components
    • AXI4Lite_Register
    • AXI4Lite_FIFO
    • AXI4Lite_FIFO_CDC
    • AXI4Lite_Termination_*
  • New AXI4 components
    • AXI4_to_AXI4Lite-Adapter
    • AXI4_FIFO
    • AXI4_FIFO_CDC
    • AXI4_Termination_*
  • New AXI4Stream components
    • AXI4Stream_FIFO
    • AXI4Stream_FIFO_CDC
    • AXI4Stream_FIFO_tempgot
    • AXI4Stream_FIFO_tempput
    • AXI4Stream_Stage
    • AXI4Stream_Mux (Arbiter)
    • AXI4Stream_DeMux
  • TerosHDL Project file
  • Added ocram_sdp_optimized
  • Added new RAM_TYPE for AMD/Xilinx UltraRAMs.

Changes

  • Renamed fifo_glue to fifo_stage.

Tests

  • AXI4Lite_Register
Assets 2
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