Introduction

This PR adds support for the Sdtrig Extension in CVA6, which primarily adds the Trigger Module. The core can now support four types of triggers i.e. icount, mcontrol6, etrigger and itrigger.

Implementation

The number of triggers supported by the core is parameterized and can be set at compile time.

The trigger module supports 2 types of action on trigger match i.e. breakpoint exception generation and debug mode

Modifications

The entire Trigger Module has been added under a SDTRIG bit for configuration. Additionally, all trigger types can be individually enabled and disabled using their own dedicated bits Icount, Mcontrol6, Etrigger, Itrigger.

The new trigger_module (trigger_module.sv) was added inside the CSR Register File (csr_regfile.sv). Additionally, the csr_regfile, commit stage and decode modules were updated to handle trigger fire logic.

Modifications Diagram

Documentation and Reference
The official The RISC-V Debug Specification Version 1.0.0 was followed to ensure alignment with ratification.

Verification

These changes have been tested with self-written tests to ensure proper functionality.