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Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

A cross-platform, reimplementation of Notepad++

ANSI Standard X3.64 Teletypewriter Command Session Library

Verilog build rules for bazel.

Netgear ReadyNAS Apps & Enhancements

A directory of Western Digital’s RISC-V SweRV Cores

Python and Octave/MATLAB explorations of algorithms from The Scientist and Engineer's Guide to Digital Signal Processing

Fully static, unprivileged, self-contained, containers as executable binaries.

Keystone Enclave (QEMU + HiFive Unleashed)

Tutorial for creating Python/Qt GUIs with fbs

Smaller, easier, more powerful, and more reliable than make. An implementation of djb's redo.

A Just-In-Time Compiler for Verilog from VMware Research

Generator Bootcamp Material: Learn Chisel the Right Way

binary releases of VS Code without MS branding/telemetry/licensing

MIPI DSI transmitter core for Xilinx FPGAs (work in progress)

Intel® Implicit SPMD Program Compiler

A Python toolbox for gaining geometric insights into high-dimensional data

Experiments with fixed function renderers and Chisel HDL

RISC-V XBitmanip Extension

A small, light weight, RISC CPU soft core

CMod-S6 SoC

Checked C is an extension to C that lets programmers write C code with bounds checking and improved type-safety. The goal is to let people easily make their existing C code type-safe and eliminate …

Non-Regex text search and replace for linux

A Bazel workspace for embedded systems

Protothreads (coroutines) in C99. Highly portable, but work best in low-end embedded systems.

DEPRECATED! -> Project moved to xPack Dev Tools ->

RISC-V Tools (ISA Simulator and Tests)

Spike, a RISC-V ISA Simulator