[ESI][Cosim][Verilator] Switch to FST and dump time #9031
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Contributor
teqdruid
commented
Sep 26, 2025
- Dump before changing the clock to make waveforms more standard.
- Switch to the more efficient FST waveform standard.
- Dump before changing the clock to make waveforms more standard. - Switch to the more efficient FST waveform standard.
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Pull Request Overview
This PR switches Verilator simulation from VCD to FST waveform format and adjusts trace dumping timing to improve waveform quality by dumping before clock changes rather than after.
- Replace VCD tracing with more efficient FST format in both Python compilation commands and C++ driver
- Reorder trace dumping to occur before clock changes for more standard waveform appearance
Reviewed Changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated no comments.
| File | Description |
|---|---|
| lib/Dialect/ESI/runtime/python/esiaccel/cosim/verilator.py | Updates Verilator compilation flags to use FST tracing instead of VCD |
| lib/Dialect/ESI/runtime/cosim_dpi_server/driver.cpp | Switches from VCD to FST includes/objects and moves trace dumping before clock transitions |
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