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[ESI][Cosim][Verilator] Switch to FST and dump time #9031

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Merged
merged 1 commit into from
Sep 26, 2025
Merged

[ESI][Cosim][Verilator] Switch to FST and dump time #9031

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12 changes: 6 additions & 6 deletions lib/Dialect/ESI/runtime/cosim_dpi_server/driver.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
#include CONCAT3(V,TOP_MODULE,.h)
// clang-format on

#include "verilated_vcd_c.h"
#include "verilated_fst_c.h"

#include "signal.h"
#include <iostream>
Expand Down Expand Up @@ -64,12 +64,12 @@ int main(int argc, char **argv) {
}

#ifdef TRACE
VerilatedVcdC *tfp = nullptr;
VerilatedFstC *tfp = nullptr;
#endif

if (waveformFile) {
#ifdef TRACE
tfp = new VerilatedVcdC();
tfp = new VerilatedFstC();
Verilated::traceEverOn(true);
dut.trace(tfp, 99); // Trace 99 levels of hierarchy
tfp->open(waveformFile);
Expand All @@ -95,11 +95,11 @@ int main(int argc, char **argv) {
// Run for a few cycles with reset held.
for (timeStamp = 0; timeStamp < 8 && !Verilated::gotFinish(); timeStamp++) {
dut.eval();
dut.clk = !dut.clk;
#ifdef TRACE
if (tfp)
tfp->dump(timeStamp);
#endif
dut.clk = !dut.clk;
}

// Take simulation out of reset.
Expand All @@ -108,12 +108,12 @@ int main(int argc, char **argv) {
// Run for the specified number of cycles out of reset.
for (; !Verilated::gotFinish() && !stopSimulation; timeStamp++) {
dut.eval();
dut.clk = !dut.clk;

#ifdef TRACE
if (tfp)
tfp->dump(timeStamp);
#endif
dut.clk = !dut.clk;

if (debugPeriod)
std::this_thread::sleep_for(std::chrono::milliseconds(debugPeriod));
}
Expand Down
3 changes: 2 additions & 1 deletion lib/Dialect/ESI/runtime/python/esiaccel/cosim/verilator.py
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Expand Up @@ -59,7 +59,8 @@ def compile_commands(self) -> List[List[str]]:
]
if self.debug:
cmd += [
"--trace", "--trace-params", "--trace-structs", "--trace-underscore"
"--trace-fst", "--trace-params", "--trace-structs",
"--trace-underscore"
]
cflags.append("-DTRACE")
if len(cflags) > 0:
Expand Down