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Merged
merged 10 commits into from
Jun 12, 2024
Merged

ARM64-SVE: gathervector #103159

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7ed74a3
ARM64-SVE: gathervector
a74nh Jun 3, 2024
c7d4fc4
HW_Flag_LowMaskedOperation
a74nh Jun 7, 2024
42dc35c
Remove HW_Flag_BaseTypeFromFirstArg and add asserts
a74nh Jun 7, 2024
f3c5eb4
Add invalid testing
a74nh Jun 10, 2024
60dc92f
Add conditional select testing
a74nh Jun 10, 2024
747aa17
Use LSL_N for 64bit address variants
a74nh Jun 11, 2024
1942bde
Remove 32bit address base variants from API
a74nh Jun 11, 2024
d41d2c2
re-add commented out 32bit APIs
a74nh Jun 12, 2024
8066bbb
Add comment on commented out methods
a74nh Jun 12, 2024
5a62f7e
Replace triple quotes with doubles
a74nh Jun 12, 2024
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6 changes: 6 additions & 0 deletions src/coreclr/jit/hwintrinsic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1607,6 +1607,12 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
assert(varTypeIsSIMD(op2->TypeGet()));
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
}
#elif defined(TARGET_ARM64)
if (intrinsic == NI_Sve_GatherVector)
{
assert(varTypeIsSIMD(op3->TypeGet()));
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
}
#endif
break;
}
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32 changes: 32 additions & 0 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -1845,6 +1845,38 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_Sve_GatherVector:
{
if (!varTypeIsSIMD(intrin.op2->gtType))
{
// GatherVector(Vector<T> mask, T* address, Vector<T2> indices)

var_types auxType = node->GetAuxiliaryType();
emitAttr auxSize = emitActualTypeSize(auxType);

if (auxSize == EA_8BYTE)
{
opt = varTypeIsUnsigned(auxType) ? INS_OPTS_SCALABLE_D_UXTW : INS_OPTS_SCALABLE_D_SXTW;
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From the summary docs, we are emitting LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3], which does not take xs field, so we do not have to embed UXTW or SXTW bit, right?

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From the summary docs, we are emitting LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3],

Correct

which does not take xs field, so we do not have to embed UXTW or SXTW bit, right?

Removing this, I get an asset (in emitarm64sve.cpp:6441). Looks like emit is expecting this field. I'll have to debug it a little more. There are a lot of different loads and I don't want to break any of them.

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so you are saying that although we pass the *XTW flag, we are not using it in for this instruction, although the code path flows through the emitarm64sve.cpp that you mentioned?

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Looks like it's using the flag to make a decision to decide on the correct encoding. Then doesn't use it later. Probably just needs a fix in emit.

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Probably just needs a fix in emit.

Did you fix it in this PR?

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Addressing modes now fixed. There are three variants for "address with vector of offsets":

Vector<64bit> GatherVector(Vector<64bit> mask, 64bit* address, Vector<64bit> indices)
-> LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]

Vector<32bit> GatherVector(Vector<32bit> mask, 32bit* address, Vector<signed32bit> indices)
-> LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, SXTW #2]

Vector<32bit> GatherVector(Vector<32bit> mask, 32bit* address, Vector<unsigned32bit> indices)
-> LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, UXTW #2]

Codegen now picks the correct ones

}
else
{
assert(auxSize == EA_4BYTE);
opt = varTypeIsUnsigned(auxType) ? INS_OPTS_SCALABLE_S_UXTW : INS_OPTS_SCALABLE_S_SXTW;
}

GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, opt,
INS_SCALABLE_OPTS_MOD_N);
}
else
{
// GatherVector(Vector<T> mask, Vector<T2> addresses)

GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op1Reg, op2Reg, 0, opt);
}

break;
}

case NI_Sve_ReverseElement:
// Use non-predicated version explicitly
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg, opt, INS_SCALABLE_OPTS_UNPREDICATED);
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1 change: 1 addition & 0 deletions src/coreclr/jit/hwintrinsiclistarm64sve.h
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Expand Up @@ -73,6 +73,7 @@ HARDWARE_INTRINSIC(Sve, FusedMultiplyAddNegated,
HARDWARE_INTRINSIC(Sve, FusedMultiplySubtract, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fmls, INS_sve_fmls}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_FmaIntrinsic|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sve, FusedMultiplySubtractBySelectedScalar, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fmls, INS_sve_fmls}, HW_Category_SIMDByIndexedElement, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_FmaIntrinsic|HW_Flag_LowVectorOperation)
HARDWARE_INTRINSIC(Sve, FusedMultiplySubtractNegated, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fnmls, INS_sve_fnmls}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_FmaIntrinsic|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sve, GatherVector, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ld1w, INS_sve_ld1w, INS_sve_ld1d, INS_sve_ld1d, INS_sve_ld1w, INS_sve_ld1d}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, GetActiveElementCount, -1, 2, true, {INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_ExplicitMaskedOperation)
HARDWARE_INTRINSIC(Sve, LeadingSignCount, -1, -1, false, {INS_sve_cls, INS_invalid, INS_sve_cls, INS_invalid, INS_sve_cls, INS_invalid, INS_sve_cls, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, LeadingZeroCount, -1, -1, false, {INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_sve_clz, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
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111 changes: 111 additions & 0 deletions ...ries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
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Expand Up @@ -1466,6 +1466,117 @@ internal Arm64() { }
public static unsafe Vector<float> FusedMultiplySubtractNegated(Vector<float> minuend, Vector<float> left, Vector<float> right) { throw new PlatformNotSupportedException(); }


/// Unextended load

/// <summary>
/// svfloat64_t svld1_gather_[s64]index[_f64](svbool_t pg, const float64_t *base, svint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<double> GatherVector(Vector<double> mask, double* address, Vector<long> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svfloat64_t svld1_gather[_u64base]_f64(svbool_t pg, svuint64_t bases)
/// LD1D Zresult.D, Pg/Z, [Zbases.D, #0]
/// </summary>
public static unsafe Vector<double> GatherVector(Vector<double> mask, Vector<ulong> addresses) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svfloat64_t svld1_gather_[u64]index[_f64](svbool_t pg, const float64_t *base, svuint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<double> GatherVector(Vector<double> mask, double* address, Vector<ulong> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint32_t svld1_gather_[s32]index[_s32](svbool_t pg, const int32_t *base, svint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, SXTW #2]
/// </summary>
public static unsafe Vector<int> GatherVector(Vector<int> mask, int* address, Vector<int> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint32_t svld1_gather[_u32base]_s32(svbool_t pg, svuint32_t bases)
/// LD1W Zresult.S, Pg/Z, [Zbases.S, #0]
/// </summary>
public static unsafe Vector<int> GatherVector(Vector<int> mask, Vector<uint> addresses) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint32_t svld1_gather_[u32]index[_s32](svbool_t pg, const int32_t *base, svuint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, UXTW #2]
/// </summary>
public static unsafe Vector<int> GatherVector(Vector<int> mask, int* address, Vector<uint> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint64_t svld1_gather_[s64]index[_s64](svbool_t pg, const int64_t *base, svint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<long> GatherVector(Vector<long> mask, long* address, Vector<long> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint64_t svld1_gather[_u64base]_s64(svbool_t pg, svuint64_t bases)
/// LD1D Zresult.D, Pg/Z, [Zbases.D, #0]
/// </summary>
public static unsafe Vector<long> GatherVector(Vector<long> mask, Vector<ulong> addresses) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint64_t svld1_gather_[u64]index[_s64](svbool_t pg, const int64_t *base, svuint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<long> GatherVector(Vector<long> mask, long* address, Vector<ulong> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svfloat32_t svld1_gather_[s32]index[_f32](svbool_t pg, const float32_t *base, svint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, SXTW #2]
/// </summary>
public static unsafe Vector<float> GatherVector(Vector<float> mask, float* address, Vector<int> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svfloat32_t svld1_gather[_u32base]_f32(svbool_t pg, svuint32_t bases)
/// LD1W Zresult.S, Pg/Z, [Zbases.S, #0]
/// </summary>
public static unsafe Vector<float> GatherVector(Vector<float> mask, Vector<uint> addresses) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svfloat32_t svld1_gather_[u32]index[_f32](svbool_t pg, const float32_t *base, svuint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, UXTW #2]
/// </summary>
public static unsafe Vector<float> GatherVector(Vector<float> mask, float* address, Vector<uint> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint32_t svld1_gather_[s32]index[_u32](svbool_t pg, const uint32_t *base, svint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, SXTW #2]
/// </summary>
public static unsafe Vector<uint> GatherVector(Vector<uint> mask, uint* address, Vector<int> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint32_t svld1_gather[_u32base]_u32(svbool_t pg, svuint32_t bases)
/// LD1W Zresult.S, Pg/Z, [Zbases.S, #0]
/// </summary>
public static unsafe Vector<uint> GatherVector(Vector<uint> mask, Vector<uint> addresses) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint32_t svld1_gather_[u32]index[_u32](svbool_t pg, const uint32_t *base, svuint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, UXTW #2]
/// </summary>
public static unsafe Vector<uint> GatherVector(Vector<uint> mask, uint* address, Vector<uint> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint64_t svld1_gather_[s64]index[_u64](svbool_t pg, const uint64_t *base, svint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<ulong> GatherVector(Vector<ulong> mask, ulong* address, Vector<long> indices) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint64_t svld1_gather[_u64base]_u64(svbool_t pg, svuint64_t bases)
/// LD1D Zresult.D, Pg/Z, [Zbases.D, #0]
/// </summary>
public static unsafe Vector<ulong> GatherVector(Vector<ulong> mask, Vector<ulong> addresses) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint64_t svld1_gather_[u64]index[_u64](svbool_t pg, const uint64_t *base, svuint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<ulong> GatherVector(Vector<ulong> mask, ulong* address, Vector<ulong> indices) { throw new PlatformNotSupportedException(); }


/// Count set predicate bits

/// <summary>
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111 changes: 111 additions & 0 deletions src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
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Expand Up @@ -1522,6 +1522,117 @@ internal Arm64() { }
public static unsafe Vector<float> FusedMultiplySubtractNegated(Vector<float> minuend, Vector<float> left, Vector<float> right) => FusedMultiplySubtractNegated(minuend, left, right);


/// Unextended load

/// <summary>
/// svfloat64_t svld1_gather_[s64]index[_f64](svbool_t pg, const float64_t *base, svint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<double> GatherVector(Vector<double> mask, double* address, Vector<long> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svfloat64_t svld1_gather[_u64base]_f64(svbool_t pg, svuint64_t bases)
/// LD1D Zresult.D, Pg/Z, [Zbases.D, #0]
/// </summary>
public static unsafe Vector<double> GatherVector(Vector<double> mask, Vector<ulong> addresses) => GatherVector(mask, addresses);

/// <summary>
/// svfloat64_t svld1_gather_[u64]index[_f64](svbool_t pg, const float64_t *base, svuint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<double> GatherVector(Vector<double> mask, double* address, Vector<ulong> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svint32_t svld1_gather_[s32]index[_s32](svbool_t pg, const int32_t *base, svint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, SXTW #2]
/// </summary>
public static unsafe Vector<int> GatherVector(Vector<int> mask, int* address, Vector<int> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svint32_t svld1_gather[_u32base]_s32(svbool_t pg, svuint32_t bases)
/// LD1W Zresult.S, Pg/Z, [Zbases.S, #0]
/// </summary>
public static unsafe Vector<int> GatherVector(Vector<int> mask, Vector<uint> addresses) => GatherVector(mask, addresses);

/// <summary>
/// svint32_t svld1_gather_[u32]index[_s32](svbool_t pg, const int32_t *base, svuint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, UXTW #2]
/// </summary>
public static unsafe Vector<int> GatherVector(Vector<int> mask, int* address, Vector<uint> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svint64_t svld1_gather_[s64]index[_s64](svbool_t pg, const int64_t *base, svint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<long> GatherVector(Vector<long> mask, long* address, Vector<long> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svint64_t svld1_gather[_u64base]_s64(svbool_t pg, svuint64_t bases)
/// LD1D Zresult.D, Pg/Z, [Zbases.D, #0]
/// </summary>
public static unsafe Vector<long> GatherVector(Vector<long> mask, Vector<ulong> addresses) => GatherVector(mask, addresses);

/// <summary>
/// svint64_t svld1_gather_[u64]index[_s64](svbool_t pg, const int64_t *base, svuint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<long> GatherVector(Vector<long> mask, long* address, Vector<ulong> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svfloat32_t svld1_gather_[s32]index[_f32](svbool_t pg, const float32_t *base, svint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, SXTW #2]
/// </summary>
public static unsafe Vector<float> GatherVector(Vector<float> mask, float* address, Vector<int> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svfloat32_t svld1_gather[_u32base]_f32(svbool_t pg, svuint32_t bases)
/// LD1W Zresult.S, Pg/Z, [Zbases.S, #0]
/// </summary>
public static unsafe Vector<float> GatherVector(Vector<float> mask, Vector<uint> addresses) => GatherVector(mask, addresses);

/// <summary>
/// svfloat32_t svld1_gather_[u32]index[_f32](svbool_t pg, const float32_t *base, svuint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, UXTW #2]
/// </summary>
public static unsafe Vector<float> GatherVector(Vector<float> mask, float* address, Vector<uint> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svuint32_t svld1_gather_[s32]index[_u32](svbool_t pg, const uint32_t *base, svint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, SXTW #2]
/// </summary>
public static unsafe Vector<uint> GatherVector(Vector<uint> mask, uint* address, Vector<int> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svuint32_t svld1_gather[_u32base]_u32(svbool_t pg, svuint32_t bases)
/// LD1W Zresult.S, Pg/Z, [Zbases.S, #0]
/// </summary>
public static unsafe Vector<uint> GatherVector(Vector<uint> mask, Vector<uint> addresses) => GatherVector(mask, addresses);

/// <summary>
/// svuint32_t svld1_gather_[u32]index[_u32](svbool_t pg, const uint32_t *base, svuint32_t indices)
/// LD1W Zresult.S, Pg/Z, [Xbase, Zindices.S, UXTW #2]
/// </summary>
public static unsafe Vector<uint> GatherVector(Vector<uint> mask, uint* address, Vector<uint> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svuint64_t svld1_gather_[s64]index[_u64](svbool_t pg, const uint64_t *base, svint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<ulong> GatherVector(Vector<ulong> mask, ulong* address, Vector<long> indices) => GatherVector(mask, address, indices);

/// <summary>
/// svuint64_t svld1_gather[_u64base]_u64(svbool_t pg, svuint64_t bases)
/// LD1D Zresult.D, Pg/Z, [Zbases.D, #0]
/// </summary>
public static unsafe Vector<ulong> GatherVector(Vector<ulong> mask, Vector<ulong> addresses) => GatherVector(mask, addresses);

/// <summary>
/// svuint64_t svld1_gather_[u64]index[_u64](svbool_t pg, const uint64_t *base, svuint64_t indices)
/// LD1D Zresult.D, Pg/Z, [Xbase, Zindices.D, LSL #3]
/// </summary>
public static unsafe Vector<ulong> GatherVector(Vector<ulong> mask, ulong* address, Vector<ulong> indices) => GatherVector(mask, address, indices);


/// Count set predicate bits

/// <summary>
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