[SelectionDAG] Split vector types for atomic load #120640

jofrn · 2024-12-19T21:28:36Z

Vector types that aren't widened are split
so that a single ATOMIC_LOAD is issued for the entire vector at once.
This change utilizes the load vectorization infrastructure in
SelectionDAG in order to group the vectors. This enables SelectionDAG
to translate vectors with type bfloat,half.

Stack:

⚠️ Part of a stack created by spr. Do not merge manually using the UI - doing so may have unexpected results.

llvmbot · 2024-12-19T21:29:12Z

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-x86

Author: None (jofrn)

Changes

load atomic <n x T> is not valid. This change splits
vector types of atomic load in SelectionDAG
so that it can translate vectors of >1 size with type bfloat,half.

Stack:

#120640 ⬅
#120598
#120387
#120386
#120385
#120384

⚠️ Part of a stack created by spr. Do not merge manually using the UI - doing so may have unexpected results.

Full diff: https://github.com/llvm/llvm-project/pull/120640.diff

3 Files Affected:

(modified) llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h (+1)
(modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+35)
(modified) llvm/test/CodeGen/X86/atomic-load-store.ll (+56)

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 3b3dddc44e3682..e0cd7319ac034b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -946,6 +946,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   void SplitVecRes_FPOp_MultiType(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_IS_FPCLASS(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
+  void SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_VP_LOAD(VPLoadSDNode *LD, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *SLD, SDValue &Lo,
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 7c4caa96244b8b..44adc3fdb4a5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1146,6 +1146,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
     SplitVecRes_STEP_VECTOR(N, Lo, Hi);
     break;
   case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
+  case ISD::ATOMIC_LOAD:
+    SplitVecRes_ATOMIC_LOAD(cast<AtomicSDNode>(N), Lo, Hi);
+    break;
   case ISD::LOAD:
     SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
     break;
@@ -2079,6 +2082,38 @@ void DAGTypeLegalizer::SplitVecRes_VP_SPLAT(SDNode *N, SDValue &Lo,
   Hi = DAG.getNode(N->getOpcode(), dl, HiVT, N->getOperand(0), MaskHi, EVLHi);
 }
 
+void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD, SDValue &Lo,
+                                               SDValue &Hi) {
+  EVT LoVT, HiVT;
+  SDLoc dl(LD);
+  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
+
+  SDValue Ch = LD->getChain();
+  SDValue Ptr = LD->getBasePtr();
+  EVT MemoryVT = LD->getMemoryVT();
+
+  EVT LoMemVT, HiMemVT;
+  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
+
+  Lo = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, LoMemVT, LoMemVT, Ch, Ptr,
+                     LD->getMemOperand());
+
+  MachinePointerInfo MPI;
+  IncrementPointer(LD, LoMemVT, MPI, Ptr);
+
+  Hi = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, HiMemVT, HiMemVT, Ch, Ptr,
+                     LD->getMemOperand());
+
+  // Build a factor node to remember that this load is independent of the
+  // other one.
+  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+                   Hi.getValue(1));
+
+  // Legalize the chain result - switch anything that used the old chain to
+  // use the new one.
+  ReplaceValueWith(SDValue(LD, 1), Ch);
+}
+
 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
                                         SDValue &Hi) {
   assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll b/llvm/test/CodeGen/X86/atomic-load-store.ll
index ba1bc4d98537d1..302a94aa9c1f60 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -176,6 +176,62 @@ define <2 x float> @atomic_vec2_float_align(ptr %x) nounwind {
   ret <2 x float> %ret
 }
 
+define <2 x half> @atomic_vec2_half(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_half:
+; CHECK3:       ## %bb.0:
+; CHECK3-NEXT:    movzwl (%rdi), %eax
+; CHECK3-NEXT:    movzwl 2(%rdi), %ecx
+; CHECK3-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:    pinsrw $0, %ecx, %xmm1
+; CHECK3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK3-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec2_half:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    movw (%rdi), %dx
+; CHECK0-NEXT:    movw 2(%rdi), %cx
+; CHECK0-NEXT:    ## implicit-def: $eax
+; CHECK0-NEXT:    movw %dx, %ax
+; CHECK0-NEXT:    ## implicit-def: $xmm0
+; CHECK0-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:    ## implicit-def: $eax
+; CHECK0-NEXT:    movw %cx, %ax
+; CHECK0-NEXT:    ## implicit-def: $xmm1
+; CHECK0-NEXT:    pinsrw $0, %eax, %xmm1
+; CHECK0-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK0-NEXT:    retq
+  %ret = load atomic <2 x half>, ptr %x acquire, align 4
+  ret <2 x half> %ret
+}
+
+define <2 x bfloat> @atomic_vec2_bfloat(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_bfloat:
+; CHECK3:       ## %bb.0:
+; CHECK3-NEXT:    movzwl (%rdi), %eax
+; CHECK3-NEXT:    movzwl 2(%rdi), %ecx
+; CHECK3-NEXT:    pinsrw $0, %ecx, %xmm1
+; CHECK3-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK3-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec2_bfloat:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    movw (%rdi), %cx
+; CHECK0-NEXT:    movw 2(%rdi), %dx
+; CHECK0-NEXT:    ## implicit-def: $eax
+; CHECK0-NEXT:    movw %dx, %ax
+; CHECK0-NEXT:    ## implicit-def: $xmm1
+; CHECK0-NEXT:    pinsrw $0, %eax, %xmm1
+; CHECK0-NEXT:    ## implicit-def: $eax
+; CHECK0-NEXT:    movw %cx, %ax
+; CHECK0-NEXT:    ## implicit-def: $xmm0
+; CHECK0-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK0-NEXT:    retq
+  %ret = load atomic <2 x bfloat>, ptr %x acquire, align 4
+  ret <2 x bfloat> %ret
+}
+
 define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
 ; CHECK3-LABEL: atomic_vec1_ptr:
 ; CHECK3:       ## %bb.0:

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

arsenm · 2025-03-04T04:40:21Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -1421,6 +1424,35 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
    SetSplitVector(SDValue(N, ResNo), Lo, Hi);
 }

+void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD) {


This is missing the Lo / Hi out arguments, like all of the other SplitVecRes cases. You should still be trying to respect the result of DAG.GetSplitDestVTs. With this you are bypassing SetSplitVector

I had tried doing it by splitting Lo and Hi. I ran into an issue though because TokenFactor (what we join our values on) requires glue operands; however, EXTRACT_SUBVECTOR does not have these, nor does DAG.getAtomicLoad.

TokenFactor does not require glue operands. The most common use case for TokenFactor is pairing a modified real value with a chain

EXTRACT_SUBVECTOR does not have chain operands, nor does DAG.getAtomicLoad. I checked a few others too, but do we not need to use a TokenFactor if you are saying we do not have to associate Lo and Hi?

arsenm · 2025-03-04T04:41:12Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+                    LD->getChain(), LD->getBasePtr(), LD->getMemOperand());
+
+  // Instead of splitting, put all the elements back into a vector.
+  SmallVector<SDValue, 4> Ops;


This loop can be replaced with DAG.ExtractVectorElements (but I don't think you should be scalarizing here like this)

arsenm · 2025-03-04T04:43:11Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+  }
+  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, dl, MemoryVT, Ops);
+
+  ReplaceValueWith(SDValue(LD, 0), Concat);


This replacement should be done piecewise in the caller, you should be inserting casting code to satisfy the two DAG.GetSplitDestVTs pieces

I see. That is done by using a TokenFactor to associate the Lo and Hi value. However, replacing the TokenFactor is not possible because we can not create it out of operands without glue.

You don't need to associate the Hi and Lo halves, you need to report the Hi and Lo halves to the caller. The only special thing you need to do here is replace the chain uses, as is done in the non-atomic load case

How do you associate both chain uses at once? Doesn't that require a TokenFactor to replace?

There are not multiple chains. The original atomic_load had a chain output and a chain result. The new coerced load has a different output chain, which you replace with the new result chain. The type coercion code is chain free and doesn't care

I'm talking about chain uses of Lo and Hi. The atomic_load lowering contains this, which looks to be associating the values:

Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), Hi.getValue(1));

However, Lo and Hi are uses from getLoad/getAtomicLoad, but getAtomicLoad does not have the chain that TokenFactor wants.

TokenFactor of a single input is identical to the single input value. But the atomic_load lowering should not contain this. The new lowering has exactly one chain as the original load. The atomic_load is specifically not being split, only the type profile is changing

arsenm · 2025-05-05T18:01:06Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+  EVT LoMemVT, HiMemVT;
+  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);


These are unused. You at most should be bit casting the in memory type to the target integer memory type, there's no splitting

Only one has to be used to get double that size. May we just remove it all and use MemoryVT.getSizeInBits()?

arsenm · 2025-05-05T18:01:30Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), LD->getValueType(0).getSizeInBits());
+  EVT MemIntVT = EVT::getIntegerVT(*DAG.getContext(), LD->getMemoryVT().getSizeInBits());
+  SDValue ALD = DAG.getAtomicLoad(ExtType, dl, MemIntVT, IntVT, Ch, Ptr,
+                                  LD->getMemOperand());


Maybe should assert this isn't an extending load, although you could in principle handle it

This will fail for some reason, on at least atomic_vec2_ptr270 and atomic_vec2_half.

Maybe the right thing to do is just create a non-extending load of the bitcast in-memory type

arsenm · 2025-05-05T18:02:03Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+  EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
+  EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
+  SDValue ExtractLo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, LoIntVT, ALD,
+                                  DAG.getVectorIdxConstant(0, dl));


This isn't a vector extract, so don't use getVectorIdxConstant. I'm not actually sure what the type for the second operand is supposed to be for extract_element

arsenm · 2025-05-06T09:29:34Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+  EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
+  EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
+  SDValue ExtractLo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, LoIntVT, ALD,
+                                  DAG.getIntPtrConstant(0, dl));


This probably should be a target constant but this appears to be what existing uses do

arsenm · 2025-05-06T17:31:36Z

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+  EVT MemIntVT =
+      EVT::getIntegerVT(*DAG.getContext(), 2 * LoMemVT.getSizeInBits());


MemVT should not be a derived quantity, directly bitcast the original memory type

Vector types that aren't widened are split so that a single ATOMIC_LOAD is issued for the entire vector at once. This change utilizes the load vectorization infrastructure in SelectionDAG in order to group the vectors. This enables SelectionDAG to translate vectors with type bfloat,half. commit-id:3a045357

llvmbot added backend:X86 llvm:SelectionDAG SelectionDAGISel as well labels Dec 19, 2024

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[AtomicExpand] Add bitcasts when expanding load atomic vector #120716

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jofrn changed the title ~~[SelectionDAG] Split <n x T> vector types for atomic load~~ [X86] load atomic vector tests for combine Jan 2, 2025

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jofrn changed the title ~~[X86] load atomic vector tests for combine~~ [SelectionDAG][X86] Split <2 x T> vector types for atomic load Jan 6, 2025

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jofrn changed the title ~~[SelectionDAG][X86] Split via Concat <n x T> vector types for atomic load~~ [SelectionDAG] Split vector types for atomic load May 5, 2025

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[X86] Remove extra MOV after widening atomic load #138635

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[SelectionDAG] Split vector types for atomic load #120640

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		EVT LoMemVT, HiMemVT;
		std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);

		EVT MemIntVT =
		EVT::getIntegerVT(DAG.getContext(), 2 LoMemVT.getSizeInBits());

[SelectionDAG] Split vector types for atomic load #120640

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