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[mlir][xegpu] SIMT distribution patterns for XeGPU CreateNdTdesc, LoadNd, StoreNd and Dpas Ops. #135271

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Merged
merged 101 commits into from
Apr 30, 2025

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charithaintc
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@charithaintc charithaintc commented Apr 10, 2025

This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.

Depends on: #135116

Comment on lines 338 to 340
TypeSwitch<Operation *>(op)
.Case<xegpu::DpasOp>(
[&](auto dpasOp) { visitDpasOp(dpasOp, operands, results); })
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Similar to the sharding propagation, you might consider using an OpInterface for this. It allows for a nicer code structure (the code is with the operation, not the lattice), for easier extension and for prettier dispatch code.

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I will take a look at your code. I think we can try to incorporate those ideas as well in future.

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Hi @fschlimb, this is Charitha from the IMEX team. We have the initial part of the XeGPU subgroup - SIMT distribution work ready for review. If you are interested and have the bandwidth, please have a look and give us feedback/approval. Thanks!

Thanks for getting in touch, interesting!

I added a few comments. This is not an area that I typically work in, so they are mostly on monkey level.

While distribution is different in this context than in the context of distributed memory, there a commonalities (similar to similarities in tiling and sharding). It seems to me that tiling/vector-distribution are special cases of general sharding/spmdization. Unification might be worth considering.

Hi Frank, thanks very much for the review. I tried to address everything as much as I can. please take a look.

Out of curiosity, in addition to the question about the forward propagation, I wonder how tensor shapes that do not evenly divide to lane-sizes would be treated.

Good question. For the operators handled in this PR, we expect perfect distribution. If the high-level work group level computation does not map to lane sizes evenly, it is the responsibility of work group to subgroup or subsequent optimizations to ensure perfect distribution at SIMT level. I think this will be done using masking gather/scatter type loads.

Also we check this requirement during the lowering. If the vector shape is not distributable pass will report that and fail.

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Overall structure LGTM % open comments
I lack experience in the distribution itself to give in-depth review of the core logic but nothing obvious catches my eye

@charithaintc charithaintc merged commit d30554b into llvm:main Apr 30, 2025
6 of 9 checks passed
@kazutakahirata
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@charithaintc I've landed b2e2ae8 to fix warnings from this PR. Thanks!

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@charithaintc I've landed b2e2ae8 to fix warnings from this PR. Thanks!

Thanks!

IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
…dNd, StoreNd and Dpas Ops. (llvm#135271)

This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
…dNd, StoreNd and Dpas Ops. (llvm#135271)

This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
…dNd, StoreNd and Dpas Ops. (llvm#135271)

This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
GeorgeARM pushed a commit to GeorgeARM/llvm-project that referenced this pull request May 7, 2025
…dNd, StoreNd and Dpas Ops. (llvm#135271)

This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
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7 participants