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[mlir][xegpu] SIMT distribution patterns for XeGPU CreateNdTdesc, LoadNd, StoreNd and Dpas Ops. #135271
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Hi Frank, thanks very much for the review. I tried to address everything as much as I can. please take a look.
Good question. For the operators handled in this PR, we expect perfect distribution. If the high-level work group level computation does not map to lane sizes evenly, it is the responsibility of work group to subgroup or subsequent optimizations to ensure perfect distribution at SIMT level. I think this will be done using masking gather/scatter type loads. Also we check this requirement during the lowering. If the vector shape is not distributable pass will report that and fail. |
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Overall structure LGTM % open comments
I lack experience in the distribution itself to give in-depth review of the core logic but nothing obvious catches my eye
@charithaintc I've landed b2e2ae8 to fix warnings from this PR. Thanks! |
Thanks! |
…dNd, StoreNd and Dpas Ops. (llvm#135271) This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
…dNd, StoreNd and Dpas Ops. (llvm#135271) This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
…dNd, StoreNd and Dpas Ops. (llvm#135271) This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
…dNd, StoreNd and Dpas Ops. (llvm#135271) This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
…dNd, StoreNd and Dpas Ops. (llvm#135271) This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
This PR adds the SIMT distribution patterns for create_nd_tdesc, load_nd, store_nd and dpas XeGPU ops.
Depends on: #135116