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Add more enums for L4 clock selections. #720

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Merged
merged 7 commits into from
May 15, 2022
Merged

Add more enums for L4 clock selections. #720

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003395f
Add more enums for L4 clock selections.
reitermarkus Apr 17, 2022
4d51182
Move `USART{2-5}EN` to separate file.
reitermarkus Apr 18, 2022
ccc6de4
Fix L4 `UART/USARTxEN` enums.
reitermarkus Apr 18, 2022
cbc357c
Remove reserved enum value.
reitermarkus Apr 22, 2022
7f2343d
Fix HSI48 description.
reitermarkus May 15, 2022
c7bebc7
Fix ADCSEL description.
reitermarkus May 15, 2022
bc9b117
Remove suffix for RTCSEL HSE clock.
reitermarkus May 15, 2022
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2 changes: 2 additions & 0 deletions devices/stm32l4x1.yaml
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Expand Up @@ -103,6 +103,8 @@ _include:
- ../peripherals/crc/crc_with_polysize.yaml
- ../peripherals/wwdg/wwdg.yaml
- ../peripherals/rcc/rcc_l4.yaml
- ../peripherals/rcc/rcc_l4_usart2_3.yaml
- ../peripherals/rcc/rcc_l4_uart4.yaml
- common_patches/tim/common.yaml
- ../peripherals/tim/tim_basic.yaml
- ../peripherals/tim/tim16.yaml
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2 changes: 2 additions & 0 deletions devices/stm32l4x2.yaml
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Expand Up @@ -11,3 +11,5 @@ _include:
- common_patches/rtc/rtc_bkpr.yaml
- ./common_patches/l4_gpio_brr.yaml
- ../peripherals/fw/fw_l0_l4.yaml
- ../peripherals/rcc/rcc_l4_usart2_3.yaml
- ../peripherals/rcc/rcc_l4_uart4.yaml
1 change: 1 addition & 0 deletions devices/stm32l4x3.yaml
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Expand Up @@ -134,6 +134,7 @@ _include:
- ../peripherals/crc/crc_with_polysize.yaml
- ../peripherals/wwdg/wwdg.yaml
- ../peripherals/rcc/rcc_l4.yaml
- ../peripherals/rcc/rcc_l4_usart2_3.yaml
- common_patches/tim/common.yaml
- ../peripherals/tim/tim_basic.yaml
- ../peripherals/tim/tim16.yaml
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3 changes: 3 additions & 0 deletions devices/stm32l4x5.yaml
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Expand Up @@ -162,6 +162,9 @@ _include:
- ../peripherals/crc/crc_with_polysize.yaml
- ../peripherals/wwdg/wwdg.yaml
- ../peripherals/rcc/rcc_l4.yaml
- ../peripherals/rcc/rcc_l4_usart2_3.yaml
- ../peripherals/rcc/rcc_l4_uart4.yaml
- ../peripherals/rcc/rcc_l4_uart5.yaml
- common_patches/tim/common.yaml
- ../peripherals/tim/tim_basic.yaml
- ../peripherals/tim/tim16.yaml
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3 changes: 3 additions & 0 deletions devices/stm32l4x6.yaml
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Expand Up @@ -60,6 +60,9 @@ _include:
- ../peripherals/crc/crc_with_polysize.yaml
- ../peripherals/wwdg/wwdg.yaml
- ../peripherals/rcc/rcc_l4.yaml
- ../peripherals/rcc/rcc_l4_usart2_3.yaml
- ../peripherals/rcc/rcc_l4_uart4.yaml
- ../peripherals/rcc/rcc_l4_uart5.yaml
- common_patches/tim/common.yaml
- ../peripherals/tim/tim_basic.yaml
- ../peripherals/tim/tim16.yaml
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73 changes: 73 additions & 0 deletions peripherals/rcc/rcc_l4.yaml
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@@ -1,4 +1,36 @@
RCC:
AHB2ENR:
ADCEN:
Disabled: [0, "ADC clock disabled"]
Enabled: [1, "ADC clock enabled"]

APB2ENR:
USART1EN:
Disabled: [0, "USART1 clock disabled"]
Enabled: [1, "USART1 clock enabled"]

APB1ENR1:
LPTIM1EN:
Disabled: [0, "LPTIM1 clock disabled"]
Enabled: [1, "LPTIM1 clock enabled"]
I2C3EN:
Disabled: [0, "I2C3 clock disabled"]
Enabled: [1, "I2C3 clock enabled"]
I2C2EN:
Disabled: [0, "I2C2 clock disabled"]
Enabled: [1, "I2C2 clock enabled"]
I2C1EN:
Disabled: [0, "I2C1 clock disabled"]
Enabled: [1, "I2C1 clock enabled"]

APB1ENR2:
LPTIM2EN:
Disabled: [0, "LPTIM2 clock disabled"]
Enabled: [1, "LPTIM2 clock enabled"]
LPUART1EN:
Disabled: [0, "LPUART1 clock disabled"]
Enabled: [1, "LPUART1 clock enabled"]

CR:
MSIRANGE:
Range100K: [0b0000, "range 0 around 100 kHz"]
Expand All @@ -13,3 +45,44 @@ RCC:
Range24M: [0b1001, "range 9 around 24 MHz"]
Range32M: [0b1010, "range 10 around 32 MHz"]
Range48M: [0b1011, "range 11 around 48 MHz"]

CCIPR:
ADCSEL:
NoClock: [0, "No clock selected"]
PLLSAI1: [1, "PLLSAI1 clock selected"]
PLLSAI2: [2, "PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)"]
SYSCLK: [3, "SYSCLK clock selected"]
CLK48SEL:
HSI48: [0, "HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)"]
PLLSAI1: [1, "PLLSAI1 clock selected"]
PLL: [2, "PLL clock selected"]
MSI: [3, "MSI clock selected"]
"LPTIM[123]SEL":
PCLK: [0, "PCLK clock selected"]
LSI: [1, "LSI clock selected"]
HSI16: [2, "HSI16 clock selected"]
LSE: [3, "LSE clock selected"]
"I2C[123]SEL":
PCLK: [0, "PCLK clock selected"]
SYSCLK: [1, "SYSCLK clock selected"]
HSI16: [2, "HSI16 clock selected"]
LPUART1SEL:
PCLK: [0, "PCLK clock selected"]
SYSCLK: [1, "SYSCLK clock selected"]
HSI16: [2, "HSI16 clock selected"]
LSE: [3, "LSE clock selected"]
"USART[12345]SEL":
PCLK: [0, "PCLK clock selected"]
SYSCLK: [1, "SYSCLK clock selected"]
HSI16: [2, "HSI16 clock selected"]
LSE: [3, "LSE clock selected"]

BDCR:
RTCEN:
Disabled: [0, "RTC clock disabled"]
Enabled: [1, "RTC clock enabled"]
RTCSEL:
NoClock: [0, "No clock"]
LSE: [1, "LSE oscillator clock selected"]
LSI: [2, "LSI oscillator clock selected"]
HSE: [3, "HSE oscillator clock divided by 32 selected"]
5 changes: 5 additions & 0 deletions peripherals/rcc/rcc_l4_uart4.yaml
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@@ -0,0 +1,5 @@
RCC:
APB1ENR1:
UART4EN:
Disabled: [0, "UART4 clock disabled"]
Enabled: [1, "UART4 clock enabled"]
5 changes: 5 additions & 0 deletions peripherals/rcc/rcc_l4_uart5.yaml
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@@ -0,0 +1,5 @@
RCC:
APB1ENR1:
UART5EN:
Disabled: [0, "UART5 clock disabled"]
Enabled: [1, "UART5 clock enabled"]
8 changes: 8 additions & 0 deletions peripherals/rcc/rcc_l4_usart2_3.yaml
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@@ -0,0 +1,8 @@
RCC:
APB1ENR1:
USART3EN:
Disabled: [0, "USART3 clock disabled"]
Enabled: [1, "USART3 clock enabled"]
USART2EN:
Disabled: [0, "USART2 clock disabled"]
Enabled: [1, "USART2 clock enabled"]