RISC-V: Update the timer implementations to use the arch mtimer #2519
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Signed-off-by: Alistair Francis <[email protected]>
hudson-ayers
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Apr 7, 2021
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Sorry, I didn't mean to push that directly to your branch, so I pushed it back. hudson-ayers@6844c4e is a commit that constructs the mtimer only once, if you are happy with it. It makes the constructors no longer |
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Ah, I didn't think about using the static address to do it! Thanks for that. Do you mind fixing up the SiFive CLINT as well? Feel free to push the changes to this branch/PR. |
hudson-ayers
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Apr 7, 2021
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hudson-ayers
approved these changes
Apr 7, 2021
bradjc
approved these changes
Apr 8, 2021
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bors r+ |
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Pull Request Overview
This fixes #2490 by using the generic RISC-V architecture version of mtimer for all of the RISC-V chips.
Testing Strategy
CI
TODO or Help Wanted
N/A
Documentation Updated
/docs, or no updates are required.Formatting
make prepush.