MachineSink.cpp File Reference

#include "llvm/CodeGen/MachineSink.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/CFG.h"
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineCycleAnalysis.h"
#include "llvm/CodeGen/MachineDomTreeUpdater.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSizeOpts.h"
#include "llvm/CodeGen/PostRAMachineSink.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstdint>
#include <utility>
#include <vector>

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "machine-sink"

Typedefs
using	RegSubRegPair = TargetInstrInfo::RegSubRegPair
using	MIRegs = std::pair<MachineInstr *, SmallVector<Register, 2>>

Functions
	STATISTIC (NumSunk, "Number of machine instructions sunk")
	STATISTIC (NumCycleSunk, "Number of machine instructions sunk into a cycle")
	STATISTIC (NumSplit, "Number of critical edges split")
	STATISTIC (NumCoalesces, "Number of copies coalesced")
	STATISTIC (NumPostRACopySink, "Number of copies sunk after RA")
	INITIALIZE_PASS_BEGIN (MachineSinkingLegacy, DEBUG_TYPE, "Machine code sinking", false, false) INITIALIZE_PASS_END(MachineSinkingLegacy
Machine code static false bool	blockPrologueInterferes (const MachineBasicBlock *BB, MachineBasicBlock::const_iterator End, const MachineInstr &MI, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, const MachineRegisterInfo *MRI)
	Return true if a target defined block prologue instruction interferes with a sink candidate.
static bool	mayLoadFromGOTOrConstantPool (MachineInstr &MI)
	Return true if this machine instruction loads from global offset table or constant pool.
static bool	SinkingPreventsImplicitNullCheck (MachineInstr &MI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
	Return true if MI is likely to be usable as a memory operation by the implicit null check optimization.
static bool	attemptDebugCopyProp (MachineInstr &SinkInst, MachineInstr &DbgMI, Register Reg)
	If the sunk instruction is a copy, try to forward the copy instead of leaving an 'undef' DBG_VALUE in the original location.
static void	performSink (MachineInstr &MI, MachineBasicBlock &SuccToSinkTo, MachineBasicBlock::iterator InsertPos, ArrayRef< MIRegs > DbgValuesToSink)
	Sink an instruction and its associated debug instructions.
	INITIALIZE_PASS (PostRAMachineSinkingLegacy, "postra-machine-sink", "PostRA Machine Sink", false, false) static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB
LiveInRegUnits	addLiveIns (MBB)
return !LiveInRegUnits	available (Reg)
static MachineBasicBlock *	getSingleLiveInSuccBB (MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock * > &SinkableBBs, Register Reg, const TargetRegisterInfo *TRI)
static MachineBasicBlock *	getSingleLiveInSuccBB (MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock * > &SinkableBBs, ArrayRef< Register > DefedRegsInCopy, const TargetRegisterInfo *TRI)
static void	clearKillFlags (MachineInstr *MI, MachineBasicBlock &CurBB, const SmallVectorImpl< unsigned > &UsedOpsInCopy, const LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
static void	updateLiveIn (MachineInstr *MI, MachineBasicBlock *SuccBB, const SmallVectorImpl< unsigned > &UsedOpsInCopy, const SmallVectorImpl< Register > &DefedRegsInCopy)
static bool	hasRegisterDependency (MachineInstr *MI, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< Register > &DefedRegsInCopy, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits)

Variables
static cl::opt< bool >	SplitEdges ("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden)
static cl::opt< bool >	UseBlockFreqInfo ("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden)
static cl::opt< unsigned >	SplitEdgeProbabilityThreshold ("machine-sink-split-probability-threshold", cl::desc("Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden)
static cl::opt< unsigned >	SinkLoadInstsPerBlockThreshold ("machine-sink-load-instrs-threshold", cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold."), cl::init(2000), cl::Hidden)
static cl::opt< unsigned >	SinkLoadBlocksThreshold ("machine-sink-load-blocks-threshold", cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold."), cl::init(20), cl::Hidden)
static cl::opt< bool >	SinkInstsIntoCycle ("sink-insts-to-avoid-spills", cl::desc("Sink instructions into cycles to avoid " "register spills"), cl::init(false), cl::Hidden)
static cl::opt< unsigned >	SinkIntoCycleLimit ("machine-sink-cycle-limit", cl::desc("The maximum number of instructions considered for cycle sinking."), cl::init(50), cl::Hidden)
	DEBUG_TYPE
Machine code	sinking
Machine code	false
Register	Reg
Register const TargetRegisterInfo *	TRI

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "machine-sink"

Definition at line 71 of file MachineSink.cpp.

Typedef Documentation

MIRegs

using MIRegs = std::pair<MachineInstr *, SmallVector<Register, 2>>

Definition at line 1606 of file MachineSink.cpp.

RegSubRegPair

using RegSubRegPair = TargetInstrInfo::RegSubRegPair

Definition at line 122 of file MachineSink.cpp.

Function Documentation

addLiveIns()

LiveInRegUnits addLiveIns

(

MBB

)

References MBB.

attemptDebugCopyProp()

bool attemptDebugCopyProp ( MachineInstr & SinkInst, MachineInstr & DbgMI, Register Reg )

static

If the sunk instruction is a copy, try to forward the copy instead of leaving an 'undef' DBG_VALUE in the original location.

Don't do this if there's any subregister weirdness involved. Returns true if copy propagation occurred.

Definition at line 1556 of file MachineSink.cpp.

References llvm::MachineInstr::getDebugOperandsForReg(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getMF(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::Register::isVirtual(), MRI, Reg, and TII.

Referenced by performSink().

available()

return !LiveInRegUnits available

(

Reg

)

References Reg.

blockPrologueInterferes()

Machine code static false bool blockPrologueInterferes ( const MachineBasicBlock * BB, MachineBasicBlock::const_iterator End, const MachineInstr & MI, const TargetRegisterInfo * TRI, const TargetInstrInfo * TII, const MachineRegisterInfo * MRI )

static

Return true if a target defined block prologue instruction interferes with a sink candidate.

Definition at line 336 of file MachineSink.cpp.

References blockPrologueInterferes(), const, MI, MRI, TII, and TRI.

Referenced by blockPrologueInterferes().

clearKillFlags()

void clearKillFlags ( MachineInstr * MI, MachineBasicBlock & CurBB, const SmallVectorImpl< unsigned > & UsedOpsInCopy, const LiveRegUnits & UsedRegUnits, const TargetRegisterInfo * TRI )

static

Definition at line 2167 of file MachineSink.cpp.

References llvm::LiveRegUnits::available(), llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), llvm::make_range(), MI, llvm::MachineOperand::setIsKill(), and TRI.

getSingleLiveInSuccBB() [1/2]

MachineBasicBlock * getSingleLiveInSuccBB ( MachineBasicBlock & CurBB, const SmallPtrSetImpl< MachineBasicBlock * > & SinkableBBs, ArrayRef< Register > DefedRegsInCopy, const TargetRegisterInfo * TRI )

static

Definition at line 2152 of file MachineSink.cpp.

References getSingleLiveInSuccBB(), and TRI.

getSingleLiveInSuccBB() [2/2]

MachineBasicBlock * getSingleLiveInSuccBB ( MachineBasicBlock & CurBB, const SmallPtrSetImpl< MachineBasicBlock * > & SinkableBBs, Register Reg, const TargetRegisterInfo * TRI )

static

Definition at line 2125 of file MachineSink.cpp.

References llvm::SmallPtrSetImpl< PtrType >::count(), Reg, llvm::MachineBasicBlock::successors(), and TRI.

Referenced by getSingleLiveInSuccBB().

hasRegisterDependency()

bool hasRegisterDependency ( MachineInstr * MI, SmallVectorImpl< unsigned > & UsedOpsInCopy, SmallVectorImpl< Register > & DefedRegsInCopy, LiveRegUnits & ModifiedRegUnits, LiveRegUnits & UsedRegUnits )

static

Definition at line 2200 of file MachineSink.cpp.

References llvm::LiveRegUnits::available(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and Reg.

INITIALIZE_PASS()

INITIALIZE_PASS	(	PostRAMachineSinkingLegacy	,
		"postra-machine-sink"	,
		"PostRA Machine Sink"	,
		false	,
		false	) &

INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	MachineSinkingLegacy	,
		DEBUG_TYPE	,
		"Machine code sinking"	,
		false	,
		false	)

References DEBUG_TYPE, and INITIALIZE_PASS_DEPENDENCY.

mayLoadFromGOTOrConstantPool()

bool mayLoadFromGOTOrConstantPool ( MachineInstr & MI )

static

Return true if this machine instruction loads from global offset table or constant pool.

Definition at line 699 of file MachineSink.cpp.

References assert(), and MI.

performSink()

void performSink ( MachineInstr & MI, MachineBasicBlock & SuccToSinkTo, MachineBasicBlock::iterator InsertPos, ArrayRef< MIRegs > DbgValuesToSink )

static

Sink an instruction and its associated debug instructions.

Definition at line 1608 of file MachineSink.cpp.

References attemptDebugCopyProp(), llvm::dwarf_linker::DebugLoc, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::DebugLoc::getMergedLocation(), llvm::MachineInstr::getMF(), llvm::MachineInstr::hasDebugOperandForReg(), llvm::MachineBasicBlock::insert(), MI, Reg, llvm::MachineInstr::setDebugValueUndef(), and llvm::MachineBasicBlock::splice().

SinkingPreventsImplicitNullCheck()

bool SinkingPreventsImplicitNullCheck ( MachineInstr & MI, const TargetInstrInfo * TII, const TargetRegisterInfo * TRI )

static

Return true if MI is likely to be usable as a memory operation by the implicit null check optimization.

This is a "best effort" heuristic, and should not be relied upon for correctness. This returning true does not guarantee that the implicit null check optimization is legal over MI, and this returning false does not guarantee MI cannot possibly be used to do a null check.

Definition at line 1511 of file MachineSink.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MBB, MI, llvm::Offset, TII, and TRI.

STATISTIC() [1/5]

STATISTIC	(	NumCoalesces	,
		"Number of copies coalesced"	)

STATISTIC() [2/5]

STATISTIC	(	NumCycleSunk	,
		"Number of machine instructions sunk into a cycle"	)

STATISTIC() [3/5]

STATISTIC	(	NumPostRACopySink	,
		"Number of copies sunk after RA"	)

STATISTIC() [4/5]

STATISTIC	(	NumSplit	,
		"Number of critical edges split"	)

STATISTIC() [5/5]

STATISTIC	(	NumSunk	,
		"Number of machine instructions sunk"	)

updateLiveIn()

void updateLiveIn ( MachineInstr * MI, MachineBasicBlock * SuccBB, const SmallVectorImpl< unsigned > & UsedOpsInCopy, const SmallVectorImpl< Register > & DefedRegsInCopy )

static

Definition at line 2187 of file MachineSink.cpp.

References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), MI, llvm::MachineBasicBlock::removeLiveIn(), llvm::MachineBasicBlock::sortUniqueLiveIns(), and TRI.

Variable Documentation

DEBUG_TYPE

DEBUG_TYPE

Definition at line 331 of file MachineSink.cpp.

false

Machine code false

Definition at line 332 of file MachineSink.cpp.

Reg

Register Reg

Definition at line 2117 of file MachineSink.cpp.

Referenced by llvm::LiveRegUnits::accumulateUsedDefed(), addAsmInstr(), llvm::X86MachineFunctionInfo::addCandidateForPush2Pop2(), addConstantsToTrack(), addDebugSubstitutionsToTable(), llvm::addDirectMem(), addExclusiveRegPair(), llvm::Loc::EntryValue::addExpr(), addHints(), addImplicitDefs(), llvm::MachineRegisterInfo::addLiveIn(), llvm::FunctionLoweringInfo::AddLiveOutRegInfo(), llvm::PPCFunctionInfo::addMustSaveCR(), llvm::LivePhysRegs::addReg(), llvm::LiveRegUnits::addReg(), llvm::MCInstBuilder::addReg(), addRegAndItsAliases(), llvm::M68k::addRegIndirectWithDisp(), llvm::LiveRegUnits::addRegMasked(), llvm::addRegOffset(), addRegUnits(), addSaveRestoreRegs(), llvm::LoongArchMachineFunctionInfo::addSExt32Register(), AddSubReg(), addToFwdRegWorklist(), llvm::SIMachineFunctionInfo::addToPrologEpilogSGPRSpills(), llvm::MipsInstrInfo::adjustStackPtr(), llvm::AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(), allocateFixedSGPRInputImpl(), llvm::CCState::AllocateReg(), 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llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineInstr::findRegisterUseOperand(), llvm::MachineInstr::findRegisterUseOperand(), findRenameRegForSameLdStRegPair(), findScratchNonCalleeSaveRegister(), findSingleRegDef(), findSingleRegUse(), findStartOfTree(), findSurvivorBackwards(), findTemporariesForLR(), findUniqueOperandDefinedInLoop(), llvm::LegalizationArtifactCombiner::ArtifactValueFinder::findUnmergeThatDefinesReg(), findUnusedRegister(), findUseBetween(), findUseBetween(), flagsNeedToBePreservedBeforeTheTerminators(), llvm::TargetInstrInfo::foldImmediate(), FollowCopyChain(), forceReg(), generateAssignInstrs(), llvm::MCRegisterInfo::get(), getADAEntry(), llvm::rdf::PhysicalRegisterInfo::getAliasSet(), getAMXRegNum(), getAnySgprS1(), getARClassRegisterMask(), getBaseWithConstantOffset(), llvm::getBRegFromDReg(), getBundledDefMI(), getBundledUseMI(), llvm::RAGreedy::ExtraRegInfo::getCascade(), llvm::RAGreedy::ExtraRegInfo::getCascadeOrCurrentNext(), getComputePGMRSrc1Reg(), getComputePGMRSrc2Reg(), getConstantZext32Val(), llvm::getConstFromIntrinsic(), llvm::TargetInstrInfo::getConstValDefinedInReg(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getCopyToReg(), GetCostForDef(), llvm::getCRFromCRBit(), llvm::CCValAssign::getCustomReg(), getDataDeps(), getDebugOperandsForRegHelper(), llvm::getDRegFromBReg(), GetDSubRegs(), getDwarfRegNum(), llvm::MipsFunctionInfo::getEhDataRegFI(), llvm::MCRegisterInfo::getEncodingValue(), getFoldableImm(), getFPReg(), getFrameHelperName(), llvm::TargetRegisterInfo::getFrameRegister(), getHexagonRegisterPair(), llvm::SPIRV::getIDFromRegister(), getIndirectThunkSymbol(), getIndVarInfo(), getInstReadLaneMask(), getInstrVecReg(), llvm::LiveIntervals::getInterval(), llvm::LiveIntervals::getInterval(), llvm::MipsFunctionInfo::getISRRegFI(), getJumpTableIndexFromReg(), llvm::getLanaiRegisterNumbering(), getLastSameOrNeg(), llvm::FunctionLoweringInfo::GetLiveOutRegInfo(), getLiveRange(), llvm::TargetInstrInfo::getLiveRangeSplitOpcode(), llvm::getLiveRegMap(), getLoadStoreRegOpcode(), getLocalId(), LiveDebugValues::MLocTracker::getLocID(), getLoopPhiUser(), getMappedReg(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getMax32BitSubRegister(), getMaxCalleeSavedReg(), getMClassRegisterMask(), llvm::AMDGPU::getMCReg(), getMinimalPhysRegClass(), llvm::getMSARegFromFReg(), getNegStatus(), getNextOrderedReg(), getNextRegister(), getNextVectorRegister(), getNumAllocatableRegsForConstraints(), getNumDefTiles(), llvm::MachineRegisterInfo::getOneDef(), llvm::getOpcodeDef(), llvm::RAGreedy::ExtraRegInfo::getOrAssignNewCascade(), llvm::LiveIntervals::getOrCreateEmptyInterval(), llvm::RAGreedy::ExtraRegInfo::getOrInitStage(), getPairedGPR(), getPGMRSrc1Reg(), getPHIDeps(), getPhysicalRegisterVT(), getPhysicalRegisterVT(), llvm::TargetRegisterInfo::getPhysRegBaseClass(), getPopFromX87Reg(), llvm::AVRInstPrinter::getPrettyRegisterName(), llvm::SIMachineFunctionInfo::getPrologEpilogSGPRSaveRestoreInfo(), getPrologueDeath(), llvm::rdf::PhysicalRegisterInfo::getRefForUnit(), llvm::CCValAssign::getReg(), llvm::SystemZMC::getRegAsGR32(), llvm::SystemZMC::getRegAsGR64(), llvm::SystemZMC::getRegAsGRH32(), llvm::TargetRegisterInfo::getRegAsmName(), llvm::SystemZMC::getRegAsVR128(), llvm::MachineRegisterInfo::getRegBank(), llvm::MachineRegisterInfo::getRegBankOrNull(), getRegClass(), llvm::MachineRegisterInfo::getRegClass(), getRegClassFromGRPhysReg(), llvm::MachineRegisterInfo::getRegClassOrNull(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::TargetRegisterInfo::getRegClassWeight(), getRegForPrinting(), getRegFromMIA(), llvm::SPIRV::ModuleAnalysisInfo::getRegisterAlias(), llvm::AVRTargetLowering::getRegisterByName(), getRegisterName(), llvm::AArch64AppleInstPrinter::getRegisterName(), llvm::AArch64InstPrinter::getRegisterName(), llvm::AMDGPUInstPrinter::getRegisterName(), llvm::ARCInstPrinter::getRegisterName(), llvm::ARMInstPrinter::getRegisterName(), llvm::BPFInstPrinter::getRegisterName(), llvm::CSKYInstPrinter::getRegisterName(), llvm::HexagonInstPrinter::getRegisterName(), llvm::LanaiInstPrinter::getRegisterName(), llvm::LoongArchInstPrinter::getRegisterName(), llvm::M68kInstPrinter::getRegisterName(), llvm::MipsInstPrinter::getRegisterName(), llvm::MSP430InstPrinter::getRegisterName(), llvm::NVPTXInstPrinter::getRegisterName(), llvm::PPCInstPrinter::getRegisterName(), llvm::R600InstPrinter::getRegisterName(), llvm::RISCVInstPrinter::getRegisterName(), llvm::SparcInstPrinter::getRegisterName(), llvm::SPIRVInstPrinter::getRegisterName(), llvm::SystemZGNUInstPrinter::getRegisterName(), llvm::SystemZHLASMInstPrinter::getRegisterName(), llvm::VEInstPrinter::getRegisterName(), llvm::WebAssemblyInstPrinter::getRegisterName(), llvm::X86ATTInstPrinter::getRegisterName(), llvm::X86IntelInstPrinter::getRegisterName(), llvm::XCoreInstPrinter::getRegisterName(), llvm::XtensaInstPrinter::getRegisterName(), getRegisterOrZero(), getRegisterSize(), getRegLiveThroughMask(), getRegName(), getRegTy(), getRegularRegInfo(), getRelaxedOpcode(), llvm::AVRRegisterInfo::getReservedRegs(), getRVVBaseRegister(), llvm::SIMachineFunctionInfo::getScratchSGPRCopyDstReg(), llvm::X86::getSegmentOverridePrefixForReg(), getSetupCost(), getSingleLiveInSuccBB(), getSpillArea(), getSrcStats(), llvm::RAGreedy::ExtraRegInfo::getStage(), llvm::getStringValueFromReg(), llvm::getSuperReg(), llvm::getSuperRegs(), getTestBitReg(), getTileDefNum(), getTMMIndex(), llvm::getTrackingRegs(), llvm::MachineRegisterInfo::getType(), getUnwindRuleRegSet(), getv64i1Argument(), getVectorRegSize(), getVectorShiftImm(), getVectorSHLImm(), llvm::AMDGPU::getVGPREncodingMSBs(), llvm::AMDGPU::getVGPRPhysRegClass(), llvm::AMDGPU::getVGPRWithMSBs(), getVReg(), llvm::MachineRegisterInfo::getVRegAttrs(), getVRegDef(), llvm::getVRegDef(), llvm::TargetRegisterInfo::getVRegFlagsOfReg(), llvm::MachineRegisterInfo::getVRegName(), llvm::WebAssembly::getWARegStackId(), llvm::getWRegFromXReg(), llvm::getXRegFromWReg(), handleNDDOrNFInstructions(), handleNormalInst(), handleRegMaskClobber(), llvm::BitTracker::has(), hasAnyNonFlatUseOfReg(), hasArgumentDef(), llvm::MachineInstr::hasDebugOperandForReg(), llvm::MachineOperand::hash_value, llvm::MCInstrDesc::hasImplicitUseOfPhysReg(), llvm::LiveIntervals::hasInterval(), hasLiveThroughUse(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), llvm::SIMachineFunctionInfo::hasPrologEpilogSGPRSpillEntry(), llvm::SPIRV::ModuleAnalysisInfo::hasRegisterAlias(), hasRegisterDependency(), llvm::TargetRegisterInfo::hasRegUnit(), llvm::TargetRegisterInfo::hasReservedSpillSlot(), hasSingleUse(), hasTiedUseOf(), hasUseAfterLoop(), hoistAndMergeSGPRInits(), if(), increaseSetPressure(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), insertCSRSaves(), InsertFPConstInst(), InsertFPImmInst(), InsertLDR_STR(), insertNoDuplicates(), insertPHI(), insertSEH(), InsertSPConstInst(), InsertSPImmInst(), llvm::MachineRegisterInfo::insertVRegByName(), llvm::WinEH::Instruction::Instruction(), interpretValues(), llvm::FunctionLoweringInfo::InvalidatePHILiveOutRegInfo(), llvm::invokeGlobalTargetPassConfigCallbacks(), llvm::X86II::is32ExtendedReg(), isACalleeSavedRegister(), llvm::TargetInstrInfo::isAddImmediate(), IsAGPROperand(), IsAliasOfSX(), llvm::CCState::isAllocated(), isAMXRegClass(), llvm::outliner::Candidate::isAnyUnavailableAcrossOrOutOfSeq(), llvm::X86II::isApxExtendedReg(), isARegister(), llvm::isARMLowRegister(), llvm::outliner::Candidate::isAvailableAcrossAndOutOfSeq(), llvm::outliner::Candidate::isAvailableInsideSeq(), llvm::TargetInstrInfo::isBasicBlockPrologue(), isCalleeSavedCR(), llvm::isCalleeSavedRegister(), isCallerPreservedOrConstPhysReg(), llvm::X86MachineFunctionInfo::isCandidateForPush2Pop2(), isCompressedReg(), isConstantCostlierToNegate(), IsCopyFromSGPR(), isCopyOf(), isCopyOfBundle(), isDblRegForSubInst(), isDead(), isDefBetween(), isDefBetween(), isDefinedOutside(), isDefLiveOut(), llvm::PPC::isDMRROWpRegister(), isEAXLiveIn(), isEvenReg(), llvm::rdf::TargetOperandInfo::isFixedReg(), isFPExtFromF16OrConst(), isFPR64(), isGPRShadowAligned(), isGuaranteedNotToBeUndefOrPoison(), llvm::AMDGPU::isHi16Reg(), llvm::SystemZ::isHighReg(), llvm::AllocationOrder::isHint(), isHReg(), isImplicitlyDef(), isIncrementOrDecrement(), isInefficientLEAReg(), llvm::AMDGPU::isInlineValue(), isIntRegForSubInst(), isInvariantStore(), isLaneMaskFromSameBlock(), llvm::PhiLoweringHelper::isLaneMaskReg(), llvm::LiveVariables::isLiveIn(), isLiveIntoMBB(), isLiveOut(), isMatchingOrAlias(), IsMovepDestinationReg(), IsMovepSrcRegister(), llvm::PPCRegisterInfo::isNonallocatableRegisterCalleeSave(), llvm::TargetRegisterInfo::isNonallocatableRegisterCalleeSave(), isNonZeroModBitWidthOrUndef(), isRegLiveIn(), isRegOtherThanSPAndFP(), IsSafeAndProfitableToMove(), isSafeToMove(), llvm::LoongArchMachineFunctionInfo::isSExt32Register(), llvm::AMDGPU::isSGPR(), llvm::SIRegisterInfo::isSGPRPhysReg(), llvm::PPCInstrInfo::isSignExtended(), isSignExtendedW(), isSignExtendedW(), IsSimplerBaseSCEVForTarget(), isSSA(), llvm::isSuperReg(), isTwoAddrUse(), llvm::TargetRegisterInfo::isUniformReg(), isValidRegDefOf(), isValidRegUseOf(), isValidSysReg(), isVCmpResult(), isVecReg(), isVectorOfTwoOrScalar(), llvm::SIRegisterInfo::isVectorRegister(), llvm::PPC::isVFRegister(), llvm::SIRegisterInfo::isVGPRPhysReg(), llvm::PPCRegisterInfo::isVirtualFrameRegister(), llvm::TargetRegisterInfo::isVirtualFrameRegister(), isVRegCompatibleReg(), llvm::PPC::isVRRegister(), llvm::SIMachineFunctionInfo::isWWMReg(), llvm::SIMachineFunctionInfo::isWWMReservedRegister(), llvm::X86II::isX86_64ExtendedReg(), llvm::X86II::isX86_64NonExtLowByteReg(), isX87Reg(), llvm::X86II::isXMMReg(), isYmmOrZmmReg(), llvm::X86II::isYMMReg(), llvm::PPCInstrInfo::isZeroExtended(), llvm::X86II::isZMMReg(), llvm::MachineInstr::killsRegister(), listContainsReg(), llvm::LiveIntervalCalc::LiveIntervalCalc(), llvm::BitTracker::lookup(), lookupSysReg(), llvm::MachineLoop::LoopInfoBase< MachineBasicBlock, MachineLoop >, LowerCallResults(), LowerCMP_SWAP(), lowerRISCVVMachineInstrToMCInst(), llvm::rdf::DataFlowGraph::makeRegRef(), mapArgRegToOffsetAIX(), llvm::SPIRV::mapBuiltinToOpcode(), llvm::yaml::MappingTraits< VirtualRegisterDefinition >::mapping(), mapRegToGPRIndex(), llvm::MIPatternMatch::CheckType::match(), llvm::MIPatternMatch::ConstantMatch< ConstT >::match(), llvm::MIPatternMatch::GCstAndRegMatch::match(), llvm::MIPatternMatch::GFCstAndRegMatch::match(), llvm::MIPatternMatch::GFCstOrSplatGFCstMatch::match(), llvm::MIPatternMatch::ICstOrSplatMatch< ConstT >::match(), llvm::MIPatternMatch::ImplicitDefMatch::match(), llvm::MIPatternMatch::OneNonDBGUse_match< SubPatternT >::match(), llvm::MIPatternMatch::OneUse_match< SubPatternT >::match(), llvm::MIPatternMatch::operand_type_match::match(), llvm::MIPatternMatch::SpecificConstantMatch::match(), llvm::MIPatternMatch::SpecificConstantOrSplatMatch::match(), llvm::MIPatternMatch::SpecificConstantSplatMatch::match(), llvm::MIPatternMatch::SpecificRegisterMatch::match(), llvm::MIPatternMatch::matchConstant(), llvm::MIPatternMatch::matchConstantSplat(), matchLoadAndBytePosition(), MatchRegisterAltName(), MatchRegisterAltName(), MatchRegisterName(), matchRegisterNameHelper(), matchUniformityAndLLT(), maybeRewriteToFallthrough(), mayBeSRetTailCallCompatible(), MaySpeculate(), llvm::AMDGPU::mc2PseudoReg(), llvm::MCRegAliasIterator::MCRegAliasIterator(), llvm::MCRegUnitIterator::MCRegUnitIterator(), llvm::MCRegUnitMaskIterator::MCRegUnitMaskIterator(), llvm::MCSubRegIndexIterator::MCSubRegIndexIterator(), llvm::MCSubRegIterator::MCSubRegIterator(), llvm::MCSuperRegIterator::MCSuperRegIterator(), llvm::MIPatternMatch::mi_match(), llvm::MachineInstr::modifiesRegister(), moveAndTeeForMultiUse(), moveForSingleUse(), MoveVPNOTBeforeFirstUser(), llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister(), needToReserveScavengingSpillSlots(), nextReg(), llvm::MachineRegisterInfo::noteNewVirtualRegister(), llvm::MCTargetAsmParser::omitRegisterFromClobberLists(), oneUseDominatesOtherUses(), onlyAllocateTileRegisters(), llvm::VGPRBlock2IndexFunctor::operator()(), llvm::VirtReg2IndexFunctor::operator()(), llvm::hlsl::rootsig::operator<<(), llvm::MCRegisterInfo::operator[](), optimizeToFixedRegisterForm(), parseCondBranch(), parseOperands(), parsePhysicalReg(), llvm::MCTargetAsmParser::parseRegister(), peekThroughBitcast(), performCopyPropagation(), performSink(), popRegsFromStack(), llvm::AMDGPUTargetLowering::PostISelFolding(), printAsmMRegister(), printAsmVRegister(), printCFIRegister(), llvm::AArch64AppleInstPrinter::printCustomAliasOperand(), llvm::AArch64InstPrinter::printCustomAliasOperand(), llvm::LoongArchInstPrinter::printCustomAliasOperand(), llvm::RISCVInstPrinter::printCustomAliasOperand(), llvm::SystemZInstPrinterCommon::printFormattedRegName(), llvm::MCInstPrinter::printInst(), llvm::AArch64InstPrinter::printPredicateAsCounter(), llvm::printReg(), printReg(), printRegClassOrBank(), printRegFlags(), printRegisterLocations(), printRegMIR(), llvm::CSKYInstPrinter::printSPAddr(), processBlockAddr(), processSwitchesConstants(), propagateSPIRVType(), llvm::Win64EH::Instruction::PushNonVol(), pushRegsToStack(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::readsVirtualRegister(), llvm::MachineRegisterInfo::reg_bundles(), llvm::MachineRegisterInfo::reg_instructions(), llvm::MachineRegisterInfo::reg_nodbg_bundles(), llvm::MachineRegisterInfo::reg_nodbg_instructions(), llvm::MachineRegisterInfo::reg_nodbg_operands(), llvm::MachineRegisterInfo::reg_operands(), llvm::MachineInstr::registerDefIsDead(), llvm::RegsForValue::RegsForValue(), regToString(), llvm::MCRegisterInfo::regunits(), rematerializeCheapDef(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::LiveIntervals::removeInterval(), llvm::LivePhysRegs::removeReg(), llvm::LiveRegUnits::removeReg(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), ReplaceCopyFromReg_128(), replaceFrameIndex(), replaceProxyReg(), reservePrivateMemoryRegs(), llvm::SIMachineFunctionInfo::reserveWWMRegister(), resetRegMaskBit(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), resultTests(), llvm::Ret_CSKY_ABIV2_SOFT_64(), llvm::Win64EH::Instruction::SaveNonVol(), llvm::GCNRPTarget::saveReg(), llvm::TargetRegisterInfo::saveScavengerRegister(), llvm::Win64EH::Instruction::SaveXMM(), scavengeFrameVirtualRegsInBlock(), selectDebugInstr(), llvm::BitTracker::RegisterCell::self(), llvm::SystemZMachineFunctionInfo::setADAVirtualRegister(), setAliasRegs(), llvm::WebAssemblyFunctionInfo::setBasePointerVreg(), llvm::sframe::FREInfo< E >::setBaseRegister(), llvm::RAGreedy::ExtraRegInfo::setCascade(), llvm::setDirectAddressInInstr(), llvm::SIMachineFunctionInfo::setFlag(), llvm::Win64EH::Instruction::SetFPReg(), llvm::WebAssemblyFunctionInfo::setFrameBaseVreg(), llvm::SIMachineFunctionInfo::setFrameOffsetReg(), llvm::sframe::FREInfo< E >::setFREInfo(), llvm::CSKYMachineFunctionInfo::setGlobalBaseReg(), llvm::M68kMachineFunctionInfo::setGlobalBaseReg(), llvm::SparcMachineFunctionInfo::setGlobalBaseReg(), llvm::VEMachineFunctionInfo::setGlobalBaseReg(), llvm::X86MachineFunctionInfo::setGlobalBaseReg(), llvm::SIMachineFunctionInfo::setLongBranchReservedReg(), llvm::AArch64FunctionInfo::setPredicateRegForFillSpill(), llvm::SIMachineFunctionInfo::setPrivateSegmentWaveByteOffset(), llvm::AArch64FunctionInfo::setPStateSMReg(), llvm::MCOperand::setReg(), llvm::setRegClassIfNull(), llvm::MachineRegisterInfo::setRegClassOrRegBank(), llvm::setRegClassType(), llvm::setRegClassType(), llvm::setRegClassType(), llvm::SPIRV::ModuleAnalysisInfo::setRegisterAlias(), setRegsToType(), llvm::SIMachineFunctionInfo::setScratchRSrcReg(), llvm::SIMachineFunctionInfo::setSGPRForEXECCopy(), llvm::AArch64FunctionInfo::setSMESaveBufferAddr(), llvm::AArch64FunctionInfo::setSRetReturnReg(), llvm::HexagonMachineFunctionInfo::setSRetReturnReg(), llvm::LanaiMachineFunctionInfo::setSRetReturnReg(), llvm::M68kMachineFunctionInfo::setSRetReturnReg(), llvm::MipsFunctionInfo::setSRetReturnReg(), llvm::MSP430MachineFunctionInfo::setSRetReturnReg(), llvm::SparcMachineFunctionInfo::setSRetReturnReg(), llvm::X86MachineFunctionInfo::setSRetReturnReg(), llvm::SIMachineFunctionInfo::setStackPtrOffsetReg(), llvm::RAGreedy::ExtraRegInfo::setStage(), llvm::RAGreedy::ExtraRegInfo::setStage(), llvm::WebAssemblyFunctionInfo::setVarargBufferVreg(), llvm::MachineFunction::setVariableDbgInfo(), llvm::RegAllocBase::shouldAllocateRegister(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), spillVGPRtoAGPR(), splitLowAndHighRegs(), llvm::AVRRegisterInfo::splitReg(), STATISTIC(), STATISTIC(), stripBitCast(), stripCopy(), stripValuesNotDefiningMask(), stripVRegCopies(), llvm::MCRegisterInfo::sub_and_superregs_inclusive(), llvm::MCRegisterInfo::subregs(), llvm::MCRegisterInfo::subregs_inclusive(), llvm::MCRegisterInfo::superregs(), llvm::MCRegisterInfo::superregs_inclusive(), suppressEGPRRegClass(), suppressEGPRRegClassInRegAndUses(), swapRegAndNonRegOperand(), toCallerWindow(), toCallerWindow(), toggleKills(), tryARMPackedUnwind(), llvm::MCTargetAsmParser::tryParseRegister(), tryScavengeRegister(), tryToFindRegisterToRename(), undefInvalidDbgValues(), llvm::TargetInstrInfo::unfoldMemoryOperand(), unstackifyVRegsUsedInSplitBB(), updateLiveness(), UpdateOperandRegClass(), updateOperandRegConstraints(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), UpdatePredRedefs(), llvm::TargetRegisterInfo::updateRegAllocHint(), llvm::MachineRegisterInfo::use_bundles(), llvm::MachineRegisterInfo::use_instructions(), llvm::MachineRegisterInfo::use_nodbg_bundles(), llvm::MachineRegisterInfo::use_nodbg_instructions(), llvm::MachineRegisterInfo::use_nodbg_operands(), llvm::MachineRegisterInfo::use_operands(), usedAsAddr(), usesExtendedRegister(), validateRootSignature(), VerifyLowRegs(), llvm::VirtRegOrUnit::VirtRegOrUnit(), llvm::VirtRegAuxInfo::weightCalcHelper(), widenScalarType(), llvm::jitlink::aarch64::writeMovRegImm64Seq(), llvm::jitlink::aarch32::writeRegister(), llvm::jitlink::aarch32::writeRegister(), llvm::ARMTargetStreamer::~ARMTargetStreamer(), llvm::MipsRegInfoRecord::~MipsRegInfoRecord(), llvm::R600SchedStrategy::~R600SchedStrategy(), llvm::ReachingDefInfo::~ReachingDefInfo(), and llvm::VirtRegAuxInfo::~VirtRegAuxInfo().

sinking

Machine code sinking

Definition at line 331 of file MachineSink.cpp.

SinkInstsIntoCycle

cl::opt< bool > SinkInstsIntoCycle("sink-insts-to-avoid-spills", cl::desc("Sink instructions into cycles to avoid " "register spills"), cl::init(false), cl::Hidden) ( "sink-insts-to-avoid-spills" , cl::desc("Sink instructions into cycles to avoid " "register spills") , cl::init(false) , cl::Hidden  )

static

SinkIntoCycleLimit

cl::opt< unsigned > SinkIntoCycleLimit("machine-sink-cycle-limit", cl::desc( "The maximum number of instructions considered for cycle sinking."), cl::init(50), cl::Hidden) ( "machine-sink-cycle-limit" , cl::desc( "The maximum number of instructions considered for cycle sinking.") , cl::init(50) , cl::Hidden  )

static

SinkLoadBlocksThreshold

cl::opt< unsigned > SinkLoadBlocksThreshold("machine-sink-load-blocks-threshold", cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold."), cl::init(20), cl::Hidden) ( "machine-sink-load-blocks-threshold" , cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold.") , cl::init(20) , cl::Hidden  )

static

SinkLoadInstsPerBlockThreshold

cl::opt< unsigned > SinkLoadInstsPerBlockThreshold("machine-sink-load-instrs-threshold", cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold."), cl::init(2000), cl::Hidden) ( "machine-sink-load-instrs-threshold" , cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold.") , cl::init(2000) , cl::Hidden  )

static

SplitEdgeProbabilityThreshold

cl::opt< unsigned > SplitEdgeProbabilityThreshold("machine-sink-split-probability-threshold", cl::desc( "Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden) ( "machine-sink-split-probability-threshold" , cl::desc( "Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge") , cl::init(40) , cl::Hidden  )

static

SplitEdges

cl::opt< bool > SplitEdges("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden) ( "machine-sink-split" , cl::desc("Split critical edges during machine sinking") , cl::init(true) , cl::Hidden  )

static

TRI

Register const TargetRegisterInfo* TRI

Initial value:

{
  LiveRegUnits LiveInRegUnits(*TRI)

Definition at line 2118 of file MachineSink.cpp.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), llvm::AArch64Subtarget::AArch64Subtarget(), llvm::DwarfCompileUnit::addAddress(), llvm::DwarfCompileUnit::addComplexAddress(), llvm::SIMachineFunctionInfo::addDispatchID(), llvm::SIMachineFunctionInfo::addDispatchPtr(), llvm::ARMBaseInstrInfo::AddDReg(), addExclusiveRegPair(), llvm::SIMachineFunctionInfo::addFlatScratchInit(), llvm::SIMachineFunctionInfo::addImplicitBufferPtr(), llvm::SIMachineFunctionInfo::addKernargSegmentPtr(), llvm::addLiveIns(), llvm::DwarfExpression::addMachineReg(), llvm::DwarfExpression::addMachineRegExpression(), llvm::SITargetLowering::AddMemOpInit(), llvm::SIMachineFunctionInfo::addPreloadedKernArg(), llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer(), llvm::SIMachineFunctionInfo::addPrivateSegmentSize(), llvm::SIMachineFunctionInfo::addQueuePtr(), addRegAndItsAliases(), addRegsToSet(), addRegUnits(), llvm::PPCFrameLowering::addScavengingSpillSlot(), AddSubReg(), AdjustBaseAndOffset(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::GCNSubtarget::adjustSchedDependency(), allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateLDSKernelId(), llvm::SITargetLowering::allocatePreloadKernArgSGPRs(), llvm::SITargetLowering::allocateSpecialEntryInputVGPRs(), llvm::SITargetLowering::allocateSpecialInputSGPRs(), llvm::SITargetLowering::allocateSpecialInputVGPRs(), llvm::SITargetLowering::allocateSpecialInputVGPRsFixed(), llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::LiveRangeEdit::allUsesAvailableAt(), llvm::X86InstrInfo::analyzeBranchPredicate(), analyzeCandidate(), analyzeCompressibleUses(), llvm::AArch64InstrInfo::analyzeLoopForPipelining(), llvm::AnalyzePhysRegInBundle(), llvm::AMDGPUResourceUsageAnalysisImpl::analyzeResourceUsage(), llvm::AnalyzeVirtRegLanesInBundle(), AnyAliasLiveIn(), appendScalableVectorExpression(), llvm::HexagonSubtarget::CallMutation::apply(), applyBitsNotInRegMaskToRegUnitsMask(), llvm::AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable(), areCFlagsAccessedBetweenInstrs(), areCombinableOperations(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(), llvm::ARCFrameLowering::assignCalleeSavedSpillSlots(), llvm::ARMFrameLowering::assignCalleeSavedSpillSlots(), llvm::CSKYFrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::PPCFrameLowering::assignCalleeSavedSpillSlots(), llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), llvm::SIFrameLowering::assignCalleeSavedSpillSlots(), llvm::SIFrameLowering::assignCalleeSavedSpillSlots(), llvm::SystemZELFFrameLowering::assignCalleeSavedSpillSlots(), llvm::SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots(), llvm::TargetFrameLowering::assignCalleeSavedSpillSlots(), llvm::TargetFrameLowering::assignCalleeSavedSpillSlots(), assignedRegPartiallyOverlaps(), assignSlotsUsingVGPRBlocks(), llvm::CodeViewDebug::beginFunctionImpl(), llvm::BitMaskClassIterator::BitMaskClassIterator(), blockPrologueInterferes(), llvm::BPFRegisterBankInfo::BPFRegisterBankInfo(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::TargetInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), buildAnyextOrCopy(), buildCallOperands(), llvm::X86InstrInfo::buildClearRegister(), buildEpilogRestore(), buildGitPtr(), buildPrologSpill(), buildScratchExecCopy(), llvm::GCNDownwardRPTracker::bumpDownwardPressure(), llvm::LiveIntervalCalc::calculate(), llvm::calculateDbgEntityHistory(), llvm::LiveRangeEdit::calculateRegClassAndHint(), canBeFeederToNewValueJump(), canClobberPhysRegDefs(), canClobberReachingPhysRegUse(), canCmpInstrBeRemoved(), canCompareBeNewValueJump(), canInstrSubstituteCmpInstr(), canRenameMOP(), canRenameUntilSecondLoad(), canRenameUpToDef(), llvm::AArch64FrameLowering::canUseAsPrologue(), CC_X86_64_VectorCall(), llvm::AArch64TargetLowering::changeStreamingMode(), checkAndUpdateCCRKill(), checkAndUpdateCPSRKill(), checkAndUpdateEFLAGSKill(), CheckForLiveRegDef(), CheckForLiveRegDef(), CheckForPhysRegDependency(), llvm::SITargetLowering::checkForPhysRegDependency(), llvm::TargetLowering::checkForPhysRegDependency(), checkRB(), llvm::checkVOPDRegConstraints(), clearKillFlags(), cloneInstr(), llvm::RegisterOperands::collect(), collectRegDefs(), llvm::TargetInstrInfo::commuteInstructionImpl(), computeCalleeSaveRegisterPairs(), computeFPBPAlignmentGap(), computeIndirectRegAndOffset(), computeIndirectRegIndex(), llvm::computeLiveIns(), computeLiveOuts(), llvm::TargetSchedModel::computeOutputLatency(), llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::LiveInterval::computeSubRangeUndefs(), llvm::MachineInstrBuilder::constrainAllUses(), llvm::constrainOperandRegClass(), llvm::constrainOperandRegClass(), llvm::constrainSelectedInstRegOperands(), consumesDstSelForwardingOperand(), containsReg(), convertArgumentInfo(), convertCallSiteObjects(), convertEntryValueObjects(), convertMRI(), convertStackObjects(), llvm::AArch64InstrInfo::copyGPRRegTuple(), llvm::VirtRegAuxInfo::copyHint(), llvm::AArch64InstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::AVRInstrInfo::copyPhysReg(), llvm::PPCInstrInfo::copyPhysReg(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::SparcInstrInfo::copyPhysReg(), llvm::VEInstrInfo::copyPhysReg(), llvm::X86InstrInfo::copyPhysReg(), llvm::AArch64InstrInfo::copyPhysRegTuple(), llvm::RISCVInstrInfo::copyPhysRegVector(), copyPhysSubRegs(), llvm::AllocationOrder::create(), llvm::M68kTargetLowering::create(), llvm::createBURRListDAGScheduler(), llvm::createCFAOffset(), llvm::createCopyConstrainDAGMutation(), llvm::createDefCFA(), createDefCFAExpression(), createDefCFAExpression(), createDefCFAOffset(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::createLoadClusterDAGMutation(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::ARMBaseInstrInfo::createMIROperandComment(), llvm::RISCVInstrInfo::createMIROperandComment(), llvm::TargetInstrInfo::createMIROperandComment(), createPostIncLoadStore(), llvm::createRISCVVectorMaskDAGMutation(), createSiFivePreemptibleInterruptFrameEntries(), llvm::createSourceListDAGScheduler(), llvm::createStoreClusterDAGMutation(), createTuple(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), llvm::MachineInstr::definesRegister(), llvm::MipsInstrInfo::describeLoadedValue(), llvm::TargetInstrInfo::describeLoadedValue(), llvm::X86InstrInfo::describeLoadedValue(), describeMOVrrLoadedValue(), describeORRLoadedValue(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::CSKYFrameLowering::determineCalleeSaves(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::RISCVFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SystemZELFFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::MachineRegisterInfo::disableCalleeSavedRegister(), llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay(), doesModifyCalleeSavedReg(), llvm::LoopCarriedEdges::dump(), llvm::PressureDiff::dump(), llvm::RegisterBank::dump(), llvm::RegisterPressure::dump(), llvm::SDep::dump(), dump_registers(), llvm::TargetRegisterInfo::dumpReg(), llvm::dumpRegSetPressure(), llvm::VERegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::SIFrameLowering::emitCSRSpillRestores(), llvm::SIFrameLowering::emitCSRSpillStores(), llvm::DwarfDebug::emitDebugLocValue(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::SystemZTargetLowering::emitEHSjLjSetJmp(), llvm::VETargetLowering::emitEHSjLjSetJmp(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::AArch64TargetLowering::EmitEntryPStateSM(), llvm::SIFrameLowering::emitEpilogue(), emitFrameOffsetAdj(), llvm::AArch64TargetLowering::EmitGetSMESaveSize(), emitIndirectDst(), emitIndirectSrc(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::MachineRegisterInfo::EmitLiveInCopies(), emitLoadM0FromVGPRLoop(), emitLoadScalarOpsFromVGPRLoop(), llvm::CSKYFrameLowering::emitPrologue(), llvm::SIFrameLowering::emitPrologue(), emitPseudoVMSKCOND(), emitSCSPrologue(), emitVFROUND_NOEXCEPT_MASK(), emitVGPRBlockComment(), estimateRSStackSizeLimit(), llvm::MipsFrameLowering::estimateStackSize(), llvm::examineCFlagsUse(), llvm::execMayBeModifiedBeforeAnyUse(), llvm::execMayBeModifiedBeforeUse(), llvm::GIMatchTableExecutor::executeMatchTable(), Expand64BitScalarArithmetic(), expandFillPPRFromZPRSlotPseudo(), llvm::M68kInstrInfo::ExpandMOVSZX_RR(), llvm::M68kInstrInfo::ExpandMOVX_RR(), expandNOVLXLoad(), expandNOVLXStore(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::VEInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), expandSMEPPRToZPRSpillPseudos(), expandSpillPPRToZPRSlotPseudo(), expandXorFP(), llvm::finalizeBundle(), llvm::PPCInstrInfo::finalizeInsInstrs(), llvm::SITargetLowering::finalizeLowering(), FindAllMemoryUses(), FindAllMemoryUses(), llvm::findCMPToFoldIntoCBZ(), findDeadCallerSavedReg(), findHoistingInsertPosAndDeps(), findIncDecAfter(), findLoopIncrementValue(), findNextInsertLocation(), findRedundantFlagInstr(), llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperand(), llvm::MachineInstr::findRegisterUseOperand(), llvm::MachineInstr::findRegisterUseOperandIdx(), findRenameRegForSameLdStRegPair(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), findSurvivorBackwards(), findUseBetween(), findUseBetween(), findVCMPToFoldIntoVPST(), firstCommonClass(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), forAllMIsUntilDef(), foreachUnit(), llvm::MipsInstrInfo::genInstrWithNewOpc(), llvm::AArch64InstrInfo::getAddrModeFromMemoryOp(), llvm::TargetInstrInfo::getAddrModeFromMemoryOp(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), llvm::MachineBasicBlock::getBeginClobberMask(), getBundledDefMI(), getBundledUseMI(), llvm::TargetFrameLowering::getCalleeSaves(), getCommonMinimalPhysRegClass(), getCopyRegClasses(), getCorrespondingDRegAndLane(), GetCostForDef(), llvm::PPCInstrInfo::getDefMIPostRA(), GetDSubRegs(), getDwarfRegNum(), llvm::MachineBasicBlock::getEndClobberMask(), llvm::PPCInstrInfo::getFMAPatterns(), getGatherLanePattern(), getImplicitSPRUseForDPRUse(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), getInstReadLaneMask(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::AVRRegisterInfo::getLargestLegalSuperClass(), getLegalRegBank(), llvm::getLivePhysRegsUpTo(), getLoadParameters(), getMaskForArgs(), getMax32BitSubRegister(), getMaxCalleeSavedReg(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), llvm::AArch64InstrInfo::getMemOperandsWithOffsetWidth(), llvm::HexagonInstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandsWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandsWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandsWithOffsetWidth(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth(), llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(), llvm::TargetInstrInfo::getMemOperandWithOffset(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), getMemsetStores(), getMinimalPhysRegClass(), llvm::RegisterBankInfo::getMinimalPhysRegClass(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), getNumAllocatableRegsForConstraints(), llvm::MipsTargetLowering::getOpndList(), llvm::ARMBaseInstrInfo::getOutliningCandidateInfo(), llvm::ARMBaseInstrInfo::getOutliningTypeImpl(), llvm::RISCVInstrInfo::getOutliningTypeImpl(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::TargetInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::MachineFrameInfo::getPristineRegs(), llvm::SIRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::getRegBankFromConstraints(), llvm::SIInstrInfo::getRegClass(), llvm::TargetInstrInfo::getRegClass(), llvm::X86InstrInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), getRegClassesForCopy(), llvm::SITargetLowering::getRegClassFor(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::AVRTargetLowering::getRegForInlineAsmConstraint(), llvm::BPFTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::MSP430TargetLowering::getRegForInlineAsmConstraint(), llvm::NVPTXTargetLowering::getRegForInlineAsmConstraint(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::SparcTargetLowering::getRegForInlineAsmConstraint(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::VETargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::XtensaTargetLowering::getRegForInlineAsmConstraint(), llvm::SparcTargetLowering::getRegisterByName(), getRegisterName(), getRegistersForValue(), getRegistersForValue(), getRegisterSize(), getRegOpRC(), getRegTy(), llvm::WebAssemblyAsmPrinter::getRegType(), getRVVBaseRegister(), llvm::SIMachineFunctionInfo::getScavengeFI(), getSingleLiveInSuccBB(), getSingleLiveInSuccBB(), llvm::RegisterBankInfo::getSizeInBits(), llvm::TargetInstrInfo::getStackSlotRange(), getSubRegForClass(), getTag(), llvm::TargetInstrInfo::getUndefRegClearance(), llvm::X86InstrInfo::getUndefRegClearance(), getVGPRSpillLaneOrTempRegister(), llvm::PerTargetMIParsingState::getVRegFlagValue(), llvm::GIMatchTableExecutor::GIMatchTableExecutor(), llvm::LoongArchFrameLowering::hasBP(), llvm::MipsFrameLowering::hasBP(), llvm::RISCVFrameLowering::hasBP(), llvm::VEFrameLowering::hasBP(), llvm::MipsFrameLowering::hasFPImpl(), llvm::hash_value(), hasLoopCarriedMemDep(), hasRAWHazard(), hasWriteToReadDep(), hoistAndMergeSGPRInits(), llvm::GCNRegPressure::inc(), llvm::LiveRegSet::init(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), INITIALIZE_PASS(), initLiveUnits(), initRegisterMaskIds(), llvm::VEInstrInfo::insertBranch(), llvm::AArch64TargetLowering::insertCopiesSplitCSR(), llvm::SITargetLowering::insertCopiesSplitCSR(), insertCSRRestores(), insertCSRRestores(), insertCSRSaves(), insertCSRSaves(), llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::RISCVInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::X86InstrInfo::insertSelect(), InstReorderLimit(), llvm::rdf::CopyPropagation::interpretAsCopy(), interpretValues(), invalidateRegisterPairing(), invalidateWindowsRegisterPairing(), isACalleeSavedRegister(), isAGPRCopy(), isAnyArgRegReserved(), llvm::outliner::Candidate::isAnyUnavailableAcrossOrOutOfSeq(), llvm::X86RegisterInfo::isArgumentRegister(), llvm::outliner::Candidate::isAvailableAcrossAndOutOfSeq(), llvm::outliner::Candidate::isAvailableInsideSeq(), isCallerPreservedOrConstPhysReg(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::MachineRegisterInfo::isConstantPhysReg(), isConvertibleToVMV_V_V(), isCopyFeedingInvariantStore(), IsCopyFromSGPR(), isCrossCopy(), llvm::isCycleInvariant(), isDefBetween(), isEFLAGSLive(), llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isFIPlusImmOrVGPR(), llvm::X86RegisterInfo::isFixedRegister(), isFPBPAccess(), llvm::DwarfExpression::isFrameRegister(), llvm::MachineOperand::isIdenticalTo(), llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence(), isInvariantStore(), isLdStSafeToCluster(), llvm::RISCVInstrInfo::isLdStSafeToPair(), llvm::TargetLoweringBase::isLegalRC(), isLiveIntoMBB(), llvm::MachineLoop::isLoopInvariant(), isLRAvailable(), isMIModifiesReg(), isMIReadsReg(), isNonFoldablePartialRegisterLoad(), isNopCopy(), llvm::isNZCVTouchedInInstructionRange(), llvm::isOfRegClass(), IsOperandAMemoryOperand(), llvm::MachineRegisterInfo::isPhysRegModified(), llvm::MachineRegisterInfo::isPhysRegUsed(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), isRegOtherThanSPAndFP(), llvm::MachineRegisterInfo::isReservedRegUnit(), IsSafeAndProfitableToMove(), llvm::GCNRPTarget::isSaveBeneficial(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), llvm::AMDGPU::isSGPR(), isSGPRToVGPRCopy(), isSubRegOf(), isSVERegOp(), isTupleInsertInstr(), isUnsafeToMoveAcross(), llvm::HexagonInstrInfo::isValidOffset(), isValidRegDefOf(), isValidRegUseOf(), isVCmpXWritesExec(), isVGPRToSGPRCopy(), isVRegCompatibleReg(), llvm::MachineInstr::killsRegister(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), loadM0FromVGPR(), loadMBUFScalarOperandsFromVGPR(), llvm::Mips16InstrInfo::loadRegFromStack(), llvm::MipsInstrInfo::loadRegFromStack(), llvm::MipsSEInstrInfo::loadRegFromStack(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARCInstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::AVRInstrInfo::loadRegFromStackSlot(), llvm::BPFInstrInfo::loadRegFromStackSlot(), llvm::CSKYInstrInfo::loadRegFromStackSlot(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), llvm::LoongArchInstrInfo::loadRegFromStackSlot(), llvm::M68kInstrInfo::loadRegFromStackSlot(), llvm::MipsInstrInfo::loadRegFromStackSlot(), llvm::MSP430InstrInfo::loadRegFromStackSlot(), llvm::PPCInstrInfo::loadRegFromStackSlot(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SparcInstrInfo::loadRegFromStackSlot(), llvm::SystemZInstrInfo::loadRegFromStackSlot(), llvm::TargetInstrInfo::loadRegFromStackSlot(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::VEInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::XCoreInstrInfo::loadRegFromStackSlot(), llvm::XtensaInstrInfo::loadRegFromStackSlot(), llvm::PPCInstrInfo::loadRegFromStackSlotNoUpd(), loadRegPairFromStackSlot(), lookupCandidateBaseReg(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::M68kCallLowering::lowerCall(), llvm::MipsCallLowering::lowerCall(), llvm::RISCVCallLowering::lowerCall(), llvm::X86CallLowering::lowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::TargetInstrInfo::lowerCopy(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::SITargetLowering::LowerReturn(), lowerRISCVVMachineInstrToMCInst(), llvm::RISCVRegisterInfo::lowerSegmentSpillReload(), llvm::AMDGPUMCInstLower::lowerT16D16Helper(), llvm::AMDGPUCallLowering::lowerTailCall(), lowerWaveReduce(), llvm::M68kRegisterBankInfo::M68kRegisterBankInfo(), llvm::GenericUniformityAnalysisImpl< ContextT >::markDefsDivergent(), llvm::MipsRegInfoRecord::MipsRegInfoRecord(), llvm::MipsRegisterBankInfo::MipsRegisterBankInfo(), llvm::MachineInstr::modifiesRegister(), onlyAllocateTileRegisters(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::TargetLowering::ParseConstraints(), llvm::SITargetLowering::passSpecialInputs(), patchMatchingInput(), performCopyPropagation(), llvm::PPCRegisterBankInfo::PPCRegisterBankInfo(), llvm::TargetInstrInfo::preservesZeroValueInReg(), llvm::X86InstrInfo::preservesZeroValueInReg(), llvm::ArgDescriptor::print(), llvm::LiveIntervalUnion::print(), llvm::MachineBasicBlock::print(), llvm::MachineFunction::print(), llvm::MachineInstr::print(), llvm::MachineOperand::print(), llvm::MachineOperand::print(), llvm::MachineOperand::print(), llvm::PhysicalRegisterUsageInfo::print(), llvm::print(), llvm::RegisterBank::print(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), printCFI(), printCFIRegister(), printCustomRegMask(), printMBB(), printMI(), printMIOperand(), PrintNodeInfo(), llvm::ARMAsmPrinter::printOperand(), llvm::printReg(), llvm::printRegClassOrBank(), printRegClassOrBank(), printRegFlags(), printRegMIR(), llvm::printRegUnit(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::MachineOperand::printSubRegIdx(), llvm::printVRegOrUnit(), llvm::AArch64FrameLowering::processFunctionBeforeFrameFinalized(), llvm::PPCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIFrameLowering::processFunctionBeforeFrameIndicesReplaced(), llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(), llvm::PSetIterator::PSetIterator(), readsLaneSubset(), llvm::MachineInstr::readsRegister(), llvm::TargetInstrInfo::reassociateOps(), llvm::recomputeLivenessFlags(), llvm::MachineRegisterInfo::recomputeRegClass(), reduceDbgValsForwardScan(), llvm::LiveInterval::refineSubRanges(), llvm::registerDefinedBetween(), llvm::MachineInstr::registerDefIsDead(), regMaskFromTemplate(), regToString(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::TargetInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), replaceFrameIndex(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::reportMismatch(), llvm::R600InstrInfo::reserveIndirectRegisters(), reservePrivateMemoryRegs(), llvm::MachineRegisterInfo::reserveReg(), llvm::GCNUpwardRPTracker::reset(), llvm::AArch64FrameLowering::resetCFIToInitialState(), resetRegMaskBit(), llvm::TargetFrameLowering::restoreCalleeSavedRegister(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::ARCFrameLowering::restoreCalleeSavedRegisters(), llvm::ARMFrameLowering::restoreCalleeSavedRegisters(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::CSKYFrameLowering::restoreCalleeSavedRegisters(), llvm::HexagonFrameLowering::restoreCalleeSavedRegisters(), llvm::Mips16FrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), llvm::SIFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters(), llvm::TargetFrameLowering::restoreCalleeSavedRegisters(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::rewriteT2FrameIndex(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::rdf::CopyPropagation::run(), RemoveLoadsIntoFakeUses::run(), llvm::GCNRegPressurePrinter::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineFunction::salvageCopySSAImpl(), scavengeFrameVirtualRegsInBlock(), scavengeVReg(), llvm::RISCVDAGToDAGISel::Select(), selectCopy(), selectCopy(), selectCopy(), llvm::InstructionSelect::selectMachineFunction(), selectMergeValues(), selectUnmergeValues(), llvm::FunctionLoweringInfo::set(), setAliasRegs(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::MIRParserImpl::setupRegisterInfo(), llvm::SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(), llvm::PPCInstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldReduceRegisterPressure(), shouldUseFrameHelper(), llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(), llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(), SinkingPreventsImplicitNullCheck(), llvm::SITargetLowering::SITargetLowering(), llvm::TargetFrameLowering::spillCalleeSavedRegister(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::ARCFrameLowering::spillCalleeSavedRegisters(), llvm::ARMFrameLowering::spillCalleeSavedRegisters(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::CSKYFrameLowering::spillCalleeSavedRegisters(), llvm::HexagonFrameLowering::spillCalleeSavedRegisters(), llvm::LoongArchFrameLowering::spillCalleeSavedRegisters(), llvm::Mips16FrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), llvm::SIFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZELFFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::spillCalleeSavedRegisters(), llvm::TargetFrameLowering::spillCalleeSavedRegisters(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), spillVGPRtoAGPR(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::stableHashValue(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), STATISTIC(), storeRegPairToStackSlot(), llvm::Mips16InstrInfo::storeRegToStack(), llvm::MipsInstrInfo::storeRegToStack(), llvm::MipsSEInstrInfo::storeRegToStack(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARCInstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::AVRInstrInfo::storeRegToStackSlot(), llvm::BPFInstrInfo::storeRegToStackSlot(), llvm::CSKYInstrInfo::storeRegToStackSlot(), llvm::HexagonInstrInfo::storeRegToStackSlot(), llvm::LoongArchInstrInfo::storeRegToStackSlot(), llvm::M68kInstrInfo::storeRegToStackSlot(), llvm::MipsInstrInfo::storeRegToStackSlot(), llvm::MSP430InstrInfo::storeRegToStackSlot(), llvm::PPCInstrInfo::storeRegToStackSlot(), llvm::RISCVInstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::SparcInstrInfo::storeRegToStackSlot(), llvm::SystemZInstrInfo::storeRegToStackSlot(), llvm::TargetInstrInfo::storeRegToStackSlot(), llvm::Thumb1InstrInfo::storeRegToStackSlot(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), llvm::VEInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), llvm::XCoreInstrInfo::storeRegToStackSlot(), llvm::XtensaInstrInfo::storeRegToStackSlot(), llvm::PPCInstrInfo::storeRegToStackSlotNoUpd(), stripValuesNotDefiningMask(), llvm::MachineOperand::substPhysReg(), llvm::MachineOperand::substVirtReg(), llvm::SuperRegClassIterator::SuperRegClassIterator(), TrackDefUses(), transferImplicitOperands(), tryChangeVGPRtoSGPRinCopy(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::tryPressure(), tryToFindRegisterToRename(), tryToGetTargetInfo(), tryToGetTargetInfo(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::X86InstrInfo::unfoldMemoryOperand(), unsupportedBinOp(), updateDefinedRegisters(), updateLiveIn(), UpdateOperandRegClass(), updateOperandRegConstraints(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), UpdatePredRedefs(), llvm::RegisterBank::verify(), llvm::RegisterBankInfo::verify(), llvm::VirtRegAuxInfo::weightCalcHelper(), llvm::X86RegisterBankInfo::X86RegisterBankInfo(), llvm::SIFrameLowering::~SIFrameLowering(), and llvm::VirtRegAuxInfo::~VirtRegAuxInfo().

UseBlockFreqInfo

cl::opt< bool > UseBlockFreqInfo("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden) ( "machine-sink-bfi" , cl::desc("Use block frequency info to find successors to sink") , cl::init(true) , cl::Hidden  )

static

Referenced by llvm::MachineSinkingPass::run().