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RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/Support/Endian.h"
27
28using namespace llvm;
29using namespace llvm::MCD;
30
31#define DEBUG_TYPE "riscv-disassembler"
32
34
35namespace {
36class RISCVDisassembler : public MCDisassembler {
37 std::unique_ptr<MCInstrInfo const> const MCII;
38
39public:
40 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCInstrInfo const *MCII)
42 : MCDisassembler(STI, Ctx), MCII(MCII) {}
43
44 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
45 ArrayRef<uint8_t> Bytes, uint64_t Address,
46 raw_ostream &CStream) const override;
47
48private:
49 DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
50 ArrayRef<uint8_t> Bytes, uint64_t Address,
51 raw_ostream &CStream) const;
52
53 DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
54 ArrayRef<uint8_t> Bytes, uint64_t Address,
55 raw_ostream &CStream) const;
56 DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const;
59};
60} // end anonymous namespace
61
63 const MCSubtargetInfo &STI,
64 MCContext &Ctx) {
65 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
66}
67
80
82 uint64_t Address,
83 const MCDisassembler *Decoder) {
84 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
85
86 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
88
89 MCRegister Reg = RISCV::X0 + RegNo;
92}
93
95 uint64_t Address,
96 const MCDisassembler *Decoder) {
97 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
98
99 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
101
102 MCRegister Reg = RISCV::X0_H + RegNo;
105}
106
108 uint64_t Address,
109 const MCDisassembler *Decoder) {
110 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
111
112 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
114
115 MCRegister Reg = RISCV::X0_W + RegNo;
118}
119
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 MCRegister Reg = RISCV::X0 + RegNo;
124 if (Reg != RISCV::X1 && Reg != RISCV::X5)
126
129}
130
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 32)
136
137 MCRegister Reg = RISCV::F0_H + RegNo;
140}
141
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 32)
147
148 MCRegister Reg = RISCV::F0_F + RegNo;
151}
152
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 8) {
158 }
159 MCRegister Reg = RISCV::F8_F + RegNo;
162}
163
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo >= 32)
169
170 MCRegister Reg = RISCV::F0_D + RegNo;
173}
174
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo >= 8) {
180 }
181 MCRegister Reg = RISCV::F8_D + RegNo;
184}
185
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo >= 32)
191
192 MCRegister Reg = RISCV::F0_Q + RegNo;
195}
196
198 const MCDisassembler *Decoder) {
199 Inst.addOperand(MCOperand::createReg(RISCV::X1));
201}
202
204 const MCDisassembler *Decoder) {
205 Inst.addOperand(MCOperand::createReg(RISCV::X2));
207}
208
210 uint32_t Address,
211 const MCDisassembler *Decoder) {
212 assert(RegNo == 2);
213 Inst.addOperand(MCOperand::createReg(RISCV::X2));
215}
216
218 const MCDisassembler *Decoder) {
219 Inst.addOperand(MCOperand::createReg(RISCV::X5));
221}
222
224 uint64_t Address,
225 const MCDisassembler *Decoder) {
226 if (RegNo == 0)
228
229 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
230}
231
233 uint32_t Address,
234 const MCDisassembler *Decoder) {
235 if (RegNo == 2)
237
238 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
239}
240
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
244 if (RegNo == 31) {
246 }
247
248 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
249}
250
252 uint64_t Address,
253 const MCDisassembler *Decoder) {
254 if (RegNo >= 8)
256
257 MCRegister Reg = RISCV::X8 + RegNo;
260}
261
263 uint64_t Address,
264 const MCDisassembler *Decoder) {
265 if (RegNo >= 32 || RegNo % 2)
267
268 const RISCVDisassembler *Dis =
269 static_cast<const RISCVDisassembler *>(Decoder);
270 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
272 RISCV::X0 + RegNo, RISCV::sub_gpr_even,
273 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
276}
277
278static DecodeStatus
280 const MCDisassembler *Decoder) {
281 if (RegNo == 0)
283
284 return DecodeGPRPairRegisterClass(Inst, RegNo, Address, Decoder);
285}
286
288 uint64_t Address,
289 const MCDisassembler *Decoder) {
290 if (RegNo >= 8 || RegNo % 2)
292
293 const RISCVDisassembler *Dis =
294 static_cast<const RISCVDisassembler *>(Decoder);
295 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
297 RISCV::X8 + RegNo, RISCV::sub_gpr_even,
298 &RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID]);
301}
302
304 uint64_t Address,
305 const void *Decoder) {
306 if (RegNo >= 8)
308
309 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
312}
313
315 uint64_t Address,
316 const MCDisassembler *Decoder) {
317 if (RegNo >= 32)
319
320 MCRegister Reg = RISCV::V0 + RegNo;
323}
324
326 uint64_t Address,
327 const MCDisassembler *Decoder) {
328 if (RegNo >= 32 || RegNo % 2)
330
331 const RISCVDisassembler *Dis =
332 static_cast<const RISCVDisassembler *>(Decoder);
333 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
335 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
336 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
337
340}
341
343 uint64_t Address,
344 const MCDisassembler *Decoder) {
345 if (RegNo >= 32 || RegNo % 4)
347
348 const RISCVDisassembler *Dis =
349 static_cast<const RISCVDisassembler *>(Decoder);
350 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
352 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
353 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
354
357}
358
360 uint64_t Address,
361 const MCDisassembler *Decoder) {
362 if (RegNo >= 32 || RegNo % 8)
364
365 const RISCVDisassembler *Dis =
366 static_cast<const RISCVDisassembler *>(Decoder);
367 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
369 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
370 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
371
374}
375
377 uint64_t Address,
378 const MCDisassembler *Decoder) {
379 if (RegNo)
381
382 Inst.addOperand(MCOperand::createReg(RISCV::V0));
384}
385
387 uint64_t Address,
388 const MCDisassembler *Decoder) {
389 if (RegNo > 15)
391
392 MCRegister Reg = RISCV::T0 + RegNo;
395}
396
398 uint64_t Address,
399 const MCDisassembler *Decoder) {
400 if (RegNo > 15 || RegNo % 2)
402
403 MCRegister Reg = RISCV::T0 + RegNo;
406}
407
409 uint64_t Address,
410 const MCDisassembler *Decoder) {
411 if (RegNo > 15 || RegNo % 4)
413
414 MCRegister Reg = RISCV::T0 + RegNo;
417}
418
420 uint64_t Address,
421 const MCDisassembler *Decoder) {
422 if (RegNo >= 2)
424
425 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
426
429}
430
432 const MCDisassembler *Decoder) {
435}
436
438 const MCDisassembler *Decoder) {
441}
442
443template <unsigned N>
445 int64_t Address,
446 const MCDisassembler *Decoder) {
447 assert(isUInt<N>(Imm) && "Invalid immediate");
450}
451
452template <unsigned Width, unsigned LowerBound>
454 int64_t Address,
455 const MCDisassembler *Decoder) {
456 assert(isUInt<Width>(Imm) && "Invalid immediate");
457
458 if (Imm < LowerBound)
460
463}
464
465template <unsigned Width, unsigned LowerBound>
467 int64_t Address,
468 const MCDisassembler *Decoder) {
469 assert(isUInt<Width>(Imm) && "Invalid immediate");
470
471 if ((Imm + 1) < LowerBound)
473
474 Inst.addOperand(MCOperand::createImm(Imm + 1));
476}
477
479 int64_t Address,
480 const MCDisassembler *Decoder) {
481 assert(isUInt<3>(Imm) && "Invalid Slist immediate");
482 const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
483 Inst.addOperand(MCOperand::createImm(Slist[Imm]));
485}
486
488 int64_t Address,
489 const MCDisassembler *Decoder) {
490 assert(isUInt<6>(Imm) && "Invalid immediate");
491
492 if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
493 !isUInt<5>(Imm))
495
498}
499
500template <unsigned N>
502 int64_t Address,
503 const MCDisassembler *Decoder) {
504 if (Imm == 0)
506 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
507}
508
509static DecodeStatus
511 const MCDisassembler *Decoder) {
512 if (Imm == 0)
514 return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
515}
516
517template <unsigned N>
519 int64_t Address,
520 const MCDisassembler *Decoder) {
521 assert(isUInt<N>(Imm) && "Invalid immediate");
522 Inst.addOperand(MCOperand::createImm(Imm + 1));
524}
525
527 int64_t Address,
528 const MCDisassembler *Decoder) {
529 assert(isUInt<5>(Imm) && "Invalid immediate");
530 Inst.addOperand(MCOperand::createImm(Imm ? Imm : -1LL));
532}
533
534template <unsigned N>
536 int64_t Address,
537 const MCDisassembler *Decoder) {
538 assert(isUInt<N>(Imm) && "Invalid immediate");
539 // Sign-extend the number in the bottom N bits of Imm
542}
543
544template <unsigned N>
546 int64_t Address,
547 const MCDisassembler *Decoder) {
548 if (Imm == 0)
550 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
551}
552
553template <unsigned T, unsigned N>
555 int64_t Address,
556 const MCDisassembler *Decoder) {
557 assert(isUInt<T - N + 1>(Imm) && "Invalid immediate");
558 // Sign-extend the number in the bottom T bits of Imm after accounting for
559 // the fact that the T bit immediate is stored in T-N bits (the LSB is
560 // always zero)
563}
564
566 int64_t Address,
567 const MCDisassembler *Decoder) {
568 assert(isUInt<6>(Imm) && "Invalid immediate");
569 if (Imm == 0)
571 Imm = SignExtend64<6>(Imm) & 0xfffff;
574}
575
576static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
577 const MCDisassembler *Decoder) {
578 assert(isUInt<3>(Imm) && "Invalid immediate");
581
584}
585
586static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
587 const MCDisassembler *Decoder) {
588 assert(isUInt<3>(Imm) && "Invalid immediate");
589 if (Imm != RISCVFPRndMode::RTZ)
591
594}
595
597 uint64_t Address,
598 const MCDisassembler *Decoder) {
599 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
600 if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
604}
605
607 uint64_t Address,
608 const MCDisassembler *Decoder) {
609 if (Imm < RISCVZC::RA_S0)
611 return decodeZcmpRlist(Inst, Imm, Address, Decoder);
612}
613
614#include "RISCVGenDisassemblerTables.inc"
615
616namespace {
617
618struct DecoderListEntry {
619 const uint8_t *Table;
620 FeatureBitset ContainedFeatures;
621 const char *Desc;
622
623 bool haveContainedFeatures(const FeatureBitset &ActiveFeatures) const {
624 return ContainedFeatures.none() ||
625 (ContainedFeatures & ActiveFeatures).any();
626 }
627};
628
629} // end anonymous namespace
630
631static constexpr FeatureBitset XCVFeatureGroup = {
632 RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,
633 RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,
634 RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
635 RISCV::FeatureVendorXCVbi};
636
638 RISCV::FeatureVendorXRivosVisni,
639 RISCV::FeatureVendorXRivosVizip,
640};
641
642static constexpr FeatureBitset XqciFeatureGroup = {
643 RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
644 RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
645 RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
646 RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
647 RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,
648 RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
649 RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
650 RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
651 RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,
652};
653
654static constexpr FeatureBitset XSfVectorGroup = {
655 RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
656 RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
657 RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
658static constexpr FeatureBitset XSfSystemGroup = {
659 RISCV::FeatureVendorXSiFivecdiscarddlone,
660 RISCV::FeatureVendorXSiFivecflushdlone,
661};
662
663static constexpr FeatureBitset XMIPSGroup = {
664 RISCV::FeatureVendorXMIPSLSP,
665 RISCV::FeatureVendorXMIPSCMov,
666 RISCV::FeatureVendorXMIPSCBOP,
667 RISCV::FeatureVendorXMIPSEXECTL,
668};
669
670static constexpr FeatureBitset XTHeadGroup = {
671 RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,
672 RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,
673 RISCV::FeatureVendorXTHeadCmo, RISCV::FeatureVendorXTHeadFMemIdx,
674 RISCV::FeatureVendorXTHeadMac, RISCV::FeatureVendorXTHeadMemIdx,
675 RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
676 RISCV::FeatureVendorXTHeadVdot};
677
678static constexpr FeatureBitset XAndesGroup = {
679 RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
680 RISCV::FeatureVendorXAndesVBFHCvt,
681 RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
682 RISCV::FeatureVendorXAndesVDot};
683
684static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
685
686static constexpr DecoderListEntry DecoderList32[]{
687 // Vendor Extensions
688 {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
689 {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
690 {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
691 {DecoderTableXVentana32,
692 {RISCV::FeatureVendorXVentanaCondOps},
693 "XVentanaCondOps"},
694 {DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},
695 {DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
696 {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
697 {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
698 {DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
699 {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
700 {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
701 // Standard Extensions
702 {DecoderTable32, {}, "standard 32-bit instructions"},
703 {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
704 {DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
705 {DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
706};
707
708namespace {
709// Define bitwidths for various types used to instantiate the decoder.
710template <> constexpr uint32_t InsnBitWidth<uint16_t> = 16;
711template <> constexpr uint32_t InsnBitWidth<uint32_t> = 32;
712// Use uint64_t to represent 48 bit instructions.
713template <> constexpr uint32_t InsnBitWidth<uint64_t> = 48;
714} // namespace
715
716DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
717 ArrayRef<uint8_t> Bytes,
718 uint64_t Address,
719 raw_ostream &CS) const {
720 if (Bytes.size() < 4) {
721 Size = 0;
723 }
724 Size = 4;
725
726 uint32_t Insn = support::endian::read32le(Bytes.data());
727
728 for (const DecoderListEntry &Entry : DecoderList32) {
729 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
730 continue;
731
732 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
734 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
735 if (Result == MCDisassembler::Fail)
736 continue;
737
738 return Result;
739 }
740
742}
743
744static constexpr DecoderListEntry DecoderList16[]{
745 // Vendor Extensions
746 {DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},
747 {DecoderTableXqccmp16,
748 {RISCV::FeatureVendorXqccmp},
749 "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
750 {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
751 // Standard Extensions
752 // DecoderTableZicfiss16 must be checked before DecoderTable16.
753 {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
754 {DecoderTable16, {}, "standard 16-bit instructions"},
755 {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
756 // Zc* instructions incompatible with Zcf or Zcd
757 {DecoderTableZcOverlap16,
758 {},
759 "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)"},
760};
761
762DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
763 ArrayRef<uint8_t> Bytes,
764 uint64_t Address,
765 raw_ostream &CS) const {
766 if (Bytes.size() < 2) {
767 Size = 0;
769 }
770 Size = 2;
771
772 uint16_t Insn = support::endian::read16le(Bytes.data());
773
774 for (const DecoderListEntry &Entry : DecoderList16) {
775 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
776 continue;
777
778 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
780 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
781 if (Result != MCDisassembler::Fail)
782 return Result;
783 }
784
786}
787
788static constexpr DecoderListEntry DecoderList48[]{
789 {DecoderTableXqci48, XqciFeatureGroup, "Qualcomm uC 48bit"},
790};
791
792DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
793 ArrayRef<uint8_t> Bytes,
794 uint64_t Address,
795 raw_ostream &CS) const {
796 if (Bytes.size() < 6) {
797 Size = 0;
799 }
800 Size = 6;
801
802 uint64_t Insn = 0;
803 for (size_t i = Size; i-- != 0;)
804 Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
805
806 for (const DecoderListEntry &Entry : DecoderList48) {
807 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
808 continue;
809
810 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
812 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
813 if (Result == MCDisassembler::Fail)
814 continue;
815
816 return Result;
817 }
818
820}
821
822DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
823 ArrayRef<uint8_t> Bytes,
824 uint64_t Address,
825 raw_ostream &CS) const {
826 CommentStream = &CS;
827 // It's a 16 bit instruction if bit 0 and 1 are not 0b11.
828 if ((Bytes[0] & 0b11) != 0b11)
829 return getInstruction16(MI, Size, Bytes, Address, CS);
830
831 // It's a 32 bit instruction if bit 1:0 are 0b11(checked above) and bits 4:2
832 // are not 0b111.
833 if ((Bytes[0] & 0b1'1100) != 0b1'1100)
834 return getInstruction32(MI, Size, Bytes, Address, CS);
835
836 // 48-bit instructions are encoded as 0bxx011111.
837 if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
838 return getInstruction48(MI, Size, Bytes, Address, CS);
839 }
840
841 // 64-bit instructions are encoded as 0x0111111.
842 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
843 Size = Bytes.size() >= 8 ? 8 : 0;
845 }
846
847 // Remaining cases need to check a second byte.
848 if (Bytes.size() < 2) {
849 Size = 0;
851 }
852
853 // 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
854 // Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
855 unsigned nnn = (Bytes[1] >> 4) & 0b111;
856 if (nnn != 0b111) {
857 Size = 10 + (nnn * 2);
858 if (Bytes.size() < Size)
859 Size = 0;
861 }
862
863 // Remaining encodings are reserved for > 176-bit instructions.
864 Size = 0;
866}
MCDisassembler::DecodeStatus DecodeStatus
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
IRTranslator LLVM IR MI
Register Reg
#define T
static constexpr FeatureBitset XqciFeatureGroup
static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static constexpr FeatureBitset XSMTGroup
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static constexpr FeatureBitset XCVFeatureGroup
static constexpr DecoderListEntry DecoderList48[]
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static constexpr DecoderListEntry DecoderList16[]
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeImmFourOperand(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static constexpr FeatureBitset XSfVectorGroup
static constexpr DecoderListEntry DecoderList32[]
static DecodeStatus DecodeGPRX5RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus decodeImmThreeOperand(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeImmZibiOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
static constexpr FeatureBitset XMIPSGroup
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static constexpr FeatureBitset XAndesGroup
static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const void *Decoder)
static constexpr FeatureBitset XTHeadGroup
static constexpr FeatureBitset XRivosFeatureGroup
static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static constexpr FeatureBitset XSfSystemGroup
static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_DEBUG(...)
Definition Debug.h:114
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
const T * data() const
Definition ArrayRef.h:144
Container class for subtarget features.
Context object for machine code objects.
Definition MCContext.h:83
Superclass for all disassemblers.
const MCSubtargetInfo & getSubtargetInfo() const
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
void addOperand(const MCOperand Op)
Definition MCInst.h:215
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
constexpr bool any(E Val)
@ Entry
Definition COFF.h:862
static bool isValidRoundingMode(unsigned Mode)
uint16_t read16le(const void *P)
Definition Endian.h:425
uint32_t read32le(const void *P)
Definition Endian.h:428
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheRISCV32Target()
Target & getTheRISCV64beTarget()
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:207
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:198
Target & getTheRISCV64Target()
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:583
Target & getTheRISCV32beTarget()
#define N
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.