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LLVM 22.0.0git
llvm::SelectionDAG Class Reference

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection. More...

#include "llvm/CodeGen/SelectionDAG.h"

Classes

struct  DAGNodeDeletedListener
struct  DAGNodeInsertedListener
struct  DAGUpdateListener
 Clients of various APIs that cause global effects on the DAG can optionally implement this interface. More...
class  FlagInserter
 Help to insert SDNodeFlags automatically in transforming. More...

Public Types

enum  OverflowKind { OFK_Never , OFK_Sometime , OFK_Always }
 Used to represent the possible overflow behavior of an operation. More...
using allnodes_const_iterator = ilist<SDNode>::const_iterator
using allnodes_iterator = ilist<SDNode>::iterator

Public Member Functions

LLVM_ABI SelectionDAG (const TargetMachine &TM, CodeGenOptLevel)
 SelectionDAG (const SelectionDAG &)=delete
SelectionDAGoperator= (const SelectionDAG &)=delete
LLVM_ABI ~SelectionDAG ()
LLVM_ABI void init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs)
 Prepare this SelectionDAG to process code in the given MachineFunction.
void init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, MachineFunctionAnalysisManager &AM, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs)
void setFunctionLoweringInfo (FunctionLoweringInfo *FuncInfo)
LLVM_ABI void clear ()
 Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
MachineFunctiongetMachineFunction () const
const PassgetPass () const
MachineFunctionAnalysisManagergetMFAM ()
CodeGenOptLevel getOptLevel () const
const DataLayoutgetDataLayout () const
const TargetMachinegetTarget () const
const TargetSubtargetInfogetSubtarget () const
template<typename STC>
const STC & getSubtarget () const
const TargetLoweringgetTargetLoweringInfo () const
const TargetLibraryInfogetLibInfo () const
const SelectionDAGTargetInfogetSelectionDAGInfo () const
const UniformityInfogetUniformityInfo () const
const FunctionVarLocsgetFunctionVarLocs () const
 Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr.
LLVMContextgetContext () const
OptimizationRemarkEmittergetORE () const
ProfileSummaryInfogetPSI () const
BlockFrequencyInfogetBFI () const
MachineModuleInfogetMMI () const
FlagInsertergetFlagInserter ()
void setFlagInserter (FlagInserter *FI)
LLVM_DUMP_METHOD void dumpDotGraph (const Twine &FileName, const Twine &Title)
 Just dump dot graph to a user-provided path and title.
LLVM_ABI void viewGraph (const std::string &Title)
 Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
LLVM_ABI void viewGraph ()
LLVM_ABI void clearGraphAttrs ()
 Clear all previously defined node graph attributes.
LLVM_ABI void setGraphAttrs (const SDNode *N, const char *Attrs)
 Set graph attributes for a node. (eg. "color=red".)
LLVM_ABI std::string getGraphAttrs (const SDNode *N) const
 Get graph attributes for a node.
LLVM_ABI void setGraphColor (const SDNode *N, const char *Color)
 Convenience for setting node color attribute.
LLVM_ABI void setSubgraphColor (SDNode *N, const char *Color)
 Convenience for setting subgraph color attribute.
allnodes_const_iterator allnodes_begin () const
allnodes_const_iterator allnodes_end () const
allnodes_iterator allnodes_begin ()
allnodes_iterator allnodes_end ()
ilist< SDNode >::size_type allnodes_size () const
iterator_range< allnodes_iteratorallnodes ()
iterator_range< allnodes_const_iteratorallnodes () const
const SDValuegetRoot () const
 Return the root tag of the SelectionDAG.
SDValue getEntryNode () const
 Return the token chain corresponding to the entry of the function.
const SDValuesetRoot (SDValue N)
 Set the current root tag of the SelectionDAG.
LLVM_ABI void Combine (CombineLevel Level, BatchAAResults *BatchAA, CodeGenOptLevel OptLevel)
 This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.
LLVM_ABI bool LegalizeTypes ()
 This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target.
LLVM_ABI void Legalize ()
 This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object.
LLVM_ABI bool LegalizeOp (SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
 Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object.
LLVM_ABI bool LegalizeVectors ()
 This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target.
LLVM_ABI void RemoveDeadNodes ()
 This method deletes all unreachable nodes in the SelectionDAG.
LLVM_ABI void DeleteNode (SDNode *N)
 Remove the specified node from the system.
LLVM_ABI SDVTList getVTList (EVT VT)
 Return an SDVTList that represents the list of values specified.
LLVM_ABI SDVTList getVTList (EVT VT1, EVT VT2)
LLVM_ABI SDVTList getVTList (EVT VT1, EVT VT2, EVT VT3)
LLVM_ABI SDVTList getVTList (EVT VT1, EVT VT2, EVT VT3, EVT VT4)
LLVM_ABI SDVTList getVTList (ArrayRef< EVT > VTs)
LLVM_ABI SDValue getGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getTargetGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
LLVM_ABI SDValue getFrameIndex (int FI, EVT VT, bool isTarget=false)
SDValue getTargetFrameIndex (int FI, EVT VT)
LLVM_ABI SDValue getJumpTable (int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
SDValue getTargetJumpTable (int JTI, EVT VT, unsigned TargetFlags=0)
LLVM_ABI SDValue getJumpTableDebugInfo (int JTI, SDValue Chain, const SDLoc &DL)
LLVM_ABI SDValue getConstantPool (const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getTargetConstantPool (const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
LLVM_ABI SDValue getConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getTargetConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
LLVM_ABI SDValue getBasicBlock (MachineBasicBlock *MBB)
LLVM_ABI SDValue getExternalSymbol (const char *Sym, EVT VT)
LLVM_ABI SDValue getTargetExternalSymbol (const char *Sym, EVT VT, unsigned TargetFlags=0)
LLVM_ABI SDValue getMCSymbol (MCSymbol *Sym, EVT VT)
LLVM_ABI SDValue getValueType (EVT)
LLVM_ABI SDValue getRegister (Register Reg, EVT VT)
LLVM_ABI SDValue getRegisterMask (const uint32_t *RegMask)
LLVM_ABI SDValue getEHLabel (const SDLoc &dl, SDValue Root, MCSymbol *Label)
LLVM_ABI SDValue getLabelNode (unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
LLVM_ABI SDValue getBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue getTargetBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, Register Reg, SDValue N, SDValue Glue)
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N, SDValue Glue)
SDValue getCopyFromReg (SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
SDValue getCopyFromReg (SDValue Chain, const SDLoc &dl, Register Reg, EVT VT, SDValue Glue)
LLVM_ABI SDValue getCondCode (ISD::CondCode Cond)
LLVM_ABI SDValue getVectorShuffle (EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
 Return an ISD::VECTOR_SHUFFLE node.
SDValue getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
 Return an ISD::BUILD_VECTOR node.
SDValue getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDUse > Ops)
 Return an ISD::BUILD_VECTOR node.
SDValue getSplatBuildVector (EVT VT, const SDLoc &DL, SDValue Op)
 Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getSplatVector (EVT VT, const SDLoc &DL, SDValue Op)
SDValue getSplat (EVT VT, const SDLoc &DL, SDValue Op)
 Returns a node representing a splat of one value into all lanes of the provided vector type.
LLVM_ABI SDValue getStepVector (const SDLoc &DL, EVT ResVT, const APInt &StepVal)
 Returns a vector of type ResVT whose elements contain the linear sequence <0, Step, Step * 2, Step * 3, ...>
LLVM_ABI SDValue getStepVector (const SDLoc &DL, EVT ResVT)
 Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...>
LLVM_ABI SDValue getCommutedVectorShuffle (const ShuffleVectorSDNode &SV)
 Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.
SDValue getExtractVectorElt (const SDLoc &DL, EVT VT, SDValue Vec, unsigned Idx)
 Extract element at Idx from Vec.
SDValue getInsertVectorElt (const SDLoc &DL, SDValue Vec, SDValue Elt, unsigned Idx)
 Insert Elt into Vec at offset Idx.
SDValue getInsertSubvector (const SDLoc &DL, SDValue Vec, SDValue SubVec, unsigned Idx)
 Insert SubVec at the Idx element of Vec.
SDValue getExtractSubvector (const SDLoc &DL, EVT VT, SDValue Vec, unsigned Idx)
 Return the VT typed sub-vector of Vec at Idx.
LLVM_ABI SDValue getFPExtendOrRound (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).
LLVM_ABI std::pair< SDValue, SDValuegetStrictFPExtendOrRound (SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
 Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation).
LLVM_ABI SDValue getAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it.
LLVM_ABI SDValue getSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it.
LLVM_ABI SDValue getZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it.
SDValue getExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT, unsigned Opcode)
 Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it.
SDValue getExtOrTrunc (bool IsSigned, SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it.
LLVM_ABI SDValue getBitcastedAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it.
LLVM_ABI SDValue getBitcastedSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it.
LLVM_ABI SDValue getBitcastedZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it.
LLVM_ABI SDValue getZeroExtendInReg (SDValue Op, const SDLoc &DL, EVT VT)
 Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
LLVM_ABI SDValue getVPZeroExtendInReg (SDValue Op, SDValue Mask, SDValue EVL, const SDLoc &DL, EVT VT)
 Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
LLVM_ABI SDValue getPtrExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics.
LLVM_ABI SDValue getPtrExtendInReg (SDValue Op, const SDLoc &DL, EVT VT)
 Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value.
LLVM_ABI SDValue getBoolExtOrTrunc (SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
 Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.
LLVM_ABI SDValue getNegative (SDValue Val, const SDLoc &DL, EVT VT)
 Create negative operation as (SUB 0, Val).
LLVM_ABI SDValue getNOT (const SDLoc &DL, SDValue Val, EVT VT)
 Create a bitwise NOT operation as (XOR Val, -1).
LLVM_ABI SDValue getLogicalNOT (const SDLoc &DL, SDValue Val, EVT VT)
 Create a logical NOT operation as (XOR Val, BooleanOne).
LLVM_ABI SDValue getVPLogicalNOT (const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
 Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL).
LLVM_ABI SDValue getVPZExtOrTrunc (const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
 Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT, by performing either vector-predicated zext or truncating it.
LLVM_ABI SDValue getVPPtrExtOrTrunc (const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
 Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT, by either truncating it or performing either vector-predicated zero or sign extension as appropriate extension for the pointer's semantics.
LLVM_ABI SDValue getMemBasePlusOffset (SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
 Returns sum of the base pointer and offset.
LLVM_ABI SDValue getMemBasePlusOffset (SDValue Base, SDValue Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
SDValue getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, TypeSize Offset)
 Create an add instruction with appropriate flags when used for addressing some offset of an object.
SDValue getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, SDValue Offset)
SDValue getCALLSEQ_START (SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
 Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence.
SDValue getCALLSEQ_END (SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
 Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getCALLSEQ_END (SDValue Chain, uint64_t Size1, uint64_t Size2, SDValue Glue, const SDLoc &DL)
LLVM_ABI bool isUndef (unsigned Opcode, ArrayRef< SDValue > Ops)
 Return true if the result of this operation is always undefined.
SDValue getUNDEF (EVT VT)
 Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getPOISON (EVT VT)
 Return a POISON node. POISON does not have a useful SDLoc.
LLVM_ABI SDValue getVScale (const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
 Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
LLVM_ABI SDValue getElementCount (const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGLOBAL_OFFSET_TABLE (EVT VT)
 Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
 Gets or creates the specified node.
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT)
 Gets or creates the specified node.
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5, const SDNodeFlags Flags)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4)
LLVM_ABI SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5)
LLVM_ABI SDValue getStackArgumentTokenFactor (SDValue Chain)
 Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
std::pair< SDValue, SDValuegetMemcmp (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, const CallInst *CI)
LLVM_ABI std::pair< SDValue, SDValuegetStrlen (SDValue Chain, const SDLoc &dl, SDValue Src, const CallInst *CI)
LLVM_ABI SDValue getMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
LLVM_ABI SDValue getMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
LLVM_ABI SDValue getMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getAtomicMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
LLVM_ABI SDValue getAtomicMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
LLVM_ABI SDValue getAtomicMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getSetCC (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
 Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue.
SDValue getSetCCVP (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Mask, SDValue EVL)
 Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an SDValue.
SDValue getSelect (const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())
 Helper function to make it easier to build Select's if you just have operands and don't want to check for vector.
SDValue getSelectCC (const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond, SDNodeFlags Flags=SDNodeFlags())
 Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue.
LLVM_ABI SDValue simplifySelect (SDValue Cond, SDValue TVal, SDValue FVal)
 Try to simplify a select/vselect into 1 of its operands or a constant.
LLVM_ABI SDValue simplifyShift (SDValue X, SDValue Y)
 Try to simplify a shift into 1 of its operands or a constant.
LLVM_ABI SDValue simplifyFPBinop (unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
 Try to simplify a floating-point binary operation into 1 of its operands or a constant.
LLVM_ABI SDValue getVAArg (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
 VAArg produces a result and token chain, and takes a pointer and a source value as input.
LLVM_ABI SDValue getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
 Gets a node for an atomic cmpxchg op.
LLVM_ABI SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
 Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
LLVM_ABI SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTList, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::LoadExtType ExtType=ISD::NON_EXTLOAD)
 Gets a node for an atomic op, produces result and chain and takes N operands.
LLVM_ABI SDValue getAtomicLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO)
LLVM_ABI SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=LocationSize::precise(0), const AAMDNodes &AAInfo=AAMDNodes())
 Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment=std::nullopt, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=LocationSize::precise(0), const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getLifetimeNode (bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex)
 Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the FrameIndex.
LLVM_ABI SDValue getPseudoProbeNode (const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
 Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing, as well as the attributes attr of the probe.
LLVM_ABI SDValue getMergeValues (ArrayRef< SDValue > Ops, const SDLoc &dl)
 Create a MERGE_VALUES node from the given operands.
LLVM_ABI SDValue getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
 Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.
LLVM_ABI SDValue getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO)
LLVM_ABI SDValue getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getIndexedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
LLVM_ABI SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 Helper function to build ISD::STORE nodes.
SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachineMemOperand *MMO)
LLVM_ABI SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, EVT SVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getIndexedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, EVT SVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false)
LLVM_ABI SDValue getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, bool IsExpanding=false)
LLVM_ABI SDValue getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
LLVM_ABI SDValue getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
LLVM_ABI SDValue getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getIndexedLoadVP (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
LLVM_ABI SDValue getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
LLVM_ABI SDValue getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
LLVM_ABI SDValue getIndexedStoreVP (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getStridedLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getStridedLoadVP (EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getExtStridedLoadVP (ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
LLVM_ABI SDValue getStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
LLVM_ABI SDValue getTruncStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
LLVM_ABI SDValue getGatherVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
LLVM_ABI SDValue getScatterVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
LLVM_ABI SDValue getMaskedLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
LLVM_ABI SDValue getIndexedMaskedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getMaskedStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
LLVM_ABI SDValue getIndexedMaskedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getMaskedGather (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
LLVM_ABI SDValue getMaskedScatter (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
LLVM_ABI SDValue getMaskedHistogram (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
LLVM_ABI SDValue getLoadFFVP (EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachineMemOperand *MMO)
LLVM_ABI SDValue getGetFPEnv (SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getSetFPEnv (SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
LLVM_ABI SDValue getSrcValue (const Value *v)
 Construct a node to track a Value* through the backend.
LLVM_ABI SDValue getMDNode (const MDNode *MD)
 Return an MDNodeSDNode which holds an MDNode.
LLVM_ABI SDValue getBitcast (EVT VT, SDValue V)
 Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
LLVM_ABI SDValue getAddrSpaceCast (const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
 Return an AddrSpaceCastSDNode.
LLVM_ABI SDValue getFreeze (SDValue V)
 Return a freeze using the SDLoc of the value operand.
LLVM_ABI SDValue getAssertAlign (const SDLoc &DL, SDValue V, Align A)
 Return an AssertAlignSDNode.
LLVM_ABI void canonicalizeCommutativeBinop (unsigned Opcode, SDValue &N1, SDValue &N2) const
 Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order.
LLVM_ABI SDValue getShiftAmountOperand (EVT LHSTy, SDValue Op)
 Return the specified value casted to the target's desired shift amount type.
LLVM_ABI bool expandMultipleResultFPLibCall (RTLIB::Libcall LC, SDNode *Node, SmallVectorImpl< SDValue > &Results, std::optional< unsigned > CallRetResNo={})
 Expands a node with multiple results to an FP or vector libcall.
LLVM_ABI SDValue expandVAArg (SDNode *Node)
 Expand the specified ISD::VAARG node as the Legalize pass would.
LLVM_ABI SDValue expandVACopy (SDNode *Node)
 Expand the specified ISD::VACOPY node as the Legalize pass would.
LLVM_ABI SDValue getSymbolFunctionGlobalAddress (SDValue Op, Function **TargetFunction=nullptr)
 Return a GlobalAddress of the function from the current module with name matching the given ExternalSymbol.
LLVM_ABI SDNodeUpdateNodeOperands (SDNode *N, SDValue Op)
 Mutate the specified node in-place to have the specified operands.
LLVM_ABI SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2)
LLVM_ABI SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3)
LLVM_ABI SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4)
LLVM_ABI SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5)
LLVM_ABI SDNodeUpdateNodeOperands (SDNode *N, ArrayRef< SDValue > Ops)
LLVM_ABI SDValue getTokenFactor (const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
 Creates a new TokenFactor containing Vals.
LLVM_ABI void setNodeMemRefs (MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
 Mutate the specified machine node's memory references to the provided list.
LLVM_ABI bool calculateDivergence (SDNode *N)
LLVM_ABI void updateDivergence (SDNode *N)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT)
 These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands.
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, ArrayRef< SDValue > Ops)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2)
LLVM_ABI SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, SDVTList VTs, ArrayRef< SDValue > Ops)
LLVM_ABI SDNodeMorphNodeTo (SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
 This mutates the specified node to have the specified return type, opcode, and operands.
LLVM_ABI SDNodemutateStrictFPToFP (SDNode *Node)
 Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments.
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT)
 These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, ArrayRef< SDValue > Ops)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops)
LLVM_ABI MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, SDVTList VTs, ArrayRef< SDValue > Ops)
LLVM_ABI SDValue getTargetExtractSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
 A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
LLVM_ABI SDValue getTargetInsertSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
 A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
LLVM_ABI SDNodegetNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
 Get the specified node if it's already available, or else return NULL.
LLVM_ABI SDNodegetNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
 getNodeIfExists - Get the specified node if it's already available, or else return NULL.
LLVM_ABI bool doesNodeExist (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
 Check if a node exists without modifying its flags.
LLVM_ABI SDDbgValuegetDbgValue (DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a SDDbgValue node.
LLVM_ABI SDDbgValuegetConstantDbgValue (DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
 Creates a constant SDDbgValue node.
LLVM_ABI SDDbgValuegetFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a FrameIndex SDDbgValue node.
LLVM_ABI SDDbgValuegetFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a FrameIndex SDDbgValue node.
LLVM_ABI SDDbgValuegetVRegDbgValue (DIVariable *Var, DIExpression *Expr, Register VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a VReg SDDbgValue node.
LLVM_ABI SDDbgValuegetDbgValueList (DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
 Creates a SDDbgValue node from a list of locations.
LLVM_ABI SDDbgLabelgetDbgLabel (DILabel *Label, const DebugLoc &DL, unsigned O)
 Creates a SDDbgLabel node.
LLVM_ABI void transferDbgValues (SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
 Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values.
LLVM_ABI void RemoveDeadNode (SDNode *N)
 Remove the specified node from the system.
LLVM_ABI void RemoveDeadNodes (SmallVectorImpl< SDNode * > &DeadNodes)
 This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
LLVM_ABI void ReplaceAllUsesWith (SDValue From, SDValue To)
 Modify anything using 'From' to use 'To' instead.
LLVM_ABI void ReplaceAllUsesWith (SDNode *From, SDNode *To)
 ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
LLVM_ABI void ReplaceAllUsesWith (SDNode *From, const SDValue *To)
 ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
LLVM_ABI void ReplaceAllUsesOfValueWith (SDValue From, SDValue To)
 Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
LLVM_ABI void ReplaceAllUsesOfValuesWith (const SDValue *From, const SDValue *To, unsigned Num)
 Like ReplaceAllUsesOfValueWith, but for multiple values at once.
LLVM_ABI SDValue makeEquivalentMemoryOrdering (SDValue OldChain, SDValue NewMemOpChain)
 If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
LLVM_ABI SDValue makeEquivalentMemoryOrdering (LoadSDNode *OldLoad, SDValue NewMemOp)
 If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
LLVM_ABI unsigned AssignTopologicalOrder ()
 Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.
void RepositionNode (allnodes_iterator Position, SDNode *N)
 Move node N in the AllNodes list to be immediately before the given iterator Position.
LLVM_ABI void AddDbgValue (SDDbgValue *DB, bool isParameter)
 Add a dbg_value SDNode.
LLVM_ABI void AddDbgLabel (SDDbgLabel *DB)
 Add a dbg_label SDNode.
ArrayRef< SDDbgValue * > GetDbgValues (const SDNode *SD) const
 Get the debug values which reference the given SDNode.
bool hasDebugValues () const
 Return true if there are any SDDbgValue nodes associated with this SelectionDAG.
SDDbgInfo::DbgIterator DbgBegin () const
SDDbgInfo::DbgIterator DbgEnd () const
SDDbgInfo::DbgIterator ByvalParmDbgBegin () const
SDDbgInfo::DbgIterator ByvalParmDbgEnd () const
SDDbgInfo::DbgLabelIterator DbgLabelBegin () const
SDDbgInfo::DbgLabelIterator DbgLabelEnd () const
LLVM_ABI void salvageDebugInfo (SDNode &N)
 To be invoked on an SDNode that is slated to be erased.
LLVM_ABI void dump () const
LLVM_ABI Align getReducedAlign (EVT VT, bool UseABI)
 In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack.
LLVM_ABI SDValue CreateStackTemporary (TypeSize Bytes, Align Alignment)
 Create a stack temporary based on the size in bytes and the alignment.
LLVM_ABI SDValue CreateStackTemporary (EVT VT, unsigned minAlign=1)
 Create a stack temporary, suitable for holding the specified value type.
LLVM_ABI SDValue CreateStackTemporary (EVT VT1, EVT VT2)
 Create a stack temporary suitable for holding either of the specified value types.
LLVM_ABI SDValue FoldSymbolOffset (unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
LLVM_ABI SDValue FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SDNodeFlags Flags=SDNodeFlags())
LLVM_ABI SDValue foldConstantFPMath (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
 Fold floating-point operations when all operands are constants and/or undefined.
LLVM_ABI SDValue FoldConstantBuildVector (BuildVectorSDNode *BV, const SDLoc &DL, EVT DstEltVT)
 Fold BUILD_VECTOR of constants/undefs to the destination type BUILD_VECTOR of constants/undefs elements.
LLVM_ABI SDValue FoldSetCC (EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
 Constant fold a setcc to true or false.
LLVM_ABI bool SignBitIsZero (SDValue Op, unsigned Depth=0) const
 Return true if the sign bit of Op is known to be zero.
LLVM_ABI bool MaskedValueIsZero (SDValue Op, const APInt &Mask, unsigned Depth=0) const
 Return true if 'Op & Mask' is known to be zero.
LLVM_ABI bool MaskedValueIsZero (SDValue Op, const APInt &Mask, const APInt &DemandedElts, unsigned Depth=0) const
 Return true if 'Op & Mask' is known to be zero in DemandedElts.
LLVM_ABI bool MaskedVectorIsZero (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Return true if 'Op' is known to be zero in DemandedElts.
LLVM_ABI bool MaskedValueIsAllOnes (SDValue Op, const APInt &Mask, unsigned Depth=0) const
 Return true if '(Op & Mask) == Mask'.
LLVM_ABI APInt computeVectorKnownZeroElements (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 For each demanded element of a vector, see if it is known to be zero.
LLVM_ABI KnownBits computeKnownBits (SDValue Op, unsigned Depth=0) const
 Determine which bits of Op are known to be either zero or one and return them in Known.
LLVM_ABI KnownBits computeKnownBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Determine which bits of Op are known to be either zero or one and return them in Known.
LLVM_ABI OverflowKind computeOverflowForSignedAdd (SDValue N0, SDValue N1) const
 Determine if the result of the signed addition of 2 nodes can overflow.
LLVM_ABI OverflowKind computeOverflowForUnsignedAdd (SDValue N0, SDValue N1) const
 Determine if the result of the unsigned addition of 2 nodes can overflow.
OverflowKind computeOverflowForAdd (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the addition of 2 nodes can overflow.
bool willNotOverflowAdd (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the addition of 2 nodes can never overflow.
LLVM_ABI OverflowKind computeOverflowForSignedSub (SDValue N0, SDValue N1) const
 Determine if the result of the signed sub of 2 nodes can overflow.
LLVM_ABI OverflowKind computeOverflowForUnsignedSub (SDValue N0, SDValue N1) const
 Determine if the result of the unsigned sub of 2 nodes can overflow.
OverflowKind computeOverflowForSub (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the sub of 2 nodes can overflow.
bool willNotOverflowSub (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the sub of 2 nodes can never overflow.
LLVM_ABI OverflowKind computeOverflowForSignedMul (SDValue N0, SDValue N1) const
 Determine if the result of the signed mul of 2 nodes can overflow.
LLVM_ABI OverflowKind computeOverflowForUnsignedMul (SDValue N0, SDValue N1) const
 Determine if the result of the unsigned mul of 2 nodes can overflow.
OverflowKind computeOverflowForMul (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the mul of 2 nodes can overflow.
bool willNotOverflowMul (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the mul of 2 nodes can never overflow.
LLVM_ABI bool isKnownToBeAPowerOfTwo (SDValue Val, unsigned Depth=0) const
 Test if the given value is known to have exactly one bit set.
LLVM_ABI bool isKnownToBeAPowerOfTwoFP (SDValue Val, unsigned Depth=0) const
 Test if the given fp value is known to be an integer power-of-2, either positive or negative.
LLVM_ABI unsigned ComputeNumSignBits (SDValue Op, unsigned Depth=0) const
 Return the number of times the sign bit of the register is replicated into the other bits.
LLVM_ABI unsigned ComputeNumSignBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Return the number of times the sign bit of the register is replicated into the other bits.
LLVM_ABI unsigned ComputeMaxSignificantBits (SDValue Op, unsigned Depth=0) const
 Get the upper bound on bit size for this Value Op as a signed integer.
LLVM_ABI unsigned ComputeMaxSignificantBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Get the upper bound on bit size for this Value Op as a signed integer.
LLVM_ABI bool isGuaranteedNotToBeUndefOrPoison (SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits.
LLVM_ABI bool isGuaranteedNotToBeUndefOrPoison (SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits.
bool isGuaranteedNotToBePoison (SDValue Op, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison.
bool isGuaranteedNotToBePoison (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison.
LLVM_ABI bool canCreateUndefOrPoison (SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
 Return true if Op can create undef or poison from non-undef & non-poison operands.
LLVM_ABI bool canCreateUndefOrPoison (SDValue Op, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
 Return true if Op can create undef or poison from non-undef & non-poison operands.
LLVM_ABI bool isADDLike (SDValue Op, bool NoWrap=false) const
 Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::ADD node.
LLVM_ABI bool isBaseWithConstantOffset (SDValue Op) const
 Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD.
LLVM_ABI bool isKnownNeverNaN (SDValue Op, const APInt &DemandedElts, bool SNaN=false, unsigned Depth=0) const
 Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN in DemandedElts.
LLVM_ABI bool isKnownNeverNaN (SDValue Op, bool SNaN=false, unsigned Depth=0) const
 Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
bool isKnownNeverSNaN (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
bool isKnownNeverSNaN (SDValue Op, unsigned Depth=0) const
LLVM_ABI bool isKnownNeverZeroFloat (SDValue Op) const
 Test whether the given floating point SDValue is known to never be positive or negative zero.
LLVM_ABI bool isKnownNeverZero (SDValue Op, unsigned Depth=0) const
 Test whether the given SDValue is known to contain non-zero value(s).
LLVM_ABI bool cannotBeOrderedNegativeFP (SDValue Op) const
 Test whether the given float value is known to be positive.
LLVM_ABI bool isEqualTo (SDValue A, SDValue B) const
 Test whether two SDValues are known to compare equal.
LLVM_ABI bool haveNoCommonBitsSet (SDValue A, SDValue B) const
 Return true if A and B have no common bits set.
LLVM_ABI bool isSplatValue (SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
 Test whether V has a splatted value for all the demanded elements.
LLVM_ABI bool isSplatValue (SDValue V, bool AllowUndefs=false) const
 Test whether V has a splatted value.
LLVM_ABI SDValue getSplatSourceVector (SDValue V, int &SplatIndex)
 If V is a splatted value, return the source vector and its splat index.
LLVM_ABI SDValue getSplatValue (SDValue V, bool LegalTypes=false)
 If V is a splat vector, return its scalar source operand by extracting that element from the source vector.
LLVM_ABI std::optional< ConstantRangegetValidShiftAmountRange (SDValue V, const APInt &DemandedElts, unsigned Depth) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the valid constant range.
LLVM_ABI std::optional< unsignedgetValidShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it.
LLVM_ABI std::optional< unsignedgetValidShiftAmount (SDValue V, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it.
LLVM_ABI std::optional< unsignedgetValidMinimumShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
LLVM_ABI std::optional< unsignedgetValidMinimumShiftAmount (SDValue V, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
LLVM_ABI std::optional< unsignedgetValidMaximumShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
LLVM_ABI std::optional< unsignedgetValidMaximumShiftAmount (SDValue V, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
LLVM_ABI SDValue matchBinOpReduction (SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
 Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract.
LLVM_ABI SDValue UnrollVectorOp (SDNode *N, unsigned ResNE=0)
 Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually.
LLVM_ABI std::pair< SDValue, SDValueUnrollVectorOverflowOp (SDNode *N, unsigned ResNE=0)
 Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
LLVM_ABI bool areNonVolatileConsecutiveLoads (LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
 Return true if loads are next to each other and can be merged.
LLVM_ABI MaybeAlign InferPtrAlign (SDValue Ptr) const
 Infer alignment of a load / store address.
LLVM_ABI std::pair< SDValue, SDValueSplitScalar (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
 Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
LLVM_ABI std::pair< EVT, EVTGetSplitDestVTs (const EVT &VT) const
 Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
LLVM_ABI std::pair< EVT, EVTGetDependentSplitDestVTs (const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
 Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
LLVM_ABI std::pair< SDValue, SDValueSplitVector (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
 Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
std::pair< SDValue, SDValueSplitVector (const SDValue &N, const SDLoc &DL)
 Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
LLVM_ABI std::pair< SDValue, SDValueSplitEVL (SDValue N, EVT VecVT, const SDLoc &DL)
 Split the explicit vector length parameter of a VP operation.
std::pair< SDValue, SDValueSplitVectorOperand (const SDNode *N, unsigned OpNo)
 Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part.
LLVM_ABI SDValue WidenVector (const SDValue &N, const SDLoc &DL)
 Widen the vector up to the next power of two using INSERT_SUBVECTOR.
LLVM_ABI void ExtractVectorElements (SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
 Append the extracted elements from Start to Count out of the vector Op in Args.
LLVM_ABI Align getEVTAlign (EVT MemoryVT) const
 Compute the default alignment value for the given type.
LLVM_ABI bool isConstantIntBuildVectorOrConstantInt (SDValue N, bool AllowOpaques=true) const
 Test whether the given value is a constant int or similar node.
LLVM_ABI bool isConstantFPBuildVectorOrConstantFP (SDValue N) const
 Test whether the given value is a constant FP or similar node.
bool isConstantValueOfAnyType (SDValue N) const
LLVM_ABI std::optional< boolisBoolConstant (SDValue N) const
 Check if a value \op N is a constant using the target's BooleanContent for its type.
void addCallSiteInfo (const SDNode *Node, CallSiteInfo &&CallInfo)
 Set CallSiteInfo to be associated with Node.
CallSiteInfo getCallSiteInfo (const SDNode *Node)
 Return CallSiteInfo associated with Node, or a default if none exists.
void addHeapAllocSite (const SDNode *Node, MDNode *MD)
 Set HeapAllocSite to be associated with Node.
MDNodegetHeapAllocSite (const SDNode *Node) const
 Return HeapAllocSite associated with Node, or nullptr if none exists.
void addPCSections (const SDNode *Node, MDNode *MD)
 Set PCSections to be associated with Node.
void addMMRAMetadata (const SDNode *Node, MDNode *MMRA)
 Set MMRAMetadata to be associated with Node.
MDNodegetPCSections (const SDNode *Node) const
 Return PCSections associated with Node, or nullptr if none exists.
MDNodegetMMRAMetadata (const SDNode *Node) const
 Return the MMRA MDNode associated with Node, or nullptr if none exists.
void addCalledGlobal (const SDNode *Node, const GlobalValue *GV, unsigned OpFlags)
 Set CalledGlobal to be associated with Node.
std::optional< CalledGlobalInfogetCalledGlobal (const SDNode *Node)
 Return CalledGlobal associated with Node, or a nullopt if none exists.
void addNoMergeSiteInfo (const SDNode *Node, bool NoMerge)
 Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
bool getNoMergeSiteInfo (const SDNode *Node) const
 Return NoMerge info associated with Node.
LLVM_ABI void copyExtraInfo (SDNode *From, SDNode *To)
 Copy extra info associated with one node to another.
DenormalMode getDenormalMode (EVT VT) const
 Return the current function's default denormal handling kind for the given floating point type.
LLVM_ABI bool shouldOptForSize () const
LLVM_ABI SDValue getNeutralElement (unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
 Get the (commutative) neutral element for the given opcode, if it exists.
bool isSafeToSpeculativelyExecute (unsigned Opcode) const
 Some opcodes may create immediate undefined behavior when used with some values (integer division-by-zero for example).
bool isSafeToSpeculativelyExecuteNode (const SDNode *N) const
 Check if the provided node is save to speculatively executed given its current arguments.
LLVM_ABI SDValue makeStateFunctionCall (unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
 Helper used to make a call to a library function that has one argument of pointer type.
LLVM_ABI SDValue getConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
 Create a ConstantSDNode wrapping a constant value.
LLVM_ABI SDValue getConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
LLVM_ABI SDValue getSignedConstant (int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
LLVM_ABI SDValue getAllOnesConstant (const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
LLVM_ABI SDValue getConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
LLVM_ABI SDValue getIntPtrConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false)
LLVM_ABI SDValue getShiftAmountConstant (uint64_t Val, EVT VT, const SDLoc &DL)
LLVM_ABI SDValue getShiftAmountConstant (const APInt &Val, EVT VT, const SDLoc &DL)
LLVM_ABI SDValue getVectorIdxConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getTargetConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getSignedTargetConstant (int64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
LLVM_ABI SDValue getBoolConstant (bool V, const SDLoc &DL, EVT VT, EVT OpVT)
 Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
LLVM_ABI SDValue getConstantFP (double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
 Create a ConstantFPSDNode wrapping a constant value.
LLVM_ABI SDValue getConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT, bool isTarget=false)
LLVM_ABI SDValue getConstantFP (const ConstantFP &V, const SDLoc &DL, EVT VT, bool isTarget=false)
SDValue getTargetConstantFP (double Val, const SDLoc &DL, EVT VT)
SDValue getTargetConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT)
SDValue getTargetConstantFP (const ConstantFP &Val, const SDLoc &DL, EVT VT)

Static Public Member Functions

static LLVM_ABI unsigned getHasPredecessorMaxSteps ()
static unsigned getOpcode_EXTEND (unsigned Opcode)
 Convert *_EXTEND_VECTOR_INREG to *_EXTEND opcode.
static unsigned getOpcode_EXTEND_VECTOR_INREG (unsigned Opcode)
 Convert *_EXTEND to *_EXTEND_VECTOR_INREG opcode.

Public Attributes

bool NewNodesMustHaveLegalTypes = false
 When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types.

Static Public Attributes

static constexpr unsigned MaxRecursionDepth = 6

Friends

struct DAGUpdateListener
 DAGUpdateListener is a friend so it can manipulate the listener stack.

Detailed Description

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection.

This DAG is constructed as the first step of instruction selection in order to allow implementation of machine specific optimizations and code simplifications.

The representation used by the SelectionDAG is a target-independent representation, which has some similarities to the GCC RTL representation, but is significantly more simple, powerful, and is a graph form instead of a linear form.

Definition at line 229 of file SelectionDAG.h.

Member Typedef Documentation

◆ allnodes_const_iterator

◆ allnodes_iterator

Definition at line 561 of file SelectionDAG.h.

Member Enumeration Documentation

◆ OverflowKind

Used to represent the possible overflow behavior of an operation.

Never: the operation cannot overflow. Always: the operation will always overflow. Sometime: the operation may or may not overflow.

Enumerator
OFK_Never 
OFK_Sometime 
OFK_Always 

Definition at line 2104 of file SelectionDAG.h.

Constructor & Destructor Documentation

◆ SelectionDAG() [1/2]

◆ SelectionDAG() [2/2]

llvm::SelectionDAG::SelectionDAG ( const SelectionDAG & )
delete

References SelectionDAG().

◆ ~SelectionDAG()

SelectionDAG::~SelectionDAG ( )

Definition at line 1389 of file SelectionDAG.cpp.

References assert().

Member Function Documentation

◆ addCalledGlobal()

void llvm::SelectionDAG::addCalledGlobal ( const SDNode * Node,
const GlobalValue * GV,
unsigned OpFlags )
inline

Set CalledGlobal to be associated with Node.

Definition at line 2538 of file SelectionDAG.h.

◆ addCallSiteInfo()

void llvm::SelectionDAG::addCallSiteInfo ( const SDNode * Node,
CallSiteInfo && CallInfo )
inline

Set CallSiteInfo to be associated with Node.

Definition at line 2501 of file SelectionDAG.h.

Referenced by llvm::RISCVTargetLowering::LowerCall().

◆ AddDbgLabel()

void SelectionDAG::AddDbgLabel ( SDDbgLabel * DB)

Add a dbg_label SDNode.

Definition at line 12686 of file SelectionDAG.cpp.

◆ AddDbgValue()

void SelectionDAG::AddDbgValue ( SDDbgValue * DB,
bool isParameter )

Add a dbg_value SDNode.

AddDbgValue - Add a dbg_value SDNode.

If SD is non-null that means the value is produced by SD.

Definition at line 12676 of file SelectionDAG.cpp.

References assert().

Referenced by handleDanglingVariadicDebugInfo(), salvageDebugInfo(), and transferDbgValues().

◆ addHeapAllocSite()

void llvm::SelectionDAG::addHeapAllocSite ( const SDNode * Node,
MDNode * MD )
inline

Set HeapAllocSite to be associated with Node.

Definition at line 2510 of file SelectionDAG.h.

◆ addMMRAMetadata()

void llvm::SelectionDAG::addMMRAMetadata ( const SDNode * Node,
MDNode * MMRA )
inline

Set MMRAMetadata to be associated with Node.

Definition at line 2523 of file SelectionDAG.h.

◆ addNoMergeSiteInfo()

void llvm::SelectionDAG::addNoMergeSiteInfo ( const SDNode * Node,
bool NoMerge )
inline

Set NoMergeSiteInfo to be associated with Node if NoMerge is true.

Definition at line 2550 of file SelectionDAG.h.

Referenced by llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), and llvm::SystemZTargetLowering::LowerCall().

◆ addPCSections()

void llvm::SelectionDAG::addPCSections ( const SDNode * Node,
MDNode * MD )
inline

Set PCSections to be associated with Node.

Definition at line 2519 of file SelectionDAG.h.

◆ allnodes() [1/2]

iterator_range< allnodes_iterator > llvm::SelectionDAG::allnodes ( )
inline

Definition at line 570 of file SelectionDAG.h.

References allnodes_begin(), allnodes_end(), and llvm::make_range().

Referenced by AssignTopologicalOrder(), dump(), and RemoveDeadNodes().

◆ allnodes() [2/2]

iterator_range< allnodes_const_iterator > llvm::SelectionDAG::allnodes ( ) const
inline

Definition at line 573 of file SelectionDAG.h.

References allnodes_begin(), allnodes_end(), and llvm::make_range().

◆ allnodes_begin() [1/2]

allnodes_iterator llvm::SelectionDAG::allnodes_begin ( )
inline

Definition at line 563 of file SelectionDAG.h.

◆ allnodes_begin() [2/2]

allnodes_const_iterator llvm::SelectionDAG::allnodes_begin ( ) const
inline

Definition at line 558 of file SelectionDAG.h.

Referenced by allnodes(), allnodes(), AssignTopologicalOrder(), and Legalize().

◆ allnodes_end() [1/2]

allnodes_iterator llvm::SelectionDAG::allnodes_end ( )
inline

Definition at line 564 of file SelectionDAG.h.

◆ allnodes_end() [2/2]

allnodes_const_iterator llvm::SelectionDAG::allnodes_end ( ) const
inline

Definition at line 559 of file SelectionDAG.h.

Referenced by allnodes(), allnodes(), and Legalize().

◆ allnodes_size()

ilist< SDNode >::size_type llvm::SelectionDAG::allnodes_size ( ) const
inline

Definition at line 566 of file SelectionDAG.h.

Referenced by AssignTopologicalOrder().

◆ areNonVolatileConsecutiveLoads()

bool SelectionDAG::areNonVolatileConsecutiveLoads ( LoadSDNode * LD,
LoadSDNode * Base,
unsigned Bytes,
int Dist ) const

Return true if loads are next to each other and can be merged.

Check that both are nonvolatile and if LD is loading 'Bytes' bytes from a location that is 'Dist' units away from the location that the 'Base' load is loading from.

Definition at line 13425 of file SelectionDAG.cpp.

References llvm::sampleprof::Base, llvm::EVT::getSizeInBits(), llvm::BaseIndexOffset::match(), and llvm::Offset.

Referenced by areLoadedOffsetButOtherwiseSame(), combineBVOfConsecutiveLoads(), combineINSERT_SUBVECTOR(), and EltsFromConsecutiveLoads().

◆ AssignTopologicalOrder()

unsigned SelectionDAG::AssignTopologicalOrder ( )

Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.

AssignTopologicalOrder - Assign a unique node id for each node in the DAG based on their topological order.

Returns the number of nodes.

It returns the maximum id and a vector of the SDNodes* in assigned order by reference.

Definition at line 12590 of file SelectionDAG.cpp.

References allnodes(), allnodes_begin(), allnodes_size(), assert(), llvm::checkForCycles(), llvm::dbgs(), llvm::SDNode::dumprFull(), llvm::ISD::EntryToken, I, llvm_unreachable, llvm::make_early_inc_range(), N, and P.

Referenced by Legalize().

◆ ByvalParmDbgBegin()

SDDbgInfo::DbgIterator llvm::SelectionDAG::ByvalParmDbgBegin ( ) const
inline

Definition at line 1994 of file SelectionDAG.h.

Referenced by dump().

◆ ByvalParmDbgEnd()

SDDbgInfo::DbgIterator llvm::SelectionDAG::ByvalParmDbgEnd ( ) const
inline

Definition at line 1997 of file SelectionDAG.h.

Referenced by dump().

◆ calculateDivergence()

bool SelectionDAG::calculateDivergence ( SDNode * N)

Definition at line 12460 of file SelectionDAG.cpp.

References assert(), gluePropagatesDivergence(), and N.

Referenced by updateDivergence().

◆ canCreateUndefOrPoison() [1/2]

bool SelectionDAG::canCreateUndefOrPoison ( SDValue Op,
bool PoisonOnly = false,
bool ConsiderFlags = true,
unsigned Depth = 0 ) const

Return true if Op can create undef or poison from non-undef & non-poison operands.

ConsiderFlags controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)

Definition at line 5637 of file SelectionDAG.cpp.

References canCreateUndefOrPoison(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), and PoisonOnly.

◆ canCreateUndefOrPoison() [2/2]

bool SelectionDAG::canCreateUndefOrPoison ( SDValue Op,
const APInt & DemandedElts,
bool PoisonOnly = false,
bool ConsiderFlags = true,
unsigned Depth = 0 ) const

Return true if Op can create undef or poison from non-undef & non-poison operands.

The DemandedElts argument limits the check to the requested vector elements.

ConsiderFlags controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)

Definition at line 5648 of file SelectionDAG.cpp.

References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::AssertAlign, llvm::ISD::AssertNoFPClass, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::cast(), computeKnownBits(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::Depth, llvm::enumerate(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FREEZE, llvm::ISD::FREM, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FSUB, llvm::KnownBits::getMaxValue(), getTarget(), getValidMaximumShiftAmount(), llvm::EVT::getVectorMinNumElements(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, isKnownNeverZero(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::TargetMachine::Options, Options, llvm::ISD::OR, llvm::ISD::PARITY, PoisonOnly, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::ISD::SADDSAT, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SCMP, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UADDSAT, llvm::ISD::UCMP, llvm::APInt::uge(), llvm::APInt::ugt(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::USUBSAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.

Referenced by canCreateUndefOrPoison(), and isGuaranteedNotToBeUndefOrPoison().

◆ cannotBeOrderedNegativeFP()

bool SelectionDAG::cannotBeOrderedNegativeFP ( SDValue Op) const

Test whether the given float value is known to be positive.

+0.0, +inf and +nan are considered positive, -0.0, -inf and -nan are not.

Definition at line 6205 of file SelectionDAG.cpp.

References llvm::isConstOrConstSplatFP().

◆ canonicalizeCommutativeBinop()

void SelectionDAG::canonicalizeCommutativeBinop ( unsigned Opcode,
SDValue & N1,
SDValue & N2 ) const

Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order.

Definition at line 7597 of file SelectionDAG.cpp.

References llvm::SDValue::getOpcode(), isConstantFPBuildVectorOrConstantFP(), isConstantIntBuildVectorOrConstantInt(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, and std::swap().

Referenced by getNode(), and getNode().

◆ clear()

void SelectionDAG::clear ( )

Clear state and free memory necessary to make this SelectionDAG ready to process a new block.

Definition at line 1450 of file SelectionDAG.cpp.

References llvm::fill(), and getEntryNode().

◆ clearGraphAttrs()

void SelectionDAG::clearGraphAttrs ( )

Clear all previously defined node graph attributes.

clearGraphAttrs - Clear all previously defined node graph attributes.

Intended to be used from a debugging tool (eg. gdb).

Definition at line 179 of file SelectionDAGPrinter.cpp.

References llvm::errs().

◆ Combine()

void SelectionDAG::Combine ( CombineLevel Level,
BatchAAResults * BatchAA,
CodeGenOptLevel OptLevel )

This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.

This is the entry point for the file.

The Level argument controls whether Combine is allowed to produce nodes and types that are illegal on the target.

This is the main entry point to this class.

Definition at line 30260 of file DAGCombiner.cpp.

◆ computeKnownBits() [1/2]

KnownBits SelectionDAG::computeKnownBits ( SDValue Op,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

Determine which bits of Op are known to be either zero or one and return them in Known.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.

Definition at line 3384 of file SelectionDAG.cpp.

References llvm::ISD::ABDS, llvm::KnownBits::abds(), llvm::ISD::ABDU, llvm::KnownBits::abdu(), llvm::ISD::ABS, llvm::KnownBits::abs(), llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::KnownBits::anyext(), llvm::KnownBits::ashr(), assert(), llvm::ISD::AssertAlign, llvm::ISD::AssertZext, llvm::ISD::AVGCEILS, llvm::KnownBits::avgCeilS(), llvm::ISD::AVGCEILU, llvm::KnownBits::avgCeilU(), llvm::ISD::AVGFLOORS, llvm::KnownBits::avgFloorS(), llvm::ISD::AVGFLOORU, llvm::KnownBits::avgFloorU(), llvm::bit_width(), llvm::ISD::BITREVERSE, llvm::BitWidth, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::KnownBits::byteSwap(), llvm::CallingConv::C, llvm::cast(), llvm::APInt::clearAllBits(), llvm::APInt::clearBit(), llvm::APInt::clearBits(), llvm::APInt::clearLowBits(), llvm::KnownBits::computeForAddCarry(), llvm::KnownBits::computeForAddSub(), llvm::KnownBits::computeForSubBorrow(), computeKnownBits(), llvm::computeKnownBitsFromRangeMetadata(), ComputeNumSignBits(), llvm::KnownBits::concat(), llvm::ISD::CONCAT_VECTORS, llvm::APInt::countl_zero(), llvm::KnownBits::countMaxLeadingZeros(), llvm::KnownBits::countMaxPopulation(), llvm::KnownBits::countMaxTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::Depth, llvm::dyn_cast(), llvm::enumerate(), llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::KnownBits::extractBits(), F, llvm::ISD::FGETSIGN, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FrameIndex, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::Constant::getAggregateElement(), llvm::getAlign(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitsSetFrom(), llvm::APInt::getBitWidth(), llvm::KnownBits::getBitWidth(), getDataLayout(), llvm::MachineFunction::getFunction(), llvm::APInt::getHiBits(), llvm::APInt::getLowBitsSet(), getMachineFunction(), llvm::ShuffleVectorSDNode::getMask(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::getShuffleDemandedElts(), llvm::EVT::getSizeInBits(), llvm::Constant::getSplatValue(), llvm::Value::getType(), llvm::ConstantRange::getUnsignedMax(), getValidMinimumShiftAmount(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::getVScaleRange(), I, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::KnownBits::insertBits(), llvm::KnownBits::intersectWith(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::ISD::isEXTLoad(), llvm::EVT::isFloatingPoint(), isGuaranteedNotToBeUndefOrPoison(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::APInt::isNegative(), llvm::KnownBits::isNegative(), llvm::ISD::isNON_EXTLoad(), llvm::APInt::isNonNegative(), llvm::KnownBits::isNonNegative(), llvm::KnownBits::isNonZero(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalableVector(), llvm::ISD::isSEXTLoad(), llvm::isUIntN(), llvm::KnownBits::isUnknown(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::ISD::isZEXTLoad(), llvm::Log2(), llvm::APInt::logBase2(), llvm::KnownBits::lshr(), llvm::KnownBits::makeConstant(), llvm::KnownBits::makeNegative(), llvm::KnownBits::makeNonNegative(), MaxRecursionDepth, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::KnownBits::mul(), llvm::ISD::MULHS, llvm::KnownBits::mulhs(), llvm::ISD::MULHU, llvm::KnownBits::mulhu(), llvm::ConstantRange::multiply(), llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::KnownBits::One, llvm::ISD::OR, llvm::ISD::PARITY, llvm::KnownBits::resetAll(), llvm::KnownBits::reverseBits(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::APInt::rotr(), llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::ISD::SCALAR_TO_VECTOR, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SDIV, llvm::KnownBits::sdiv(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::KnownBits::setAllConflict(), llvm::KnownBits::setAllZero(), llvm::APInt::setBit(), llvm::APInt::setBitsFrom(), llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::KnownBits::sext(), llvm::KnownBits::sextInReg(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::APInt::shl(), llvm::KnownBits::shl(), llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::ISD::SMAX, llvm::KnownBits::smax(), llvm::ISD::SMIN, llvm::KnownBits::smin(), llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::Splat, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SPLAT_VECTOR_PARTS, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::KnownBits::srem(), llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STEP_VECTOR, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, llvm::Sub, llvm::ISD::SUBC, std::swap(), llvm::ISD::TargetFrameIndex, llvm::ConstantRange::toKnownBits(), llvm::KnownBits::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UDIV, llvm::KnownBits::udiv(), llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::KnownBits::umax(), llvm::ISD::UMIN, llvm::KnownBits::umin(), llvm::ISD::UMUL_LOHI, llvm::APInt::umul_ov(), umul_ov(), llvm::ISD::UMULO, llvm::KnownBits::unionWith(), llvm::ISD::UREM, llvm::KnownBits::urem(), llvm::KnownBits::usub_sat(), llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::USUBSAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, llvm::APInt::zext(), llvm::KnownBits::zext(), llvm::ISD::ZEXTLOAD, and llvm::KnownBits::zextOrTrunc().

◆ computeKnownBits() [2/2]

KnownBits SelectionDAG::computeKnownBits ( SDValue Op,
unsigned Depth = 0 ) const

Determine which bits of Op are known to be either zero or one and return them in Known.

For vectors, the known bits are those that are shared by every vector element. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.

For vectors, the known bits are those that are shared by every vector element.

Definition at line 3369 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

Referenced by adjustForRedundantAnd(), llvm::TargetLowering::BuildUDIV(), canCreateUndefOrPoison(), checkDot4MulSignedness(), checkZExtBool(), combineArithReduction(), combineFaddCFmul(), combineFMulcFCMulc(), combineMOVMSK(), combineMul(), combinePMULH(), combineSCALAR_TO_VECTOR(), combineSetCC(), combineShiftToAVG(), combineVPMADD52LH(), computeKnownBits(), computeKnownBits(), computeKnownBitsBinOp(), computeKnownBitsForHorizontalOperation(), computeKnownBitsForPMADDUBSW(), computeKnownBitsForPMADDWD(), computeKnownBitsForPRMT(), computeKnownBitsForPSADBW(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::SITargetLowering::computeKnownBitsForTargetNode(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), computeOverflowForSignedMul(), computeOverflowForSignedSub(), computeOverflowForUnsignedAdd(), computeOverflowForUnsignedMul(), computeOverflowForUnsignedSub(), detectExtMul(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandFixedPointDiv(), getPack(), getValidShiftAmountRange(), haveNoCommonBitsSet(), isBitfieldPositioningOp(), isKnownNeverZero(), isSafeSignedCMN(), isTruncateOf(), isWordAligned(), LowerAndToBT(), LowerAndToBTST(), LowerCTPOP(), LowerMUL(), llvm::SITargetLowering::lowerSET_ROUNDING(), LowerShift(), lowerShuffleWithVPMOV(), LowerVectorAllEqual(), MaskedValueIsAllOnes(), MaskedValueIsZero(), MaskedValueIsZero(), MaskedVectorIsZero(), matchBinaryShuffle(), matchTruncateWithPACK(), matchVPMADD52(), narrowIndex(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), performANDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performORCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSIGN_EXTEND_INREGCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performUADDVCombine(), provablyDisjointOr(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().

◆ ComputeMaxSignificantBits() [1/2]

unsigned SelectionDAG::ComputeMaxSignificantBits ( SDValue Op,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

Get the upper bound on bit size for this Value Op as a signed integer.

i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.

Definition at line 5404 of file SelectionDAG.cpp.

References ComputeNumSignBits(), and llvm::Depth.

◆ ComputeMaxSignificantBits() [2/2]

unsigned SelectionDAG::ComputeMaxSignificantBits ( SDValue Op,
unsigned Depth = 0 ) const

Get the upper bound on bit size for this Value Op as a signed integer.

i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.

Definition at line 5398 of file SelectionDAG.cpp.

References ComputeNumSignBits(), and llvm::Depth.

Referenced by combineConcatVectorOps(), combineMulToPMADDWD(), combinePMULH(), detectExtMul(), EmitCmp(), llvm::TargetLowering::expandMUL_LOHI(), getPack(), lowerBuildVectorOfConstants(), llvm::AMDGPUTargetLowering::numBitsSigned(), and llvm::TargetLowering::SimplifyDemandedBits().

◆ ComputeNumSignBits() [1/2]

unsigned SelectionDAG::ComputeNumSignBits ( SDValue Op,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

Return the number of times the sign bit of the register is replicated into the other bits.

We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. The DemandedElts argument allows us to only collect the minimum sign bits of the requested vector elements. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.

Definition at line 4725 of file SelectionDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::AVGCEILS, llvm::ISD::AVGFLOORS, llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::CallingConv::C, llvm::cast(), llvm::APInt::clearBit(), llvm::APInt::clearBits(), computeKnownBits(), ComputeNumSignBits(), llvm::ISD::CONCAT_VECTORS, llvm::KnownBits::countMinSignBits(), llvm::Depth, llvm::dyn_cast(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FP_TO_SINT_SAT, llvm::Constant::getAggregateElement(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::ConstantRange::getBitWidth(), llvm::getConstantRangeFromMetadata(), getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::getShuffleDemandedElts(), llvm::ConstantRange::getSignedMax(), llvm::ConstantRange::getSignedMin(), getValidMinimumShiftAmount(), getValidShiftAmountRange(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::ISD::isExtOpcode(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::KnownBits::isNonNegative(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), MaxRecursionDepth, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ConstantRange::signExtend(), llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, llvm::Sub, std::swap(), T, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ConstantRange::zeroExtend(), llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.

◆ ComputeNumSignBits() [2/2]

unsigned SelectionDAG::ComputeNumSignBits ( SDValue Op,
unsigned Depth = 0 ) const

Return the number of times the sign bit of the register is replicated into the other bits.

We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.

Definition at line 4713 of file SelectionDAG.cpp.

References ComputeNumSignBits(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

Referenced by canReduceVMulWidth(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineBitOpWithPACK(), combineGatherScatter(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMulToPMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineSelect(), combineSetCCMOVMSK(), combineShiftToAVG(), combineSIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), ComputeMaxSignificantBits(), ComputeMaxSignificantBits(), ComputeNumSignBits(), ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::AArch64TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), computeOverflowForSignedAdd(), computeOverflowForSignedMul(), computeOverflowForSignedSub(), EmitCmp(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandFixedPointDiv(), foldAddSubMasked1(), getFauxShuffleMask(), getNode(), isS16(), LowerADDSAT_SUBSAT(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), LowerEXTEND_VECTOR_INREG(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerShiftByScalarImmediate(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerVectorIntrinsicScalars(), LowerVSETCC(), matchBinaryShuffle(), matchShuffleWithPACK(), matchTruncateWithPACK(), matchUnaryShuffle(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performVectorShiftCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), selectUmullSmull(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode().

◆ computeOverflowForAdd()

OverflowKind llvm::SelectionDAG::computeOverflowForAdd ( bool IsSigned,
SDValue N0,
SDValue N1 ) const
inline

Determine if the result of the addition of 2 nodes can overflow.

Definition at line 2119 of file SelectionDAG.h.

References computeOverflowForSignedAdd(), and computeOverflowForUnsignedAdd().

Referenced by willNotOverflowAdd().

◆ computeOverflowForMul()

OverflowKind llvm::SelectionDAG::computeOverflowForMul ( bool IsSigned,
SDValue N0,
SDValue N1 ) const
inline

Determine if the result of the mul of 2 nodes can overflow.

Definition at line 2159 of file SelectionDAG.h.

References computeOverflowForSignedMul(), and computeOverflowForUnsignedMul().

Referenced by willNotOverflowMul().

◆ computeOverflowForSignedAdd()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedAdd ( SDValue N0,
SDValue N1 ) const

Determine if the result of the signed addition of 2 nodes can overflow.

Definition at line 4508 of file SelectionDAG.cpp.

References ComputeNumSignBits(), llvm::isNullConstant(), OFK_Never, and OFK_Sometime.

Referenced by computeOverflowForAdd().

◆ computeOverflowForSignedMul()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedMul ( SDValue N0,
SDValue N1 ) const

◆ computeOverflowForSignedSub()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedSub ( SDValue N0,
SDValue N1 ) const

Determine if the result of the signed sub of 2 nodes can overflow.

Definition at line 4546 of file SelectionDAG.cpp.

References computeKnownBits(), ComputeNumSignBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::signedSubMayOverflow().

Referenced by computeOverflowForSub().

◆ computeOverflowForSub()

OverflowKind llvm::SelectionDAG::computeOverflowForSub ( bool IsSigned,
SDValue N0,
SDValue N1 ) const
inline

Determine if the result of the sub of 2 nodes can overflow.

Definition at line 2139 of file SelectionDAG.h.

References computeOverflowForSignedSub(), and computeOverflowForUnsignedSub().

Referenced by willNotOverflowSub().

◆ computeOverflowForUnsignedAdd()

◆ computeOverflowForUnsignedMul()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedMul ( SDValue N0,
SDValue N1 ) const

Determine if the result of the unsigned mul of 2 nodes can overflow.

Definition at line 4577 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), llvm::isOneConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::unsignedMulMayOverflow().

Referenced by computeOverflowForMul().

◆ computeOverflowForUnsignedSub()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedSub ( SDValue N0,
SDValue N1 ) const

Determine if the result of the unsigned sub of 2 nodes can overflow.

Definition at line 4564 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::unsignedSubMayOverflow().

Referenced by computeOverflowForSub().

◆ computeVectorKnownZeroElements()

APInt SelectionDAG::computeVectorKnownZeroElements ( SDValue Op,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

◆ copyExtraInfo()

◆ CreateStackTemporary() [1/3]

SDValue SelectionDAG::CreateStackTemporary ( EVT VT,
unsigned minAlign = 1 )

Create a stack temporary, suitable for holding the specified value type.

If minAlign is specified, the slot size will have at least that alignment.

Definition at line 2739 of file SelectionDAG.cpp.

References CreateStackTemporary(), getContext(), getDataLayout(), getPrefTypeAlign(), llvm::EVT::getStoreSize(), and llvm::EVT::getTypeForEVT().

◆ CreateStackTemporary() [2/3]

SDValue SelectionDAG::CreateStackTemporary ( EVT VT1,
EVT VT2 )

◆ CreateStackTemporary() [3/3]

◆ DbgBegin()

SDDbgInfo::DbgIterator llvm::SelectionDAG::DbgBegin ( ) const
inline

Definition at line 1991 of file SelectionDAG.h.

Referenced by dump().

◆ DbgEnd()

SDDbgInfo::DbgIterator llvm::SelectionDAG::DbgEnd ( ) const
inline

Definition at line 1992 of file SelectionDAG.h.

Referenced by dump().

◆ DbgLabelBegin()

SDDbgInfo::DbgLabelIterator llvm::SelectionDAG::DbgLabelBegin ( ) const
inline

Definition at line 2001 of file SelectionDAG.h.

◆ DbgLabelEnd()

SDDbgInfo::DbgLabelIterator llvm::SelectionDAG::DbgLabelEnd ( ) const
inline

Definition at line 2004 of file SelectionDAG.h.

◆ DeleteNode()

void SelectionDAG::DeleteNode ( SDNode * N)

Remove the specified node from the system.

This node must have no referrers.

Definition at line 1088 of file SelectionDAG.cpp.

References N.

Referenced by Legalize().

◆ doesNodeExist()

bool SelectionDAG::doesNodeExist ( unsigned Opcode,
SDVTList VTList,
ArrayRef< SDValue > Ops )

Check if a node exists without modifying its flags.

doesNodeExist - Check if a node exists without modifying its flags.

Definition at line 11847 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddNodeIDNode(), llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.

Referenced by EmitCmp(), llvm::TargetLowering::expandIntMINMAX(), foldAndOrOfSETCC(), performCSELCombine(), and llvm::TargetLowering::SimplifySetCC().

◆ dump()

◆ dumpDotGraph()

LLVM_DUMP_METHOD void SelectionDAG::dumpDotGraph ( const Twine & FileName,
const Twine & Title )

Just dump dot graph to a user-provided path and title.

This doesn't open the dot viewer program and helps visualization when outside debugging session. FileName expects absolute path. If provided without any path separators then the file will be created in the current directory. Error will be emitted if the path is insane.

Definition at line 171 of file SelectionDAGPrinter.cpp.

References llvm::dumpDotGraphToFile(), and LLVM_DUMP_METHOD.

◆ expandMultipleResultFPLibCall()

◆ expandVAArg()

SDValue SelectionDAG::expandVAArg ( SDNode * Node)

◆ expandVACopy()

SDValue SelectionDAG::expandVACopy ( SDNode * Node)

Expand the specified ISD::VACOPY node as the Legalize pass would.

Definition at line 2679 of file SelectionDAG.cpp.

References llvm::cast(), getDataLayout(), getLoad(), getStore(), getTargetLoweringInfo(), and llvm::SDValue::getValue().

Referenced by LowerVACOPY().

◆ ExtractVectorElements()

◆ FoldConstantArithmetic()

SDValue SelectionDAG::FoldConstantArithmetic ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
ArrayRef< SDValue > Ops,
SDNodeFlags Flags = SDNodeFlags() )

Definition at line 6941 of file SelectionDAG.cpp.

References llvm::ISD::ABS, llvm::APInt::abs(), AbstractManglingParser< Derived, Alloc >::NumOps, AbstractManglingParser< Derived, Alloc >::Ops, llvm::APFloat::add(), llvm::all_of(), llvm::ISD::ANY_EXTEND, llvm::APInt::ashrInPlace(), assert(), llvm::APFloatBase::BFloat(), llvm::ISD::BITREVERSE, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::APInt::byteSwap(), llvm::CallingConv::C, llvm::cast(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::CONDCODE, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::APFloat::convert(), llvm::APFloat::convertFromAPInt(), llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, DL, llvm::dyn_cast(), llvm::ISD::FMA, llvm::ISD::FMAD, foldConstantFPMath(), FoldSTEP_VECTOR(), FoldSymbolOffset(), FoldValue(), FoldValueWithUndef(), llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FSHL, llvm::APIntOps::fshl(), llvm::ISD::FSHR, llvm::APIntOps::fshr(), llvm::APFloat::fusedMultiplyAdd(), getBitcast(), llvm::APInt::getBitWidth(), getBuildVector(), getConstant(), getConstantFP(), getContext(), getDataLayout(), llvm::TargetLoweringBase::getExtendForContent(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::EVT::getFltSemantics(), getNode(), getOpcode(), llvm::SDValue::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getSplatVector(), getStepVector(), getUNDEF(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), I, llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), llvm::isa(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::SDValue::isUndef(), isUndef(), llvm::EVT::isVector(), llvm::ISD::MUL, llvm::APFloat::multiply(), NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::APFloatBase::opInexact, llvm::APFloatBase::opInvalidOp, llvm::APFloatBase::opOK, llvm::peekThroughBitcasts(), llvm::APInt::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::BuildVectorSDNode::recastRawBits(), llvm::APInt::reverseBits(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardNegative, llvm::APFloatBase::rmTowardPositive, llvm::APFloatBase::rmTowardZero, SDValue(), llvm::ISD::SETCC, llvm::APInt::sextOrTrunc(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::TargetLoweringBase::TypeLegal, llvm::ISD::UINT_TO_FP, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().

Referenced by combineGatherScatter(), foldAddSubOfSignBit(), foldBinOpIntoSelectIfProfitable(), foldBinOpIntoSelectIfProfitable(), getNode(), getNode(), getNode(), getTargetVShiftByConstNode(), getTargetVShiftNode(), LowerRotate(), PromoteMaskArithmetic(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyDemandedVectorElts().

◆ FoldConstantBuildVector()

◆ foldConstantFPMath()

◆ FoldSetCC()

◆ FoldSymbolOffset()

◆ getAddrSpaceCast()

◆ getAllOnesConstant()

SDValue SelectionDAG::getAllOnesConstant ( const SDLoc & DL,
EVT VT,
bool IsTarget = false,
bool IsOpaque = false )

Definition at line 1795 of file SelectionDAG.cpp.

References DL, llvm::APInt::getAllOnes(), getConstant(), and llvm::EVT::getScalarSizeInBits().

Referenced by combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAndLoadToBZHI(), combineBitcastToBoolVector(), combineMinMaxReduction(), combinePTESTCC(), combineSelectToBinOp(), combineSetCC(), combineSetCCMOVMSK(), combineVectorCompare(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), ConvertCarryValueToCarryFlag(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTTZ(), expandVPFunnelShift(), foldBoolSelectToLogic(), foldSubCtlzNot(), foldXorTruncShiftIntoCmp(), getBoolConstant(), getNeutralElement(), getNode(), getNOT(), getOnesVector(), getTargetVShiftNode(), getWideningInterleave(), isConditionalZeroOrAllOnes(), isConditionalZeroOrAllOnes(), LowerADDSUBO_CARRY(), LowerBUILD_VECTORvXi1(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), lowerSelectToBinOp(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), LowerSIGN_EXTEND_Mask(), llvm::HexagonTargetLowering::LowerUAddSubO(), LowerVectorAllEqual(), LowerVSETCC(), MatchVectorAllEqualTest(), performAddCSelIntoCSinc(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSIGN_EXTEND_INREGCombine(), performSignExtendInRegCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), ReplaceATOMIC_LOAD_128Results(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), and simplifySetCCWithCTPOP().

◆ getAnyExtOrTrunc()

◆ getAssertAlign()

◆ getAtomic() [1/2]

SDValue SelectionDAG::getAtomic ( unsigned Opcode,
const SDLoc & dl,
EVT MemVT,
SDValue Chain,
SDValue Ptr,
SDValue Val,
MachineMemOperand * MMO )

◆ getAtomic() [2/2]

◆ getAtomicCmpSwap()

SDValue SelectionDAG::getAtomicCmpSwap ( unsigned Opcode,
const SDLoc & dl,
EVT MemVT,
SDVTList VTs,
SDValue Chain,
SDValue Ptr,
SDValue Cmp,
SDValue Swp,
MachineMemOperand * MMO )

Gets a node for an atomic cmpxchg op.

There are two valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, a success flag (initially i1), and a chain.

Definition at line 9535 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), getAtomic(), llvm::SDValue::getValueType(), and Ptr.

◆ getAtomicLoad()

SDValue SelectionDAG::getAtomicLoad ( ISD::LoadExtType ExtType,
const SDLoc & dl,
EVT MemVT,
EVT VT,
SDValue Chain,
SDValue Ptr,
MachineMemOperand * MMO )

◆ getAtomicMemcpy()

◆ getAtomicMemmove()

◆ getAtomicMemset()

◆ getBasicBlock()

SDValue SelectionDAG::getBasicBlock ( MachineBasicBlock * MBB)

Definition at line 2019 of file SelectionDAG.cpp.

References AddNodeIDNode(), llvm::ISD::BasicBlock, getVTList(), MBB, N, and SDValue().

Referenced by AddNodeIDCustom().

◆ getBFI()

BlockFrequencyInfo * llvm::SelectionDAG::getBFI ( ) const
inline

Definition at line 514 of file SelectionDAG.h.

◆ getBitcast()

SDValue SelectionDAG::getBitcast ( EVT VT,
SDValue V )

Return a bitcast using the SDLoc of the value operand, and casting to the provided type.

Use getNode to set a custom SDLoc.

Definition at line 2428 of file SelectionDAG.cpp.

References getNode().

Referenced by addShuffleForVecExtend(), adjustBitcastSrcVectorSSE1(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleVectorByLane(), canonicalizeShuffleWithOp(), combineAnd(), combineAndMaskToShift(), combineAndNotIntoANDNP(), combineAndnp(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBitcast(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBlendOfPermutes(), combineBROADCAST_LOAD(), combineCastedMaskArithmetic(), combineCMP(), combineCompareEqual(), combineCONCAT_VECTORS(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineConstantPoolLoads(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFMulcFCMulc(), combineFneg(), combineFP_EXTEND(), combineFP_ROUND(), combineHorizOpWithShuffle(), combineINSERT_SUBVECTOR(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMinMaxReduction(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combinePMULDQ(), combinePMULH(), combinePredicateReduction(), combinePTESTCC(), combineRedundantDWordShuffle(), combineSCALAR_TO_VECTOR(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCCMOVMSK(), combineShuffleOfBitcast(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorHADDSUB(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), combineXor(), constructDup(), convertIntLogicToFPLogic(), convertShiftLeftToScale(), createMMXBuildVector(), createVariablePermute(), EltsFromConsecutiveLoads(), expandBitCastF128ToI128(), expandBitCastI128ToF128(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandUINT_TO_FP(), ExtractBitFromMaskVector(), FixupMMXIntrinsicTypes(), FoldConstantArithmetic(), FoldConstantBuildVector(), FoldIntToFPToInt(), GeneratePerfectShuffle(), generateSToVPermutedForVecShuffle(), getAVX2GatherNode(), getBitcastedAnyExtOrTrunc(), getBitcastedSExtOrTrunc(), getBitcastedZExtOrTrunc(), getBuildDwordsVector(), getCanonicalConstSplat(), getConstVector(), getConstVector(), getCopyFromPartsVector(), getCopyToPartsVector(), getDataClassTest(), getDeinterleaveShiftAndTrunc(), getFlagsOfCmpZeroFori1(), getMaskNode(), getMemsetValue(), llvm::X86TargetLowering::getNegatedExpression(), getOnesVector(), getPack(), getScalarMaskingNode(), getScalarValueForVectorElement(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getv64i1Argument(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), getVShift(), getWideningInterleave(), getWideningSpread(), getZeroVector(), llvm::TargetLowering::IncrementMemoryAddress(), isHorizontalBinOp(), IsNOT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::SystemZTargetLowering::joinRegisterPartsIntoValue(), lower128BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerATOMIC_STORE(), LowerAVXExtend(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXbf16(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), LowerCTPOP(), LowerEXTEND_VECTOR_INREG(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFMINIMUM_FMAXIMUM(), llvm::SITargetLowering::LowerFormalArguments(), LowerFunnelShift(), LowerHorizontalByteSum(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), lowerLaneOp(), LowerLoad(), lowerMasksToReg(), LowerMUL(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsShift(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVTRUNC(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithUNPCK256(), lowerShuffleWithVPMOV(), LowerStore(), lowerSTOREVector(), LowerTruncateVecI1(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV16F32Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2I64Shuffle(), lowerV4F32Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV8F16Shuffle(), lowerV8F32Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsShift(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllEqual(), LowerVectorCTLZ_GFNI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), LowerVectorMatch(), LowerVSETCC(), LowervXi8MulWithUNPCK(), lowerVZIP(), lowerX86FPLogicOp(), matchPERM(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), packImage16bitOpsToDwords(), Passv64i1ArgInRegs(), performBITCASTCombine(), performBitcastCombine(), PerformBUILD_VECTORCombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMulCombine(), performSETCC_BITCASTCombine(), performUzpCombine(), performVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), processVCIXOperands(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), ReplaceBITCAST(), replaceLoadVector(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), scalarizeVectorStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), takeInexpensiveLog2(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryCombineNeonFcvtFP16ToI16(), tryWidenMaskForShuffle(), tryWidenMaskForShuffle(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), widenBuildVec(), and widenShuffleMask().

◆ getBitcastedAnyExtOrTrunc()

SDValue SelectionDAG::getBitcastedAnyExtOrTrunc ( SDValue Op,
const SDLoc & DL,
EVT VT )

Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it.

Definition at line 1509 of file SelectionDAG.cpp.

References assert(), DL, getAnyExtOrTrunc(), getBitcast(), llvm::EVT::getIntegerVT(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), and Size.

Referenced by getDWordFromOffset(), and matchPERM().

◆ getBitcastedSExtOrTrunc()

SDValue SelectionDAG::getBitcastedSExtOrTrunc ( SDValue Op,
const SDLoc & DL,
EVT VT )

Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it.

Definition at line 1524 of file SelectionDAG.cpp.

References assert(), DL, getBitcast(), llvm::MVT::getIntegerVT(), getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), and Size.

◆ getBitcastedZExtOrTrunc()

SDValue SelectionDAG::getBitcastedZExtOrTrunc ( SDValue Op,
const SDLoc & DL,
EVT VT )

Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it.

Definition at line 1539 of file SelectionDAG.cpp.

References assert(), DL, getBitcast(), llvm::MVT::getIntegerVT(), llvm::SDValue::getValueType(), getZExtOrTrunc(), llvm::EVT::isVector(), and Size.

◆ getBlockAddress()

SDValue SelectionDAG::getBlockAddress ( const BlockAddress * BA,
EVT VT,
int64_t Offset = 0,
bool isTarget = false,
unsigned TargetFlags = 0 )

◆ getBoolConstant()

◆ getBoolExtOrTrunc()

SDValue SelectionDAG::getBoolExtOrTrunc ( SDValue Op,
const SDLoc & SL,
EVT VT,
EVT OpVT )

Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.

Definition at line 1554 of file SelectionDAG.cpp.

References llvm::EVT::bitsLE(), getNode(), and llvm::ISD::TRUNCATE.

Referenced by combineCarryDiamond(), combineSelectAsExtAnd(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandUADDSUBO(), and llvm::TargetLowering::SimplifySetCC().

◆ getBuildVector() [1/2]

SDValue llvm::SelectionDAG::getBuildVector ( EVT VT,
const SDLoc & DL,
ArrayRef< SDUse > Ops )
inline

Return an ISD::BUILD_VECTOR node.

The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.

Definition at line 877 of file SelectionDAG.h.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BUILD_VECTOR, DL, and getNode().

◆ getBuildVector() [2/2]

SDValue llvm::SelectionDAG::getBuildVector ( EVT VT,
const SDLoc & DL,
ArrayRef< SDValue > Ops )
inline

Return an ISD::BUILD_VECTOR node.

The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.

Definition at line 868 of file SelectionDAG.h.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BUILD_VECTOR, DL, and getNode().

Referenced by adjustLoadValueTypeImpl(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), BuildExactUDIV(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineConcatVectorOfScalars(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineShuffleOfScalars(), combineStore(), combineToExtendBoolVectorInReg(), combineX86ShuffleChain(), CompactSwizzlableVector(), convertLocVTToValVT(), convertShiftLeftToScale(), ExtendToType(), extractSubVector(), extractSubVector(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), FoldConstantBuildVector(), GenerateFixedLengthSVETBL(), GenerateTBL(), getBuildDwordsVector(), getBuildVectorizedValue(), getBuildVectorSplat(), getConstant(), getConstVector(), getConstVector(), getCopyFromPartsVector(), getDWordFromOffset(), getGeneralPermuteNode(), getGFNICtrlMask(), llvm::TargetLowering::getNegatedExpression(), getStepVector(), getTargetVShiftNode(), getVectorShuffle(), incDecVectorConstant(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), lowerDisjointIndicesShuffle(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerINT_TO_FP_vXi64(), lowerLaneOp(), lowerMSABinaryBitImmIntr(), lowerMSASplatZExt(), LowerMUL(), LowerShift(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificExtension(), lowerShuffleWithPSHUFB(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerSTOREVector(), LowerTruncateVectorStore(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_VSHF(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_XVPERM(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLEAsVRGatherVX(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), LowervXi8MulWithUNPCK(), NormalizeBuildVector(), packImage16bitOpsToDwords(), padEltsToUndef(), PerformBUILD_VECTORCombine(), performBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performVECTOR_SHUFFLECombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), ReorganizeVector(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::SimplifyDemandedVectorElts(), SkipExtensionForVMULL(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), llvm::AMDGPUTargetLowering::splitVector(), takeInexpensiveLog2(), tryBuildVectorShuffle(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), UnrollVectorOp(), UnrollVectorOverflowOp(), unrollVectorShift(), widenBuildVec(), and widenVectorToPartType().

◆ getCalledGlobal()

std::optional< CalledGlobalInfo > llvm::SelectionDAG::getCalledGlobal ( const SDNode * Node)
inline

Return CalledGlobal associated with Node, or a nullopt if none exists.

Definition at line 2543 of file SelectionDAG.h.

References I.

◆ getCALLSEQ_END() [1/2]

◆ getCALLSEQ_END() [2/2]

SDValue llvm::SelectionDAG::getCALLSEQ_END ( SDValue Chain,
uint64_t Size1,
uint64_t Size2,
SDValue Glue,
const SDLoc & DL )
inline

Definition at line 1164 of file SelectionDAG.h.

References DL, getCALLSEQ_END(), and getIntPtrConstant().

◆ getCALLSEQ_START()

◆ getCallSiteInfo()

CallSiteInfo llvm::SelectionDAG::getCallSiteInfo ( const SDNode * Node)
inline

Return CallSiteInfo associated with Node, or a default if none exists.

Definition at line 2505 of file SelectionDAG.h.

References CallSiteInfo, and I.

◆ getCommutedVectorShuffle()

SDValue SelectionDAG::getCommutedVectorShuffle ( const ShuffleVectorSDNode & SV)

Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.

Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>

Definition at line 2313 of file SelectionDAG.cpp.

References llvm::ShuffleVectorSDNode::commuteMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and getVectorShuffle().

Referenced by lowerVECTOR_SHUFFLE().

◆ getCondCode()

◆ getConstant() [1/3]

SDValue SelectionDAG::getConstant ( const APInt & Val,
const SDLoc & DL,
EVT VT,
bool isTarget = false,
bool isOpaque = false )

Definition at line 1667 of file SelectionDAG.cpp.

References DL, and getConstant().

◆ getConstant() [2/3]

◆ getConstant() [3/3]

SDValue SelectionDAG::getConstant ( uint64_t Val,
const SDLoc & DL,
EVT VT,
bool isTarget = false,
bool isOpaque = false )

Create a ConstantSDNode wrapping a constant value.

If VT is a vector type, the constant is splatted into a BUILD_VECTOR.

If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal).

Definition at line 1661 of file SelectionDAG.cpp.

References DL, getConstant(), and llvm::EVT::getScalarSizeInBits().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), adjustForSubtraction(), adjustForTestUnderMask(), adjustICmpTruncate(), adjustSubwordCmp(), adjustZeroCmp(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), bitcastf32Toi32(), buildCallOperands(), BuildExactSDIV(), BuildExactUDIV(), BuildIntrinsicOp(), BuildIntrinsicOp(), BuildIntrinsicOp(), llvm::SITargetLowering::buildRSRC(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), canonicalizePRMTInput(), canonicalizeShuffleVectorByLane(), carryFlagToValue(), checkSignTestSetCCCombine(), clampDynamicVectorIndex(), combine_CC(), combine_CC(), combineAcrossLanesIntrinsic(), combineADC(), combineAdd(), combineAddOfBooleanXor(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndLoadToBZHI(), combineAndnp(), CombineANDShift(), combineAndXorSubWithBMI(), combineArithReduction(), combineAVG(), combineAVX512SetCCToKMOV(), CombineBaseUpdate(), combineBitcast(), combineBitcastToBoolVector(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineCONCAT_VECTORS(), combineConcatVectorOps(), combineDeMorganOfBoolean(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFP_EXTEND(), combineGatherScatter(), combinei64TruncSrlConstant(), combineKSHIFT(), combineM68kBrCond(), combineMinMaxReduction(), combineMOVMSK(), combineMul(), combineMulSpecial(), combineMulToPMADDWD(), combineMulWide(), combineOr(), combinePMULDQ(), combinePredicateReduction(), combinePRMT(), combinePTESTCC(), combineSCALAR_TO_VECTOR(), combineScalarAndWithMaskSetcc(), combineSelect(), llvm::VETargetLowering::combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineShlAddIAddImpl(), combineStore(), combineSub(), combineSubOfBoolean(), combineSubSetcc(), combineSVEPrefetchVecBaseImmOff(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), combineToExtendBoolVectorInReg(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUADDO_CARRYDiamond(), combineVectorCompare(), combineVectorMulToSraBitcast(), combineVectorShiftImm(), combineVectorShiftVar(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), CombineVMOVDRRCandidateWithVecOp(), combineVPMADD(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), combineX86AddSub(), combineX86ShuffleChain(), combineXorToBitfieldInsert(), constantFoldBFE(), constructDup(), constructRetValue(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), ConvertCarryFlagToCarryValue(), ConvertCarryValueToCarryFlag(), convertFixedMaskToScalableVector(), convertFromF16(), convertFromScalableVector(), convertShiftLeftToScale(), convertToF16(), convertToScalableVector(), convertValVTToLocVT(), CreateCopyOfByValArgument(), CreateCopyOfByValArgument(), CreateCopyOfByValArgument(), createFPCmp(), createLoadLR(), createPSADBW(), createSetFPEnvNodes(), createStoreLR(), createVariablePermute(), createVPDPBUSD(), llvm::TargetLowering::CTTZTableLookup(), customLegalizeToWOp(), EltsFromConsecutiveLoads(), EmitCMP(), emitConditionalComparison(), emitConstantSizeRepmov(), emitConstantSizeRepstos(), emitFloatCompareMask(), emitMemMemImm(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::RISCVSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), EmitTest(), emitVectorComparison(), Expand64BitShift(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), expandf64Toi32(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), expandFSH64(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIntMINMAX(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandIS_FPCLASS(), expandMul(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), expandMulToAddOrSubOfShl(), expandMulToNAFSequence(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZ(), llvm::TargetLowering::expandVPCTTZElements(), expandVPFunnelShift(), ExtendToType(), extractF64Exponent(), extractShiftForRotate(), finalizeTS1AM(), foldAddSubBoolOfMaskedVal(), foldAndOrOfSETCC(), foldAndToUsubsat(), FoldConstantArithmetic(), FoldConstantBuildVector(), foldCSELofCTTZ(), foldExtendedSignBitTest(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldReduceOperandViaVQDOT(), foldSelectOfConstantsUsingSra(), foldSelectOfCTTZOrCTLZ(), FoldSetCC(), foldSetCCWithFunnelShift(), FoldSTEP_VECTOR(), foldVectorXorShiftIntoCmp(), llvm::TargetLowering::forceExpandMultiply(), llvm::TargetLowering::forceExpandWideMUL(), genConstMult(), generateEquivalentSub(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAllOnesConstant(), getARMIndexedAddressParts(), getAVX512Node(), getBitTestCondition(), getBoolConstant(), getBoundedStrlen(), getBuildVectorSplat(), getCanonicalConstSplat(), getCCResult(), getCondCode(), getConstant(), getConstant(), getConstant(), getConstVector(), getConstVector(), llvm::RegsForValue::getCopyFromRegs(), getCSAddressAndShifts(), getDataClassTest(), getDefaultVLOps(), getDeinterleaveShiftAndTrunc(), getDWordFromOffset(), getElementCount(), GetExponent(), getFlagsOfCmpZeroFori1(), getGeneralPermuteNode(), getGFNICtrlMask(), llvm::AMDGPUTargetLowering::getHiHalf64(), getIntPtrConstant(), llvm::AMDGPUTargetLowering::getLoHalf64(), getMaskNode(), getMemBasePlusOffset(), getMemsetStringVal(), getMemsetValue(), getMVEIndexedAddressParts(), getNegative(), getNeutralElement(), getNode(), getNode(), getNode(), getPack(), getPMOVMSKB(), llvm::AVRTargetLowering::getPostIndexedAddressParts(), getPRMT(), getPRMT(), getPTest(), getPTrue(), getReductionSDNode(), getScaledOffsetForBitWidth(), getSETCC(), getSETCC(), getShiftAmountConstant(), getShuffleScalarElt(), getSignedConstant(), GetSignificand(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStepVector(), getSVEPredicateBitCast(), getT2IndexedAddressParts(), getTargetConstant(), getTargetConstant(), getTargetConstant(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getTruncatedUSUBSAT(), getUniformBase(), getVectorBitwiseReduce(), getVectorIdxConstant(), llvm::TargetLowering::getVectorSubVecPointer(), getVPZeroExtendInReg(), getVScale(), getWideningInterleave(), getWideningSpread(), getZeroExtendInReg(), getZeroVector(), getzOSCalleeAndADA(), incDecVectorConstant(), llvm::TargetLowering::IncrementMemoryAddress(), insert1BitVector(), IntCondCCodeToICC(), isConditionalZeroOrAllOnes(), isConditionalZeroOrAllOnes(), IsSingleInstrConstant(), legalizeIntrinsicImmArg(), llvm::AMDGPUTargetLowering::loadInputValue(), lower1BitShuffle(), LowerABS(), lowerAddrSpaceCast(), LowerADDSAT_SUBSAT(), LowerAndToBT(), LowerAndToBTST(), LowerAsSplatVectorLoad(), LowerATOMIC_FENCE(), LowerAVXExtend(), lowerBALLOTIntrinsic(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::LanaiTargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORToVIDUP(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv16i8(), lowerBuildVectorViaPacking(), lowerBuildVectorViaVID(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), lowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::lowerCTLZResults(), LowerCTPOP(), LowerCTPOP(), LowerCTTZ(), lowerCttzElts(), lowerDisjointIndicesShuffle(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), llvm::AMDGPUTargetLowering::LowerF64ToF16Safe(), lowerFABSorFNEG(), lowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), LowerFGETSIGN(), LowerFLDEXP(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), LowerFMINIMUM_FMAXIMUM(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP16_TO_FP(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), LowerFP_TO_INT_SAT(), lowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), LowerFunnelShift(), llvm::SITargetLowering::lowerGET_ROUNDING(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerGR128ToI128(), LowerHorizontalByteSum(), lowerI128ToGR128(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT_i1(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), lowerINT_TO_FP_vXi64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), LowerLabelRef(), lowerLaneOp(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), lowerLoadI1(), LowerMemOpCallTo(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSASplatImm(), lowerMSASplatZExt(), llvm::LanaiTargetLowering::LowerMUL(), LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), lowerOverflowArithmetic(), LowerPARITY(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), lowerPrmtIntrinsic(), lowerReductionSeq(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), lowerRETURNADDR(), LowerRotate(), LowerSaturatingConditional(), lowerScalarInsert(), lowerScalarSplat(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), lowerSelectToBinOp(), LowerSELECTWithCmpZero(), llvm::SITargetLowering::lowerSET_FPENV(), llvm::SITargetLowering::lowerSET_ROUNDING(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificExtension(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleWithEXPAND(), lowerShuffleWithPSHUFB(), LowerSIGN_EXTEND_Mask(), LowerSMELdrStr(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::NVPTXTargetLowering::LowerSTACKSAVE(), lowerStoreF128(), lowerStoreI1(), LowerSVEIntrinsicEXT(), LowerTruncatei1(), LowerTruncateVecI1(), LowerTruncateVectorStore(), LowerUADDSUBO_CARRY(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), llvm::VETargetLowering::lowerVAARG(), LowerVecReduce(), LowerVecReduceMinMax(), lowerVECTOR_COMPRESS(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), lowerVECTOR_SHUFFLE_XVPERM(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsShift(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllEqual(), lowerVectorBitClear(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZ_GFNI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), lowerVectorIntrinsicScalars(), LowerVectorMatch(), lowerVectorSplatImm(), LowerVSETCC(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowervXi8MulWithUNPCK(), lowerVZIP(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), matchMergedBFX(), matchPERM(), MatchVectorAllEqualTest(), memsetStore(), narrowIndex(), NormalizeBuildVector(), optimizeIncrementingWhile(), optimizeLogicalImm(), overflowFlagToValue(), llvm::SITargetLowering::passSpecialInputs(), performAddCSelIntoCSinc(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performAddSubIntoVectorOp(), performAddUADDVCombine(), performANDCombine(), performANDCombine(), performANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), performBITCASTCombine(), performBitcastCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), PerformCSETCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDSPShiftCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFP_TO_INT_SATCombine(), performFpToIntCombine(), performGlobalAddressCombine(), performInsertSubvectorCombine(), performINTRINSIC_WO_CHAINCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), performLDNT1Combine(), PerformLongShiftCombine(), PerformMinMaxCombine(), PerformMinMaxToSatCombine(), PerformMULCombine(), performMulCombine(), performMulVectorCmpZeroCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performORCombine(), performORCombine(), PerformORCombineToBFI(), PerformPREDICATE_CASTCombine(), performRNDRCombine(), performScalarToVectorCombine(), performSELECT_CCCombine(), performSetccAddFolding(), performSETCCCombine(), performSETCCCombine(), PerformShiftCombine(), performSHLCombine(), performSHLCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSHLSimplify(), PerformShuffleVMOVNCombine(), performSIGN_EXTEND_INREGCombine(), performSignExtendCombine(), performSPLIT_PAIR_F64Combine(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSRACombine(), llvm::AMDGPUTargetLowering::performSraCombine(), performSRLCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), PerformSUBCombine(), performSUBCombine(), performSubsToAndsCombine(), performSVEAndCombine(), performTBZCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), performUnpackCombine(), performUzpCombine(), PerformVCMPCombine(), PerformVCVTCombine(), PerformVDUPCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), performVECTOR_SHUFFLECombine(), performVectorDeinterleaveCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), PerformVMulVCTPCombine(), performVP_REVERSECombine(), performVP_STORECombine(), PerformVSELECTCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), PerformXORCombine(), performXORCombine(), performZExtDeinterleaveShuffleCombine(), performZExtUZPCombine(), prepareTS1AM(), promoteExtBeforeAdd(), reassociateCSELOperandsForCSE(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), refineUniformBase(), ReplaceBITCAST(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), replaceVPICKVE2GRResults(), resolveSources(), reverseZExtICmpCombine(), SaturateWidenedDIVFIX(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::LoongArchTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCIntoEq(), simplifySetCCWithCTPOP(), simplifyShift(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), llvm::AMDGPUTargetLowering::split64BitValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), SplitEVL(), splitStores(), splitStoreSplat(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::splitVector(), llvm::AMDGPUTargetLowering::storeStackInputValue(), takeInexpensiveLog2(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddShlImm(), TranslateM68kCC(), translateSetCCForBranch(), translateSetCCForBranch(), TranslateX86CC(), truncateVecElts(), truncateVecElts(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), TryCombineBaseUpdate(), tryCombineMULLWithUZP1(), tryCombineShiftImm(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), tryExtendDUPToExtractHigh(), tryFoldMADwithSRL(), tryFoldSelectIntoOp(), tryFoldToZero(), tryFormConcatFromShuffle(), TryMULWIDECombine(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), UnpackFromArgumentSlot(), UnrollVectorOverflowOp(), unrollVectorShift(), valueToCarryFlag(), llvm::X86TargetLowering::visitMaskedLoad(), widenBuildVec(), WidenVector(), and widenVectorOpsToi8().

◆ getConstantDbgValue()

SDDbgValue * SelectionDAG::getConstantDbgValue ( DIVariable * Var,
DIExpression * Expr,
const Value * C,
const DebugLoc & DL,
unsigned O )

Creates a constant SDDbgValue node.

Constant.

Definition at line 11874 of file SelectionDAG.cpp.

References assert(), llvm::CallingConv::C, llvm::cast(), DL, and llvm::SDDbgOperand::fromConst().

◆ getConstantFP() [1/3]

SDValue SelectionDAG::getConstantFP ( const APFloat & Val,
const SDLoc & DL,
EVT VT,
bool isTarget = false )

Definition at line 1824 of file SelectionDAG.cpp.

References DL, getConstantFP(), and getContext().

◆ getConstantFP() [2/3]

◆ getConstantFP() [3/3]

SDValue SelectionDAG::getConstantFP ( double Val,
const SDLoc & DL,
EVT VT,
bool isTarget = false )

Create a ConstantFPSDNode wrapping a constant value.

If VT is a vector type, the constant is splatted into a BUILD_VECTOR.

If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal). The forms that take a double should only be used for simple constants that can be exactly represented in VT. No checks are made.

Definition at line 1868 of file SelectionDAG.cpp.

References llvm::APFloat::convert(), DL, getConstantFP(), llvm::EVT::getFltSemantics(), llvm::EVT::getScalarType(), llvm_unreachable, and llvm::APFloatBase::rmNearestTiesToEven.

Referenced by combineBitcast(), combineExtractWithShuffle(), combineFneg(), combineFP_ROUND(), combineVSelectWithAllOnesOrZeros(), EltsFromConsecutiveLoads(), expandExp(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), expandFP_TO_UINT_SSE(), llvm::TargetLowering::expandIS_FPCLASS(), expandLog(), ExpandPowI(), llvm::TargetLowering::expandUINT_TO_FP(), FoldConstantArithmetic(), foldConstantFPMath(), getConstantFP(), getConstantFP(), getF32Constant(), getInvertedVectorForFMA(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getMemsetValue(), llvm::TargetLowering::getNegatedExpression(), getNeutralElement(), getNode(), getNode(), getRVVFPReductionOpAndOperands(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getShuffleScalarElt(), llvm::TargetLowering::getSqrtInputTest(), llvm::TargetLowering::getSqrtResultForDenormInput(), getTargetConstantFP(), getTargetConstantFP(), getTargetConstantFP(), getZeroVector(), LowerFABSorFNEG(), LowerFCanonicalize(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFLOG2(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), llvm::AMDGPUTargetLowering::LowerFLOGUnsafe(), LowerFMINIMUM_FMAXIMUM(), LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), lowerFREM(), llvm::AMDGPUTargetLowering::LowerFROUND(), LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerShuffleAsBitMask(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performInsertSubvectorCombine(), llvm::AMDGPUTargetLowering::performRcpCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyFPBinop(), and strictFPExtFromF16().

◆ getConstantPool() [1/2]

◆ getConstantPool() [2/2]

SDValue SelectionDAG::getConstantPool ( MachineConstantPoolValue * C,
EVT VT,
MaybeAlign Align = std::nullopt,
int Offs = 0,
bool isT = false,
unsigned TargetFlags = 0 )

◆ getContext()

LLVMContext * llvm::SelectionDAG::getContext ( ) const
inline

Definition at line 511 of file SelectionDAG.h.

Referenced by AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), canCombineShuffleToExtendVectorInreg(), canFoldInAddressingMode(), checkIntrinsicImmArg(), CollectOpsToWiden(), combineAdd(), combineAnd(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFMinNumFMaxNum(), combineFP_EXTEND(), combineFP_ROUND(), combinei64TruncSrlConstant(), combineLoad(), combineMinNumMaxNumImpl(), combineOr(), combinePMULH(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineShiftAnd1ToBitTest(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineUIntToFP(), combineVectorMulToSraBitcast(), combineVectorSizedSetCCEquality(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), concatSubVectors(), constructRetValue(), convertIntLogicToFPLogic(), createPSADBW(), CreateStackTemporary(), CreateStackTemporary(), llvm::TargetLowering::CTTZTableLookup(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), emitErrorAndReplaceIntrinsicResults(), emitFloatCompareMask(), emitIntrinsicErrorMessage(), emitIntrinsicWithChainErrorMessage(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), emitSMEStateSaveRestore(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), emitVectorComparison(), errorUnsupported(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), expandMultipleResultFPLibCall(), llvm::TargetLowering::expandPartialReduceMLA(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZElements(), extractSubVector(), extractSubVector(), fail(), findMemType(), FoldConstantArithmetic(), FoldConstantBuildVector(), foldExtendVectorInregToExtendOfSubvector(), foldShuffleOfConcatUndefs(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), GenerateFixedLengthSVETBL(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getBuildVectorizedValue(), getConstant(), getConstantFP(), getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), GetDependentSplitDestVTs(), getEVTAlign(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getLargeExternalSymbol(), getMemcmp(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), getPrefTypeAlign(), getPrefTypeAlign(), getPTest(), getReducedAlign(), getRegistersForValue(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getSplatValue(), GetSplitDestVTs(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::TargetLowering::getSqrtInputTest(), getStrlen(), GetTLSADDR(), getUniformBase(), getVectorBitwiseReduce(), llvm::TargetLowering::getVectorElementPointer(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), isSaturatingMinMax(), isUpperSubvectorUndef(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), legalizeIntrinsicImmArg(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), lowerBitreverseShuffle(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), lowerFCMPIntrinsic(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFMINIMUM_FMAXIMUM(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerICMPIntrinsic(), lowerLaneOp(), LowerMSCATTER(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::NVPTXTargetLowering::LowerSTACKRESTORE(), llvm::NVPTXTargetLowering::LowerSTACKSAVE(), LowerStore(), lowerSTOREVector(), LowerSVEIntrinsicEXT(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToVVP(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorExtend(), lowerVectorSplatImm(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_LOAD_STORE(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), makeStateFunctionCall(), matchBinOpReduction(), matchPMADDWD(), matchPMADDWD_2(), narrowExtractedVectorBinOp(), narrowIndex(), PerformARMBUILD_VECTORCombine(), performBITCASTCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformExtractFpToIntStores(), PerformInsertEltCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformMinMaxFpToSatCombine(), performMulVectorCmpZeroCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performSelectCombine(), performSETCC_BITCASTCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSignExtendInRegCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), performSunpkloCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), performVecReduceAddCombine(), performVECTOR_SHUFFLECombine(), performVectorExtCombine(), PromoteBinOpToF32(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), replaceAtomicSwap128(), replaceLoadVector(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceProxyReg(), reverseZExtICmpCombine(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), shouldTransformMulToShiftsAddsSubs(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), skipExtensionForVectorMULL(), llvm::TargetLowering::softenSetCCOperands(), splitStores(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), splitVector(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryCombineMULLWithUZP1(), tryFormConcatFromShuffle(), UnrollVectorOp(), UnrollVectorOverflowOp(), widenAbs(), widenBuildVec(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), and WidenVector().

◆ getCopyFromReg() [1/2]

SDValue llvm::SelectionDAG::getCopyFromReg ( SDValue Chain,
const SDLoc & dl,
Register Reg,
EVT VT )
inline

Definition at line 839 of file SelectionDAG.h.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::CopyFromReg, getNode(), getRegister(), getVTList(), and Reg.

Referenced by llvm::AArch64TargetLowering::changeStreamingMode(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), emitSMEStateSaveRestore(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyFromRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFRAMEADDR(), getReadTimeStampCounter(), GetTLSADDR(), getv64i1Argument(), getzOSCalleeAndADA(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBALLOTIntrinsic(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), lowerCallResult(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::SITargetLowering::LowerSTACKSAVE(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), performDivRemCombine(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::AMDGPUTargetLowering::storeStackInputValue(), unpack64(), unpackF64OnLA32DSoftABI(), unpackF64OnRV32DSoftABI(), unpackFromRegLoc(), unpackFromRegLoc(), and unpackFromRegLoc().

◆ getCopyFromReg() [2/2]

SDValue llvm::SelectionDAG::getCopyFromReg ( SDValue Chain,
const SDLoc & dl,
Register Reg,
EVT VT,
SDValue Glue )
inline

◆ getCopyToReg() [1/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue Chain,
const SDLoc & dl,
Register Reg,
SDValue N )
inline

Definition at line 813 of file SelectionDAG.h.

References llvm::ISD::CopyToReg, getNode(), getRegister(), N, and Reg.

Referenced by emitRepmovs(), emitRepstos(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyToRegs(), llvm::MipsTargetLowering::getOpndList(), GetTLSADDR(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::SITargetLowering::PostISelFolding(), prepareDescriptorIndirectCall(), and llvm::X86TargetLowering::ReplaceNodeResults().

◆ getCopyToReg() [2/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue Chain,
const SDLoc & dl,
Register Reg,
SDValue N,
SDValue Glue )
inline

◆ getCopyToReg() [3/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue Chain,
const SDLoc & dl,
SDValue Reg,
SDValue N,
SDValue Glue )
inline

◆ getDataLayout()

const DataLayout & llvm::SelectionDAG::getDataLayout ( ) const
inline

Definition at line 498 of file SelectionDAG.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), analyzeCallOperands(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), BuildExactUDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), canFoldInAddressingMode(), combineBVOfVecSExt(), combineConcatVectorOps(), combineFMinNumFMaxNum(), combineGatherScatter(), combineLoad(), combinePredicateReduction(), combineShiftAnd1ToBitTest(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineStore(), combineTargetShuffle(), combineTruncationShuffle(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), createGPRPairNode(), createGPRPairNodei64(), createMMXBuildVector(), createSetFPEnvNodes(), CreateStackTemporary(), CreateStackTemporary(), CreateStackTemporary(), llvm::TargetLowering::CTTZTableLookup(), EltsFromConsecutiveLoads(), emitSMEStateSaveRestore(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), expandMultipleResultFPLibCall(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), FoldConstantArithmetic(), FoldConstantBuildVector(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), getADAEntry(), getAddressForMemoryInput(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getAVX2GatherNode(), getConstant(), getConstantPool(), getConstantPool(), getCopyFromParts(), getCopyToParts(), getEVTAlign(), getGatherNode(), getGlobalAddress(), getIntPtrConstant(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getJumpTableDebugInfo(), getLifetimeNode(), getLoadStackGuard(), getMemcmp(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetStringVal(), getNode(), getNode(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getPPCf128HiElementSelector(), getPrefetchNode(), getPrefTypeAlign(), getPrefTypeAlign(), getReducedAlign(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getScatterNode(), getShiftAmountConstant(), getShiftAmountOperand(), llvm::PPC::getSplatIdxForPPCMnemonics(), llvm::TargetLowering::getSqrtInputTest(), getStrlen(), getSymbolFunctionGlobalAddress(), getTagSymNode(), getUniformBase(), getVectorIdxConstant(), getzOSCalleeAndADA(), getZT0FrameIndex(), InferPtrAlign(), isBLACompatibleAddress(), isExtendedBUILD_VECTOR(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), IsPredicateKnownToFail(), llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), LowerADDSAT_SUBSAT(), llvm::HexagonTargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::LoongArchTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::TargetLowering::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), LowerCTPOP(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerF64Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFMINIMUM_FMAXIMUM(), LowerFNEGorFABS(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), LowerRETURNADDR(), llvm::NVPTXTargetLowering::LowerSTACKRESTORE(), llvm::NVPTXTargetLowering::LowerSTACKSAVE(), LowerSTORE(), lowerSTOREVector(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), LowerVASTART(), LowerVASTART(), LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::SparcTargetLowering::makeAddress(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), makeStateFunctionCall(), matchPERM(), narrowExtractedVectorLoad(), PerformBITCASTCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUzpCombine(), PerformVMOVRRDCombine(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), replaceLoadVector(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), transformCallee(), unpackFromMemLoc(), unpackFromMemLoc(), unpackFromMemLoc(), UnrollVectorOverflowOp(), and llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().

◆ getDbgLabel()

SDDbgLabel * SelectionDAG::getDbgLabel ( DILabel * Label,
const DebugLoc & DL,
unsigned O )

Creates a SDDbgLabel node.

Definition at line 12152 of file SelectionDAG.cpp.

References assert(), llvm::cast(), and DL.

◆ getDbgValue()

SDDbgValue * SelectionDAG::getDbgValue ( DIVariable * Var,
DIExpression * Expr,
SDNode * N,
unsigned R,
bool IsIndirect,
const DebugLoc & DL,
unsigned O )

Creates a SDDbgValue node.

getDbgValue - Creates a SDDbgValue node.

SDNode

Definition at line 11862 of file SelectionDAG.cpp.

References assert(), llvm::cast(), DL, llvm::SDDbgOperand::fromNode(), and N.

◆ getDbgValueList()

SDDbgValue * SelectionDAG::getDbgValueList ( DIVariable * Var,
DIExpression * Expr,
ArrayRef< SDDbgOperand > Locs,
ArrayRef< SDNode * > Dependencies,
bool IsIndirect,
const DebugLoc & DL,
unsigned O,
bool IsVariadic )

Creates a SDDbgValue node from a list of locations.

Definition at line 11924 of file SelectionDAG.cpp.

References assert(), llvm::cast(), and DL.

Referenced by handleDanglingVariadicDebugInfo(), salvageDebugInfo(), and transferDbgValues().

◆ GetDbgValues()

ArrayRef< SDDbgValue * > llvm::SelectionDAG::GetDbgValues ( const SDNode * SD) const
inline

Get the debug values which reference the given SDNode.

Definition at line 1982 of file SelectionDAG.h.

Referenced by ProcessSDDbgValues(), salvageDebugInfo(), and transferDbgValues().

◆ getDenormalMode()

DenormalMode llvm::SelectionDAG::getDenormalMode ( EVT VT) const
inline

Return the current function's default denormal handling kind for the given floating point type.

Definition at line 2565 of file SelectionDAG.h.

References llvm::EVT::getFltSemantics().

◆ GetDependentSplitDestVTs()

std::pair< EVT, EVT > SelectionDAG::GetDependentSplitDestVTs ( const EVT & VT,
const EVT & EnvVT,
bool * HiIsEmpty ) const

Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.

GetDependentSplitDestVTs - Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.

Sets the HisIsEmpty flag when hi type has zero storage size.

Sets the HiIsEmpty flag when hi type has zero storage size.

Definition at line 13519 of file SelectionDAG.cpp.

References assert(), getContext(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().

◆ getEHLabel()

SDValue SelectionDAG::getEHLabel ( const SDLoc & dl,
SDValue Root,
MCSymbol * Label )

Definition at line 2353 of file SelectionDAG.cpp.

References getLabelNode().

◆ getElementCount()

◆ getEntryNode()

SDValue llvm::SelectionDAG::getEntryNode ( ) const
inline

Return the token chain corresponding to the entry of the function.

Definition at line 581 of file SelectionDAG.h.

References SDValue().

Referenced by llvm::AMDGPUTargetLowering::addTokenForArgument(), clear(), combineConcatVectorOps(), combineTargetShuffle(), copyExtraInfo(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(), llvm::TargetLowering::CTTZTableLookup(), expandMultipleResultFPLibCall(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), getADAEntry(), llvm::MipsTargetLowering::getAddrLocal(), getFLUSHW(), getFRAMEADDR(), getLargeExternalSymbol(), getLargeGlobalAddress(), getStackArgumentTokenFactor(), GetTLSADDR(), getzOSCalleeAndADA(), HandleMergeInputChains(), llvm::AMDGPUTargetLowering::loadStackInputValue(), lowerBALLOTIntrinsic(), lowerBuildVectorAsBroadcast(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerFCanonicalize(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), performDivRemCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::SITargetLowering::PostISelFolding(), promoteXINT_TO_FP(), llvm::SITargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), SelectionDAG(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle().

◆ getEVTAlign()

Align SelectionDAG::getEVTAlign ( EVT MemoryVT) const

◆ getExternalSymbol()

◆ getExtLoad() [1/2]

SDValue SelectionDAG::getExtLoad ( ISD::LoadExtType ExtType,
const SDLoc & dl,
EVT VT,
SDValue Chain,
SDValue Ptr,
EVT MemVT,
MachineMemOperand * MMO )

Definition at line 9852 of file SelectionDAG.cpp.

References getLoad(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getExtLoad() [2/2]

◆ getExtLoadVP() [1/2]

SDValue SelectionDAG::getExtLoadVP ( ISD::LoadExtType ExtType,
const SDLoc & dl,
EVT VT,
SDValue Chain,
SDValue Ptr,
SDValue Mask,
SDValue EVL,
EVT MemVT,
MachineMemOperand * MMO,
bool IsExpanding = false )

Definition at line 10080 of file SelectionDAG.cpp.

References getLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getExtLoadVP() [2/2]

SDValue SelectionDAG::getExtLoadVP ( ISD::LoadExtType ExtType,
const SDLoc & dl,
EVT VT,
SDValue Chain,
SDValue Ptr,
SDValue Mask,
SDValue EVL,
MachinePointerInfo PtrInfo,
EVT MemVT,
MaybeAlign Alignment,
MachineMemOperand::Flags MMOFlags,
const AAMDNodes & AAInfo,
bool IsExpanding = false )

Definition at line 10067 of file SelectionDAG.cpp.

References getLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getExtOrTrunc() [1/2]

SDValue llvm::SelectionDAG::getExtOrTrunc ( bool IsSigned,
SDValue Op,
const SDLoc & DL,
EVT VT )
inline

Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it.

Definition at line 1041 of file SelectionDAG.h.

References DL, getSExtOrTrunc(), and getZExtOrTrunc().

◆ getExtOrTrunc() [2/2]

SDValue llvm::SelectionDAG::getExtOrTrunc ( SDValue Op,
const SDLoc & DL,
EVT VT,
unsigned Opcode )
inline

Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it.

Definition at line 1025 of file SelectionDAG.h.

References llvm::ISD::ANY_EXTEND, DL, getAnyExtOrTrunc(), getSExtOrTrunc(), getZExtOrTrunc(), llvm_unreachable, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineShiftToAVG(), combineShiftToMULH(), earlyExpandDIVFIX(), expandDivFix(), LowerShift(), and PerformMinMaxFpToSatCombine().

◆ getExtractSubvector()

◆ getExtractVectorElt()

◆ getExtStridedLoadVP()

SDValue SelectionDAG::getExtStridedLoadVP ( ISD::LoadExtType ExtType,
const SDLoc & DL,
EVT VT,
SDValue Chain,
SDValue Ptr,
SDValue Stride,
SDValue Mask,
SDValue EVL,
EVT MemVT,
MachineMemOperand * MMO,
bool IsExpanding = false )

Definition at line 10284 of file SelectionDAG.cpp.

References DL, getStridedLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getFlagInserter()

FlagInserter * llvm::SelectionDAG::getFlagInserter ( )
inline

Definition at line 517 of file SelectionDAG.h.

Referenced by llvm::SelectionDAG::FlagInserter::FlagInserter().

◆ getFPExtendOrRound()

◆ getFrameIndex()

SDValue SelectionDAG::getFrameIndex ( int FI,
EVT VT,
bool isTarget = false )

Definition at line 1920 of file SelectionDAG.cpp.

References AddNodeIDNode(), llvm::ISD::FrameIndex, getVTList(), N, Opc, SDValue(), and llvm::ISD::TargetFrameIndex.

Referenced by llvm::X86TargetLowering::BuildFILD(), CalculateTailCallArgDest(), CreateStackTemporary(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), getAddressForMemoryInput(), getLifetimeNode(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getTargetFrameIndex(), getZT0FrameIndex(), llvm::AMDGPUTargetLowering::loadStackInputValue(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::TargetLowering::LowerCallTo(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), LowerVASTART(), unpack64(), unpackF64OnLA32DSoftABI(), unpackF64OnRV32DSoftABI(), unpackFromMemLoc(), unpackFromMemLoc(), and unpackFromMemLoc().

◆ getFrameIndexDbgValue() [1/2]

SDDbgValue * SelectionDAG::getFrameIndexDbgValue ( DIVariable * Var,
DIExpression * Expr,
unsigned FI,
ArrayRef< SDNode * > Dependencies,
bool IsIndirect,
const DebugLoc & DL,
unsigned O )

Creates a FrameIndex SDDbgValue node.

FrameIndex with dependencies.

Definition at line 11898 of file SelectionDAG.cpp.

References assert(), llvm::cast(), DL, and llvm::SDDbgOperand::fromFrameIdx().

◆ getFrameIndexDbgValue() [2/2]

SDDbgValue * SelectionDAG::getFrameIndexDbgValue ( DIVariable * Var,
DIExpression * Expr,
unsigned FI,
bool IsIndirect,
const DebugLoc & DL,
unsigned O )

Creates a FrameIndex SDDbgValue node.

FrameIndex.

Definition at line 11887 of file SelectionDAG.cpp.

References assert(), llvm::cast(), DL, and getFrameIndexDbgValue().

Referenced by getFrameIndexDbgValue().

◆ getFreeze()

◆ getFunctionVarLocs()

const FunctionVarLocs * llvm::SelectionDAG::getFunctionVarLocs ( ) const
inline

Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr.

Definition at line 510 of file SelectionDAG.h.

◆ getGatherVP()

◆ getGetFPEnv()

◆ getGLOBAL_OFFSET_TABLE()

SDValue llvm::SelectionDAG::getGLOBAL_OFFSET_TABLE ( EVT VT)
inline

Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.

Definition at line 1190 of file SelectionDAG.h.

References getNode(), and llvm::ISD::GLOBAL_OFFSET_TABLE.

Referenced by llvm::HexagonTargetLowering::LowerGLOBALADDRESS().

◆ getGlobalAddress()

◆ getGraphAttrs()

std::string SelectionDAG::getGraphAttrs ( const SDNode * N) const

Get graph attributes for a node.

getGraphAttrs - Get graph attributes for a node.

(eg. "color=red".) Used from getNodeAttributes.

Definition at line 203 of file SelectionDAGPrinter.cpp.

References llvm::errs(), I, and N.

Referenced by llvm::DOTGraphTraits< SelectionDAG * >::getNodeAttributes().

◆ getHasPredecessorMaxSteps()

unsigned SelectionDAG::getHasPredecessorMaxSteps ( )
static

◆ getHeapAllocSite()

MDNode * llvm::SelectionDAG::getHeapAllocSite ( const SDNode * Node) const
inline

Return HeapAllocSite associated with Node, or nullptr if none exists.

Definition at line 2514 of file SelectionDAG.h.

References I.

◆ getIndexedLoad()

◆ getIndexedLoadVP()

◆ getIndexedMaskedLoad()

SDValue SelectionDAG::getIndexedMaskedLoad ( SDValue OrigLoad,
const SDLoc & dl,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM )

◆ getIndexedMaskedStore()

SDValue SelectionDAG::getIndexedMaskedStore ( SDValue OrigStore,
const SDLoc & dl,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM )

◆ getIndexedStore()

SDValue SelectionDAG::getIndexedStore ( SDValue OrigStore,
const SDLoc & dl,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM )

◆ getIndexedStoreVP()

◆ getInsertSubvector()

◆ getInsertVectorElt()

SDValue llvm::SelectionDAG::getInsertVectorElt ( const SDLoc & DL,
SDValue Vec,
SDValue Elt,
unsigned Idx )
inline

◆ getIntPtrConstant()

SDValue SelectionDAG::getIntPtrConstant ( uint64_t Val,
const SDLoc & DL,
bool isTarget = false )

Definition at line 1801 of file SelectionDAG.cpp.

References DL, getConstant(), and getDataLayout().

Referenced by buildCallOperands(), combineBVZEXTLOAD(), CompactSwizzlableVector(), CreateCopyOfByValArgument(), emitConstantSizeRepmov(), emitConstantSizeRepstos(), emitRepmovsB(), emitRepstosB(), extractSubVector(), getCALLSEQ_END(), getCALLSEQ_START(), getCopyToParts(), getFPExtendOrRound(), getFRAMEADDR(), getParamsForOneTrueMaskedElt(), getStrictFPExtendOrRound(), GetTLSADDR(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerClusterLaunchControlQueryCancel(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerEXTRACT_SUBVECTOR(), LowerFCOPYSIGN(), LowerFLDEXP(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), lowerINT_TO_FP(), lowerMasksToReg(), llvm::RISCVTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), lowerSTOREVector(), LowerTcgen05St(), LowerToTLSExecModel(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), llvm::HexagonTargetLowering::LowerVACOPY(), LowerVACOPY(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::PPCTargetLowering::PerformDAGCombine(), performFPExtendCombine(), PerformTruncatingStoreCombine(), prepareDescriptorIndirectCall(), promoteXINT_TO_FP(), ReorganizeVector(), replaceAtomicSwap128(), replaceLoadVector(), and SplitScalar().

◆ getJumpTable()

SDValue SelectionDAG::getJumpTable ( int JTI,
EVT VT,
bool isTarget = false,
unsigned TargetFlags = 0 )

◆ getJumpTableDebugInfo()

◆ getLabelNode()

SDValue SelectionDAG::getLabelNode ( unsigned Opcode,
const SDLoc & dl,
SDValue Root,
MCSymbol * Label )

◆ getLibInfo()

const TargetLibraryInfo & llvm::SelectionDAG::getLibInfo ( ) const
inline

Definition at line 505 of file SelectionDAG.h.

Referenced by expandMultipleResultFPLibCall().

◆ getLifetimeNode()

SDValue SelectionDAG::getLifetimeNode ( bool IsStart,
const SDLoc & dl,
SDValue Chain,
int FrameIndex )

Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the FrameIndex.

Definition at line 9653 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddNodeIDNode(), getDataLayout(), llvm::SDLoc::getDebugLoc(), getFrameIndex(), llvm::SDLoc::getIROrder(), getTargetLoweringInfo(), getVTList(), N, NewSDValueDbgMsg(), and SDValue().

◆ getLoad() [1/5]

SDValue SelectionDAG::getLoad ( EVT VT,
const SDLoc & dl,
SDValue Chain,
SDValue Ptr,
MachineMemOperand * MMO )

Definition at line 9834 of file SelectionDAG.cpp.

References getLoad(), getUNDEF(), llvm::ISD::NON_EXTLOAD, Ptr, and llvm::ISD::UNINDEXED.

◆ getLoad() [2/5]

SDValue SelectionDAG::getLoad ( EVT VT,
const SDLoc & dl,
SDValue Chain,
SDValue Ptr,
MachinePointerInfo PtrInfo,
MaybeAlign Alignment = MaybeAlign(),
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
const AAMDNodes & AAInfo = AAMDNodes(),
const MDNode * Ranges = nullptr )

Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.

This function will set the MOLoad flag on MMOFlags, but you can set it if you want. The MOStore flag must not be set.

Definition at line 9824 of file SelectionDAG.cpp.

References getLoad(), getUNDEF(), llvm::ISD::NON_EXTLOAD, Ptr, and llvm::ISD::UNINDEXED.

Referenced by bitcastf32Toi32(), llvm::X86TargetLowering::BuildFILD(), combineBVOfConsecutiveLoads(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineExtractWithShuffle(), combineLoad(), combineMaskedLoadConstantMask(), combineMOVDQ2Q(), combineStore(), combineTargetShuffle(), EltsFromConsecutiveLoads(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), expandf64Toi32(), expandMultipleResultFPLibCall(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), getADAEntry(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrLocal(), llvm::MipsTargetLowering::getDllimportVariable(), getExtLoad(), getExtLoad(), getFRAMEADDR(), getIndexedLoad(), getLargeExternalSymbol(), getLargeGlobalAddress(), getLoad(), getLoad(), getLoad(), getLoad(), getMemmoveLoadsAndStores(), GetTLSADDR(), getzOSCalleeAndADA(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerAsSplatVectorLoad(), llvm::NVPTXTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerF128Load(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerLoad(), LowerLoad(), lowerLoadF128(), lowerLoadI1(), lowerMSALoadIntr(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), lowerShuffleAsBroadcast(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerUINT_TO_FP_i64(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), lowerVECTOR_SHUFFLE(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), narrowExtractedVectorLoad(), performConcatVectorsCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), PerformVMOVhrCombine(), PerformVMOVRRDCombine(), prepareDescriptorIndirectCall(), reduceMaskedLoadToScalarLoad(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifySetCC(), SkipLoadExtensionForVMULL(), unpack64(), unpackF64OnLA32DSoftABI(), and unpackF64OnRV32DSoftABI().

◆ getLoad() [3/5]

◆ getLoad() [4/5]

◆ getLoad() [5/5]

SDValue llvm::SelectionDAG::getLoad ( ISD::MemIndexedMode AM,
ISD::LoadExtType ExtType,
EVT VT,
const SDLoc & dl,
SDValue Chain,
SDValue Ptr,
SDValue Offset,
MachinePointerInfo PtrInfo,
EVT MemVT,
MaybeAlign Alignment = MaybeAlign(),
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
const AAMDNodes & AAInfo = AAMDNodes(),
const MDNode * Ranges = nullptr )
inline

◆ getLoadFFVP()

◆ getLoadVP() [1/5]

SDValue SelectionDAG::getLoadVP ( EVT VT,
const SDLoc & dl,
SDValue Chain,
SDValue Ptr,
SDValue Mask,
SDValue EVL,
MachineMemOperand * MMO,
bool IsExpanding = false )

◆ getLoadVP() [2/5]

SDValue SelectionDAG::getLoadVP ( EVT VT,
const SDLoc & dl,
SDValue Chain,
SDValue Ptr,
SDValue Mask,
SDValue EVL,
MachinePointerInfo PtrInfo,
MaybeAlign Alignment,
MachineMemOperand::Flags MMOFlags,
const AAMDNodes & AAInfo,
const MDNode * Ranges = nullptr,
bool IsExpanding = false )

◆ getLoadVP() [3/5]

◆ getLoadVP() [4/5]

◆ getLoadVP() [5/5]

SDValue llvm::SelectionDAG::getLoadVP ( ISD::MemIndexedMode AM,
ISD::LoadExtType ExtType,
EVT VT,
const SDLoc & dl,
SDValue Chain,
SDValue Ptr,
SDValue Offset,
SDValue Mask,
SDValue EVL,
MachinePointerInfo PtrInfo,
EVT MemVT,
MaybeAlign Alignment = MaybeAlign(),
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
const AAMDNodes & AAInfo = AAMDNodes(),
const MDNode * Ranges = nullptr,
bool IsExpanding = false )
inline

◆ getLogicalNOT()

SDValue SelectionDAG::getLogicalNOT ( const SDLoc & DL,
SDValue Val,
EVT VT )

◆ getMachineFunction()

MachineFunction & llvm::SelectionDAG::getMachineFunction ( ) const
inline

Definition at line 493 of file SelectionDAG.h.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), buildCallOperands(), llvm::X86TargetLowering::BuildFILD(), llvm::TargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSREMPow2(), CalculateTailCallSPDiff(), llvm::AArch64TargetLowering::changeStreamingMode(), combineConcatVectorOps(), combineFMA(), combineFMADDSUB(), combineFMinNumFMaxNum(), combineFneg(), combineMul(), combineStore(), combineTargetShuffle(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), llvm::BaseIndexOffset::computeAliasing(), computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::SITargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::TargetLowering::CTTZTableLookup(), llvm::SITargetLowering::denormalsEnabledForType(), EmitCmp(), emitConstantSizeRepmov(), emitConstantSizeRepstos(), emitLockedStackOp(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), emitSMEStateSaveRestore(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemmove(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::RISCVSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), EmitUnrolledSetTag(), llvm::BaseIndexOffset::equalBaseIndex(), errorUnsupported(), llvm::X86TargetLowering::expandIndirectJTBranch(), llvm::TargetLowering::expandIS_FPCLASS(), expandMul(), expandMultipleResultFPLibCall(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVectorSplice(), fail(), fixupFuncForFI(), getADAEntry(), getAddressForMemoryInput(), llvm::MipsTargetLowering::getAddrLocal(), getBROADCAST_LOAD(), getCopyFromParts(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFRAMEADDR(), llvm::MipsTargetLowering::getGlobalReg(), getLargeExternalSymbol(), getLargeGlobalAddress(), getLoad(), getLoadStackGuard(), getLoadVP(), getMemcpyLoadsAndStores(), getMemIntrinsicNode(), getMemmoveLoadsAndStores(), getMemsetStores(), llvm::MipsTargetLowering::getOpndList(), llvm::VETargetLowering::getPICJumpTableRelocBase(), getReducedAlign(), getRegistersForValue(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStore(), getTagSymNode(), GetTLSADDR(), getTruncStore(), getTruncStoreVP(), getv64i1Argument(), getVCIXISDNodeWCHAIN(), getVScale(), getzOSCalleeAndADA(), hasReturnsTwiceAttr(), InferPointerInfo(), InferPtrAlign(), llvm::SITargetLowering::isCanonicalized(), isConsecutiveLSLoc(), llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isEligibleToFoldADDIForFasterLocalAccesses(), llvm::SITargetLowering::isFMADLegal(), llvm::SITargetLowering::isFPExtFoldable(), llvm::TargetLowering::isInTailCallPosition(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), isKnownNeverZero(), isThreadPointerAcquisitionNode(), IsWebAssemblyLocal(), legalizeScatterGatherIndexType(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerAsSplatVectorLoad(), LowerATOMIC_STORE(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFDIV(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(), llvm::R600TargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), lowerShuffleAsBroadcast(), llvm::NVPTXTargetLowering::LowerSTACKRESTORE(), llvm::NVPTXTargetLowering::LowerSTACKSAVE(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerToTLSLocalDynamicModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVACOPY(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), LowerVASTART(), LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), lowerVECTOR_SHUFFLE(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), MarkEHGuard(), MarkEHRegistrationNode(), narrowExtractedVectorLoad(), llvm::AMDGPUTargetLowering::needsDenormHandlingF32(), llvm::SITargetLowering::passSpecialInputs(), performBRCONDCombine(), performCONCAT_VECTORSCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformFADDCombineWithOperands(), performMemPairCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performVP_REVERSECombine(), performVP_STORECombine(), llvm::SITargetLowering::PostISelFolding(), llvm::AArch64TargetLowering::preferredShiftLegalizationStrategy(), llvm::RISCVTargetLowering::preferredShiftLegalizationStrategy(), llvm::X86TargetLowering::preferredShiftLegalizationStrategy(), processVCIXOperands(), promoteToConstantPool(), promoteVCIXScalar(), recoverFramePointer(), reduceVMULWidth(), replaceAtomicSwap128(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), selectI64Imm(), setAlignFlagsForFI(), setUsesTOCBasePtr(), shouldGenerateInlineTPLoop(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifySetCC(), splitStores(), llvm::AMDGPUTargetLowering::storeStackInputValue(), StoreTailCallArgumentsToStackSlot(), transformCallee(), tryMemPairCombine(), llvm::X86InstrInfo::unfoldMemoryOperand(), unpack64(), unpackF64OnLA32DSoftABI(), unpackF64OnRV32DSoftABI(), unpackFromMemLoc(), unpackFromMemLoc(), unpackFromMemLoc(), unpackFromRegLoc(), unpackFromRegLoc(), unpackFromRegLoc(), updateForAIXShLibTLSModelOpt(), and viewGraph().

◆ getMachineNode() [1/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
ArrayRef< EVT > ResultTys,
ArrayRef< SDValue > Ops )

◆ getMachineNode() [2/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT )

These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.

getMachineNode - These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.

Note that getMachineNode returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one.

Definition at line 11685 of file SelectionDAG.cpp.

References getMachineNode(), and getVTList().

Referenced by buildRegSequence16(), buildRegSequence32(), llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), llvm::VETargetLowering::combineTRUNCATE(), convertFromF16(), llvm::SITargetLowering::copyToM0(), createGPRPairNode(), createGPRPairNode2xi32(), emitLockedStackOp(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), expandBitCastI128ToF128(), expandIntrinsicWChainHelper(), getDataClassTest(), getLeftShift(), getLoadStackGuard(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getPrefetchNode(), getTargetExtractSubreg(), getTargetInsertSubreg(), InvertCarryFlag(), isWorthFoldingIntoOrrWithShift(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::VETargetLowering::lowerATOMIC_FENCE(), lowerBuildVectorViaPacking(), llvm::SITargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerF128Load(), LowerF128Store(), LowerF64Op(), LowerFNEGorFABS(), llvm::VETargetLowering::LowerFormalArguments(), lowerI128ToGR128(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINTRINSIC_W_CHAIN(), lowerLoadF128(), lowerLoadI1(), llvm::SystemZTargetLowering::LowerOperationWrapper(), LowerPtrAuthGlobalAddressStatically(), llvm::VETargetLowering::LowerReturn(), lowerStoreF128(), lowerStoreI1(), optimizeLogicalImm(), llvm::packConstantV2I16(), llvm::SITargetLowering::PostISelFolding(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), replaceCMP_XCHG_128Results(), llvm::PPCTargetLowering::SelectAddressRegImm(), selectConstantAddr(), selectI64Imm(), selectI64Imm(), selectI64ImmDirect(), selectI64ImmDirectPrefix(), selectImm(), selectImmSeq(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), SelectSAddrFI(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), Widen(), and llvm::SITargetLowering::wrapAddr64Rsrc().

◆ getMachineNode() [3/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT,
ArrayRef< SDValue > Ops )

◆ getMachineNode() [4/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT,
SDValue Op1 )

◆ getMachineNode() [5/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT,
SDValue Op1,
SDValue Op2 )

◆ getMachineNode() [6/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT,
SDValue Op1,
SDValue Op2,
SDValue Op3 )

◆ getMachineNode() [7/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT1,
EVT VT2,
ArrayRef< SDValue > Ops )

◆ getMachineNode() [8/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT1,
EVT VT2,
EVT VT3,
ArrayRef< SDValue > Ops )

◆ getMachineNode() [9/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT1,
EVT VT2,
EVT VT3,
SDValue Op1,
SDValue Op2 )

◆ getMachineNode() [10/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT1,
EVT VT2,
EVT VT3,
SDValue Op1,
SDValue Op2,
SDValue Op3 )

◆ getMachineNode() [11/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT1,
EVT VT2,
SDValue Op1,
SDValue Op2 )

◆ getMachineNode() [12/13]

MachineSDNode * SelectionDAG::getMachineNode ( unsigned Opcode,
const SDLoc & dl,
EVT VT1,
EVT VT2,
SDValue Op1,
SDValue Op2,
SDValue Op3 )

◆ getMachineNode() [13/13]

◆ getMaskedGather()

◆ getMaskedHistogram()

◆ getMaskedLoad()

◆ getMaskedScatter()

◆ getMaskedStore()

◆ getMCSymbol()

SDValue SelectionDAG::getMCSymbol ( MCSymbol * Sym,
EVT VT )

Definition at line 2055 of file SelectionDAG.cpp.

References getVTList(), N, and SDValue().

Referenced by recoverFramePointer(), and transformCallee().

◆ getMDNode()

SDValue SelectionDAG::getMDNode ( const MDNode * MD)

Return an MDNodeSDNode which holds an MDNode.

Definition at line 2413 of file SelectionDAG.cpp.

References AddNodeIDNode(), getVTList(), N, and SDValue().

Referenced by llvm::PPCTargetLowering::CollectTargetIntrinsicOperands().

◆ getMemBasePlusOffset() [1/2]

SDValue SelectionDAG::getMemBasePlusOffset ( SDValue Base,
SDValue Offset,
const SDLoc & DL,
const SDNodeFlags Flags = SDNodeFlags() )

Definition at line 8583 of file SelectionDAG.cpp.

References llvm::ISD::ADD, assert(), DL, getNode(), llvm::Offset, and Ptr.

◆ getMemBasePlusOffset() [2/2]

◆ getMemcmp()

◆ getMemcpy()

◆ getMemIntrinsicNode() [1/3]

◆ getMemIntrinsicNode() [2/3]

SDValue SelectionDAG::getMemIntrinsicNode ( unsigned Opcode,
const SDLoc & dl,
SDVTList VTList,
ArrayRef< SDValue > Ops,
EVT MemVT,
MachinePointerInfo PtrInfo,
Align Alignment,
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore,
LocationSize Size = LocationSize::precise(0),
const AAMDNodes & AAInfo = AAMDNodes() )

Creates a MemIntrinsicNode that may produce a result and takes a list of operands.

Opcode may be INTRINSIC_VOID, INTRINSIC_W_CHAIN, or a target-specific memory-referencing opcode

Definition at line 9595 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, getMachineFunction(), getMemIntrinsicNode(), llvm::EVT::getStoreSize(), llvm::LocationSize::precise(), and Size.

Referenced by llvm::X86TargetLowering::BuildFILD(), combineBitcast(), combineBVZEXTLOAD(), combinePackingMovIntoStore(), combineStore(), combineTargetShuffle(), CombineVLDDUP(), combineX86CloadCstore(), createLoadLR(), createSetFPEnvNodes(), createStoreLR(), EltsFromConsecutiveLoads(), EmitMaskedTruncSStore(), llvm::RISCVSelectionDAGInfo::EmitTargetCodeForMemset(), EmitTruncSStore(), EmitUnrolledSetTag(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), getAVX2GatherNode(), getBROADCAST_LOAD(), getGatherNode(), getMemIntrinsicNode(), getMemIntrinsicNode(), getScatterNode(), LowerATOMIC_STORE(), lowerAtomicArithWithLOCK(), lowerBuildVectorAsBroadcast(), LowerCMP_SWAP(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMSCATTER(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), lowerShuffleAsBroadcast(), LowerSTORE(), LowerStore(), lowerSTOREVector(), LowerTcgen05St(), lowerUINT_TO_FP_vXi32(), lowerVECTOR_SHUFFLE(), narrowLoadToVZLoad(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformVDUPCombine(), replaceAtomicSwap128(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceTcgen05Ld(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), TryCombineBaseUpdate(), tryMemPairCombine(), llvm::X86TargetLowering::visitMaskedLoad(), and llvm::X86TargetLowering::visitMaskedStore().

◆ getMemIntrinsicNode() [3/3]

◆ getMemmove()

◆ getMemset()

◆ getMergeValues()

SDValue SelectionDAG::getMergeValues ( ArrayRef< SDValue > Ops,
const SDLoc & dl )

Create a MERGE_VALUES node from the given operands.

getMergeValues - Create a MERGE_VALUES node from the given operands.

Definition at line 9584 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, getNode(), getVTList(), llvm::ISD::MERGE_VALUES, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorImpl< T >::reserve().

Referenced by combineFP_EXTEND(), combineFP_ROUND(), combineVectorCompareAndMaskUnaryOp(), combineX86AddSub(), combineX86SubCmpForFlags(), constructRetValue(), emitIntrinsicWithChainErrorMessage(), FixupMMXIntrinsicTypes(), getAVX2GatherNode(), getGatherNode(), getVCIXISDNodeWCHAIN(), lowerADDSUBO_CARRY(), llvm::VETargetLowering::lowerATOMIC_SWAP(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), LowerF128Load(), lowerFixedVectorSegLoadIntrinsics(), llvm::SITargetLowering::LowerFormalArguments(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP_vXi64(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerLoad(), LowerLoad(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), lowerLOADi1(), lowerLoadI1(), lowerLoadVector(), LowerMGATHER(), LowerMLOAD(), LowerMLOAD(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerREADCYCLECOUNTER(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::NVPTXTargetLowering::LowerSTACKSAVE(), llvm::SITargetLowering::LowerSTACKSAVE(), llvm::HexagonTargetLowering::LowerUAddSubO(), llvm::HexagonTargetLowering::LowerUAddSubOCarry(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVSETCC(), LowerXALUO(), llvm::RISCVTargetLowering::PerformDAGCombine(), performGatherLoadCombine(), performLD1Combine(), performLD1ReplicateCombine(), performLDNT1Combine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLongShiftCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), performRNDRCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformVMOVRRDCombine(), SplitStrictFPVectorOp(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryMemPairCombine(), UnrollVectorOp(), llvm::SystemZTargetLowering::useLibCall(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), and widenVectorOpsToi8().

◆ getMFAM()

MachineFunctionAnalysisManager * llvm::SelectionDAG::getMFAM ( )
inline

Definition at line 495 of file SelectionDAG.h.

◆ getMMI()

MachineModuleInfo * llvm::SelectionDAG::getMMI ( ) const
inline

Definition at line 515 of file SelectionDAG.h.

◆ getMMRAMetadata()

MDNode * llvm::SelectionDAG::getMMRAMetadata ( const SDNode * Node) const
inline

Return the MMRA MDNode associated with Node, or nullptr if none exists.

Definition at line 2533 of file SelectionDAG.h.

◆ getNegative()

◆ getNeutralElement()

◆ getNode() [1/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
ArrayRef< EVT > ResultTys,
ArrayRef< SDValue > Ops )

◆ getNode() [2/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
ArrayRef< EVT > ResultTys,
ArrayRef< SDValue > Ops,
const SDNodeFlags Flags )

◆ getNode() [3/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT )

Gets or creates the specified node.

Definition at line 6418 of file SelectionDAG.cpp.

References AddNodeIDNode(), DL, getVTList(), N, NewSDValueDbgMsg(), and SDValue().

◆ getNode() [4/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
ArrayRef< SDUse > Ops )

Gets or creates the specified node.

Definition at line 10875 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::get(), and getNode().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), AddRequiredExtensionForVMULL(), addShuffleForVecExtend(), llvm::AMDGPUTargetLowering::addTokenForArgument(), adjustBitcastSrcVectorSSE1(), adjustForTestUnderMask(), adjustICmp128(), adjustLoadValueTypeImpl(), buildCallOperands(), BuildExactSDIV(), BuildExactUDIV(), buildFromShuffleMostly(), BuildIntrinsicOp(), BuildIntrinsicOp(), BuildIntrinsicOp(), buildMergeScalars(), buildPCRelGlobalAddress(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::buildSDIVPow2WithCMov(), buildTreeReduction(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), BuildVSLDOI(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleVectorByLane(), canonicalizeShuffleWithOp(), carryFlagToValue(), chainLoadsAndStoresForMemcpy(), llvm::AArch64TargetLowering::changeStreamingMode(), checkIntrinsicImmArg(), checkSignTestSetCCCombine(), clampDynamicVectorIndex(), CollectOpsToWiden(), combine_CC(), combine_CC(), combineAcrossLanesIntrinsic(), combineADC(), combineAdd(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineADDToMAT_PCREL_ADDR(), combineADDX(), combineAnd(), combineAndLoadToBZHI(), combineAndMaskToShift(), combineAndNotIntoANDNP(), combineAndNotOrIntoAndNotAnd(), combineAndnp(), combineAndOrForCcmpCtest(), CombineANDShift(), combineAndShuffleNot(), combineAndXorSubWithBMI(), combineArithReduction(), combineAVG(), combineAVX512SetCCToKMOV(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBrCond(), combineCarryDiamond(), combineCarryThroughADD(), combineCastedMaskArithmetic(), combineCMov(), combineCMP(), combineCommutableSHUFP(), combineCompareEqual(), combineConcatVectorOfCasts(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfScalars(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOfSplats(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineDeMorganOfBoolean(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFMA(), combineFMADDSUB(), combineFMinFMax(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacyImpl(), combineFMinNumFMaxNum(), combineFMulcFCMulc(), combineFneg(), combineFP16_TO_FP(), combineFP_EXTEND(), combineFP_ROUND(), combineFP_TO_xINT_SAT(), combineFPToSInt(), combineGatherScatter(), combineHorizOpWithShuffle(), combinei64TruncSrlConstant(), combineINSERT_SUBVECTOR(), combineKSHIFT(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLRINT_LLRINT(), combineM68kBrCond(), combineMADConstOne(), combineMinMaxReduction(), combineMinNumMaxNumImpl(), combineMOVMSK(), combineMul(), combineMulSelectConstOne(), combineMulSpecial(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineMulWide(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineOrOfCZERO(), combineOrXorWithSETCC(), combinePMULDQ(), combinePMULH(), combinePredicateReduction(), combinePTESTCC(), combineRedundantDWordShuffle(), combineSBB(), combineSCALAR_TO_VECTOR(), combineScalarAndWithMaskSetcc(), combineSelect(), llvm::VETargetLowering::combineSelect(), combineSelectAndUse(), combineSelectAndUse(), combineSelectAndUse(), combineSelectAsExtAnd(), llvm::VETargetLowering::combineSelectCC(), combineSelectOfTwoConstants(), combineSelectToBinOp(), combineSetCC(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShlAddIAddImpl(), combineShuffleToAddSubOrFMAddSub(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToFMAddSub(), combineShuffleToZeroExtendVectorInReg(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineSubShiftToOrcB(), combineSUBX(), combineSVEBitSel(), combineSVEPrefetchVecBaseImmOff(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineToHorizontalAddSub(), combineToVCPOP(), combineToVWMACC(), combineTruncate(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineTruncToVnclip(), combineUADDO_CARRYDiamond(), combineUIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorHADDSUB(), combineVectorInsert(), combineVectorMulToSraBitcast(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVFMADD_VLWithVFNEG_VL(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVPMADD52LH(), combineVqdotAccum(), combineVSelectToBLENDV(), combineVSelectWithAllOnesOrZeros(), combineVTRUNC(), combineVWADDSUBWSelect(), combineX86AddSub(), combineX86CloadCstore(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86SubCmpForFlags(), combineXor(), combineXorSubCTLZ(), combineXorToBitfieldInsert(), combineZext(), CompactSwizzlableVector(), ConstantBuildVector(), constructDup(), constructRetValue(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), ConvertCarryFlagToCarryValue(), ConvertCarryValueToCarryFlag(), convertFixedMaskToScalableVector(), convertFPToInt(), convertFromF16(), convertFromScalableVector(), convertIntLogicToFPLogic(), convertIntToFP(), convertLocVTToValVT(), convertLocVTToValVT(), convertLocVTToValVT(), convertLocVTToValVT(), convertMergedOpToPredOp(), ConvertSelectToConcatVector(), convertShiftLeftToScale(), convertToF16(), convertToScalableVector(), convertValVTToLocVT(), convertValVTToLocVT(), convertValVTToLocVT(), convertValVTToLocVT(), correctParamType(), createCMovFP(), createFPCmp(), createLoadLR(), createMemMemNode(), createMMXBuildVector(), createPSADBW(), createSetFPEnvNodes(), createStoreLR(), createVariablePermute(), createVPDPBUSD(), llvm::TargetLowering::CTTZTableLookup(), customLegalizeToWOp(), customLegalizeToWOp(), customLegalizeToWOpWithSExt(), customLegalizeToWOpWithSExt(), CustomNonLegalBITCASTResults(), detectPMADDUBSW(), detectUSatPattern(), distributeOpThroughSelect(), dump(), EltsFromConsecutiveLoads(), EmitAVX512Test(), EmitCMP(), EmitCmp(), emitCmp(), emitComparison(), emitConditionalComparison(), emitConstantSizeRepmov(), emitConstantSizeRepstos(), emitFloatCompareMask(), emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), emitMemMemReg(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), emitOrXorXorTree(), emitRepmovs(), emitRepstos(), emitSETCC(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), emitStrictFPComparison(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::RISCVSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), EmitTest(), EmitUnrolledSetTag(), emitVectorComparison(), Expand64BitShift(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), expandBitCastF128ToI128(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), ExpandBVWithShuffles(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), expandExp(), expandExp2(), expandf64Toi32(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), expandFP_TO_UINT_SSE(), expandFSH64(), llvm::TargetLowering::expandFunnelShift(), ExpandHorizontalBinOp(), llvm::RISCVTargetLowering::expandIndirectJTBranch(), llvm::TargetLowering::expandIndirectJTBranch(), llvm::X86TargetLowering::expandIndirectJTBranch(), llvm::TargetLowering::expandIntMINMAX(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandIS_FPCLASS(), expandLog(), expandLog10(), expandLog2(), expandMul(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), expandMulToAddOrSubOfShl(), expandMulToNAFSequence(), llvm::TargetLowering::expandPartialReduceMLA(), expandPow(), ExpandPowI(), ExpandREAD_REGISTER(), llvm::TargetLowering::expandREM(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandV4F32ToV2F64(), expandVAArg(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVectorNaryOpBySplitting(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZ(), llvm::TargetLowering::expandVPCTTZElements(), expandVPFunnelShift(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtractBitFromMaskVector(), extractF64Exponent(), extractLOHI(), extractShiftForRotate(), extractSubVector(), finalizeTS1AM(), findMoreOptimalIndexType(), FixupMMXIntrinsicTypes(), foldADCToCINC(), foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndOrOfSETCC(), foldAndToUsubsat(), foldBinOpIntoSelectIfProfitable(), foldBinOpIntoSelectIfProfitable(), foldBitOrderCrossLogicOp(), FoldConstantArithmetic(), FoldConstantBuildVector(), foldCSELOfCSEL(), foldCSELofCTTZ(), foldCSELofLASTB(), foldExtendedSignBitTest(), foldExtendVectorInregToExtendOfSubvector(), foldExtractSubvectorFromShuffleVector(), foldFPToIntToFP(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), foldIndexIntoBase(), FoldIntToFPToInt(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedMerge(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldOverflowCheck(), foldReduceOperandViaVQDOT(), foldSelectOfConstantsUsingSra(), foldSelectOfCTTZOrCTLZ(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldSubCtlzNot(), foldToSaturated(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandMultiply(), llvm::TargetLowering::forceExpandWideMUL(), fpExtendHelper(), genConstMult(), generateComparison(), generateEquivalentSub(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), GeneratePerfectShuffle(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), getADAEntry(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrGPRel(), llvm::MipsTargetLowering::getAddrLocal(), llvm::MipsTargetLowering::getAddrNonPIC(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAllOnesMask(), getAnyExtOrTrunc(), getAVX512Node(), getAVX512TruncNode(), getBitcast(), getBitSelect(), getBitTestCondition(), getBMIMatchingOp(), getBoolExtOrTrunc(), getBoundedStrlen(), getBT(), getBuildVector(), getBuildVector(), getBuildVectorSplat(), getCALLSEQ_END(), getCALLSEQ_START(), getCCResult(), getConstant(), getCopyFromParts(), getCopyFromPartsVector(), getCopyFromReg(), getCopyFromReg(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), getCopyToReg(), getCopyToReg(), getCopyToReg(), llvm::RegsForValue::getCopyToRegs(), getCSAddressAndShifts(), getDataClassTest(), getDeinterleaveShiftAndTrunc(), llvm::MipsTargetLowering::getDllimportSymbol(), getDWordFromOffset(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getEstimate(), GetExponent(), getEXTEND_VECTOR_INREG(), GetExtendHigh(), getExtractSubvector(), getExtractVectorElt(), getExtractVectorizedValue(), getFlagsOfCmpZeroFori1(), getFLUSHW(), getFPBinOp(), getFPExtendOrRound(), getFPTernOp(), getFRAMEADDR(), getFreeze(), getGeneralPermuteNode(), getGLOBAL_OFFSET_TABLE(), llvm::AMDGPUTargetLowering::getHiHalf64(), getHopForBuildVector(), getI128Select(), getInsertSubvector(), getInsertVectorElt(), llvm::AMDGPUTargetLowering::getIsFinite(), getJumpTableDebugInfo(), getKnownUndefForVectorBinop(), getLargeExternalSymbol(), getLargeGlobalAddress(), getLimitedPrecisionExp2(), getLoadExtOrTrunc(), getLogicalNOT(), llvm::AMDGPUTargetLowering::getLoHalf64(), getMad(), getMad64_32(), getMaskNode(), getMemBasePlusOffset(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), getMergeValues(), getMul24(), llvm::AMDGPUTargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::X86TargetLowering::getNegatedExpression(), getNegative(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNOT(), getPack(), getPermuteNode(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getPMOVMSKB(), getPOISON(), getPopFromX87Reg(), getPRMT(), getPTest(), getPTrue(), llvm::AMDGPUTargetLowering::getRecipEstimate(), llvm::LoongArchTargetLowering::getRecipEstimate(), getReductionSDNode(), getRegistersForValue(), getScalarMaskingNode(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getScaledOffsetForBitWidth(), getSelect(), getSelectCC(), getSETCC(), getSETCC(), getSETCC(), getSetCC(), getSetCCVP(), getSExtOrTrunc(), getShuffleHalfVectors(), GetSignificand(), getSplatBuildVector(), getSplatVector(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::LoongArchTargetLowering::getSqrtEstimate(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::TargetLowering::getSqrtInputTest(), getStackArgumentTokenFactor(), getStepVector(), getSToVPermuted(), getStrictFPExtendOrRound(), getSVEPredicateBitCast(), getTargetVShiftByConstNode(), getTargetVShiftNode(), GetTLSADDR(), getTokenFactor(), getTruncatedUSUBSAT(), getUNDEF(), getv64i1Argument(), getVAArg(), getVCIXISDNodeVOID(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), getVectorMaskingNode(), getVectorShuffle(), llvm::TargetLowering::getVectorSubVecPointer(), getVPLogicalNOT(), getVPZeroExtendInReg(), getVPZExtOrTrunc(), getVScale(), getVShift(), getVSlidedown(), getVSlideup(), getWideningInterleave(), getWideningSpread(), getX86XALUOOp(), getZeroExtendInReg(), getZeroPaddedAdd(), getZeroVector(), getZExtOrTrunc(), getzOSCalleeAndADA(), handleCMSEValue(), HandleMergeInputChains(), llvm::TargetLowering::IncrementMemoryAddress(), initAccumulator(), insert1BitVector(), InsertBitToMaskVector(), isFNEG(), isFusableLoadOpStorePattern(), isFusableLoadOpStorePattern(), IsNOT(), isUpperSubvectorUndef(), joinDwords(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), legalizeIntrinsicImmArg(), legalizeScatterGatherIndexType(), llvm::TargetLowering::LegalizeSetCCCondCode(), legalizeSVEGatherPrefetchOffsVec(), llvm::AMDGPUTargetLowering::loadInputValue(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), LowerABD(), LowerABS(), LowerADDRSPACECAST(), LowerADDRSPACECAST(), lowerAddrSpaceCast(), LowerADDSAT_SUBSAT(), LowerADDSUBO_CARRY(), lowerADDSUBO_CARRY(), LowerADDSUBSAT(), lowerAddSubToHorizontalOp(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), llvm::VETargetLowering::lowerATOMIC_FENCE(), LowerATOMIC_STORE(), llvm::VETargetLowering::lowerATOMIC_SWAP(), lowerAtomicArith(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), lowerBALLOTIntrinsic(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::HexagonTargetLowering::LowerBlockAddress(), llvm::LanaiTargetLowering::LowerBlockAddress(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBRCOND(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), lowerBUILD_VECTORAsBroadCastLoad(), LowerBUILD_VECTORToVIDUP(), LowerBUILD_VECTORvXbf16(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), lowerBuildVectorViaVID(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), lowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerClusterLaunchControlQueryCancel(), LowerCMP_SWAP(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerConstantPool(), llvm::LanaiTargetLowering::LowerConstantPool(), LowerConvertLow(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), lowerCTLZCTPOP(), llvm::AMDGPUTargetLowering::lowerCTLZResults(), LowerCTPOP(), LowerCTPOP(), LowerCTTZ(), LowerCTTZ(), lowerCttzElts(), LowerCVTPS2PH(), lowerDisjointIndicesShuffle(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP(), llvm::VETargetLowering::lowerEH_SJLJ_SETJMP(), llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH(), LowerEXTEND_VECTOR_INREG(), llvm::MSP430TargetLowering::LowerExternalSymbol(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), LowerF64Op(), llvm::AMDGPUTargetLowering::LowerF64ToF16Safe(), LowerFABSorFNEG(), lowerFABSorFNEG(), LowerFCanonicalize(), llvm::AMDGPUTargetLowering::LowerFCEIL(), lowerFCMPIntrinsic(), LowerFCOPYSIGN(), lowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFGETSIGN(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), LowerFLDEXP(), llvm::AMDGPUTargetLowering::LowerFLOG2(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), llvm::AMDGPUTargetLowering::LowerFLOGUnsafe(), lowerFMAXIMUM_FMINIMUM(), LowerFMINIMUM_FMAXIMUM(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP16_TO_FP(), llvm::SITargetLowering::lowerFP_EXTEND(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT(), lowerFP_TO_INT(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), LowerFP_TO_INT_SAT(), lowerFP_TO_INT_SAT(), LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), lowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), LowerFunnelShift(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), lowerGetVectorLength(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerGR128Binary(), lowerGR128ToI128(), LowerHorizontalByteSum(), lowerI128ToGR128(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerICMPIntrinsic(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT_i1(), lowerINT_TO_FP(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), lowerINT_TO_FP_vXi64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(), llvm::HexagonTargetLowering::LowerJumpTable(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerLabelRef(), lowerLaneOp(), LowerLoad(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), lowerLOADi1(), lowerLoadI1(), lowerMasksToReg(), LowerMemOpCallTo(), LowerMGATHER(), LowerMLOAD(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSACopyIntr(), lowerMSALoadIntr(), lowerMSASplatZExt(), lowerMSAStoreIntr(), LowerMSCATTER(), llvm::LanaiTargetLowering::LowerMUL(), LowerMUL(), LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), LowerMULO(), llvm::AArch64TargetLowering::LowerOperation(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), lowerOverflowArithmetic(), LowerPARITY(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), LowerPREFETCH(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), llvm::HexagonTargetLowering::LowerREADSTEADYCOUNTER(), lowerReductionSeq(), lowerRegToMasks(), llvm::AMDGPUTargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLE(), LowerRotate(), LowerSaturatingConditional(), LowerSCALAR_TO_VECTOR(), lowerScalarInsert(), lowerScalarSplat(), LowerSDIV(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), lowerSELECT(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), lowerSelectToBinOp(), LowerSELECTWithCmpZero(), llvm::SITargetLowering::lowerSET_FPENV(), llvm::SITargetLowering::lowerSET_ROUNDING(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), llvm::MSP430TargetLowering::LowerShifts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBitMask(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsInsertPS(), lowerShuffleAsLanePermuteAndSHUFP(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsShift(), lowerShuffleAsSpecificExtension(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleWithEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithSHUFPD(), lowerShuffleWithSHUFPS(), lowerShuffleWithSSE4A(), lowerShuffleWithUndefHalf(), lowerShuffleWithUNPCK(), lowerShuffleWithUNPCK256(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), LowerSMELdrStr(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::NVPTXTargetLowering::LowerSTACKRESTORE(), llvm::NVPTXTargetLowering::LowerSTACKSAVE(), llvm::SITargetLowering::LowerSTACKSAVE(), LowerSTORE(), LowerSTORE(), LowerStore(), lowerStoreF128(), lowerStoreI1(), lowerSTOREVector(), LowerSVEIntrinsicDUP(), LowerSVEIntrinsicEXT(), LowerSVEIntrinsicIndex(), LowerTcgen05St(), lowerToAddSubOrFMAddSub(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerTruncate(), LowerTruncatei1(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVectorStore(), llvm::HexagonTargetLowering::LowerUAddSubO(), LowerUADDSUBO_CARRY(), llvm::HexagonTargetLowering::LowerUAddSubOCarry(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV16F32Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV2X128Shuffle(), lowerV4F32Shuffle(), lowerV4F64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV4X128Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), LowerVecReduce(), LowerVecReduceMinMax(), lowerVECTOR_COMPRESS(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLE_ILVEV(), lowerVECTOR_SHUFFLE_ILVL(), lowerVECTOR_SHUFFLE_ILVOD(), lowerVECTOR_SHUFFLE_ILVR(), lowerVECTOR_SHUFFLE_PCKEV(), lowerVECTOR_SHUFFLE_PCKOD(), lowerVECTOR_SHUFFLE_SHF(), lowerVECTOR_SHUFFLE_VILVH(), lowerVECTOR_SHUFFLE_VILVL(), lowerVECTOR_SHUFFLE_VPACKEV(), lowerVECTOR_SHUFFLE_VPACKOD(), lowerVECTOR_SHUFFLE_VPICKEV(), lowerVECTOR_SHUFFLE_VPICKOD(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHF(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), lowerVECTOR_SHUFFLE_XVILVH(), lowerVECTOR_SHUFFLE_XVILVL(), lowerVECTOR_SHUFFLE_XVPERM(), lowerVECTOR_SHUFFLE_XVPICKEV(), lowerVECTOR_SHUFFLE_XVPICKOD(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsShift(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllEqual(), LowerVectorArith(), lowerVectorBitClear(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZ_GFNI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), LowerVectorExtend(), LowerVectorFP_TO_INT(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVectorINT_TO_FP(), lowerVectorIntrinsicScalars(), LowerVectorMatch(), lowerVectorSplatImm(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), LowerVSETCC(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowervXi8MulWithUNPCK(), lowerVZIP(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), lowerX86FPLogicOp(), LowerXALUO(), LowerXALUO(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), makeEquivalentMemoryOrdering(), llvm::SparcTargetLowering::makeHiLoPair(), llvm::VETargetLowering::makeHiLoPair(), matchBSwapHWordOrAndAnd(), matchMergedBFX(), matchPERM(), matchPMADDWD(), matchPMADDWD_2(), matchSplatAsGather(), matchTruncateWithPACK(), MatchVectorAllEqualTest(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowIndex(), narrowInsertExtractVectorBinOp(), narrowVectorSelect(), optimizeLogicalImm(), overflowFlagToValue(), packImage16bitOpsToDwords(), partitionShuffleOfConcats(), llvm::SITargetLowering::passSpecialInputs(), performActiveLaneMaskCombine(), performADDCombine(), performAddCombineForShiftedOperands(), performAddCombineSubShift(), PerformADDCombineWithOperands(), performAddCSelIntoCSinc(), PerformAddcSubcCombine(), performAddDotCombine(), PerformAddeSubeCombine(), performAddSubIntoVectorOp(), performAddSubLongCombine(), performAddUADDVCombine(), PerformADDVecReduce(), PerformANDCombine(), performANDCombine(), performANDCombine(), performANDCombine(), performANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), performAnyAllCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), PerformBITCASTCombine(), performBITCASTCombine(), performBitcastCombine(), performBITREV_WCombine(), performBITREVERSECombine(), performBR_CCCombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), performBSPExpandForSVE(), PerformBUILD_VECTORCombine(), performBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performBuildVectorCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCMovFPCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), performCONDCombine(), performCSELCombine(), PerformCSETCombine(), performCTLZCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), performDivRemCombine(), performDSPShiftCombine(), performDUPCombine(), performDupLane128Combine(), performExtBinopLoadFold(), PerformExtendCombine(), performExtendCombine(), performEXTRACT_VECTOR_ELTCombine(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performExtractLastActiveCombine(), performExtractSubvectorCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFADDCombine(), PerformFADDCombineWithOperands(), PerformFADDVCMLACombine(), PerformFAddVSelectCombine(), performFlagSettingCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performFPExtendCombine(), performFpToIntCombine(), performGatherLoadCombine(), performGLD1Combine(), performGlobalAddressCombine(), PerformHWLoopCombine(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performINTRINSIC_WO_CHAINCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), performIntrinsicCombine(), performIntToFpCombine(), performLD1Combine(), performLD1ReplicateCombine(), performLDNT1Combine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLongShiftCombine(), performLowerPartialReduction(), performMADD_MSUBCombine(), PerformMinMaxCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), PerformMULCombine(), performMULCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performMulCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performMulVectorCmpZeroCombine(), performMulVectorExtendCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformMVEVMULLCombine(), performNegCMovCombine(), performNegCSelCombine(), performNVCASTCombine(), PerformORCombine(), performORCombine(), performORCombine(), performORCombine(), PerformORCombine_i1(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), performOrXorChainCombine(), PerformPREDICATE_CASTCombine(), PerformReduceShuffleCombine(), PerformREMCombine(), performRNDRCombine(), performScalarToVectorCombine(), performScatterStoreCombine(), performSELECT_CCCombine(), PerformSELECTCombine(), performSELECTCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSelectCombine(), performSETCC_BITCASTCombine(), performSetccAddFolding(), PerformSETCCCombine(), performSETCCCombine(), performSETCCCombine(), performSETCCCombine(), performSETCCCombine(), performSetccMergeZeroCombine(), PerformShiftCombine(), performSHLCombine(), performSHLCombine(), performSHLCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSHLSimplify(), PerformShuffleVMOVNCombine(), performSIGN_EXTEND_INREGCombine(), performSignExtendCombine(), PerformSignExtendInregCombine(), performSignExtendInRegCombine(), performSignExtendSetCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSRACombine(), performSRACombine(), llvm::AMDGPUTargetLowering::performSraCombine(), performSRLCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performST1Combine(), performSTNT1Combine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), performSubAddMULCombine(), PerformSUBCombine(), performSUBCombine(), PerformSubCSINCCombine(), performSubsToAndsCombine(), performSunpkloCombine(), performSVEAndCombine(), performSVEMulAddSubCombine(), performTBZCombine(), performTRUNCATECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVAddCombine(), performUADDVCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), PerformUMLALCombine(), performUzpCombine(), PerformVCMPCombine(), PerformVCVTCombine(), PerformVDUPCombine(), PerformVDUPLANECombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), performVECREDUCECombine(), PerformVECTOR_REG_CASTCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), performVectorCompareAndMaskUnaryOpCombine(), performVectorDeinterleaveCombine(), performVectorExtCombine(), performVectorExtendCombine(), performVectorExtendToFPCombine(), performVectorNonNegToFPCombine(), performVectorTruncZeroCombine(), PerformVMOVDRRCombine(), PerformVMOVhrCombine(), PerformVMOVNCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), PerformVMulVCTPCombine(), performVP_REVERSECombine(), performVP_STORECombine(), performVP_TRUNCATECombine(), PerformVQDMULHCombine(), PerformVQDMULHCombine(), PerformVSELECTCombine(), PerformVSELECTCombine(), performVSELECTCombine(), performVSELECTCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), PerformXORCombine(), performXORCombine(), performXORCombine(), performZExtDeinterleaveShuffleCombine(), performZExtUZPCombine(), prepareDescriptorIndirectCall(), prepareIndirectCall(), PrepareTailCall(), prepareTS1AM(), PromoteBinOpToF32(), promoteExtBeforeAdd(), PromoteMaskArithmetic(), PromoteMaskArithmetic(), PromoteMVEPredVector(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), promoteVCIXScalar(), promoteXINT_TO_FP(), pushAddIntoCmovOfConsts(), reassociateCSELOperandsForCSE(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), recoverFramePointer(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), refineUniformBase(), ReorganizeVector(), ReplaceAddWithADDP(), ReplaceAllUsesWith(), ReplaceAllUsesWith(), ReplaceATOMIC_LOAD_128Results(), replaceAtomicSwap128(), ReplaceBITCAST(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), replaceCMP_XCHG_128Results(), ReplaceCopyFromReg_128(), replaceInChain(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), ReplaceLongIntrinsic(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceProxyReg(), ReplaceREADCYCLECOUNTER(), ReplaceReductionResults(), ReplaceTcgen05Ld(), replaceVecCondBranchResults(), replaceVPICKVE2GRResults(), resolveSources(), reverseZExtICmpCombine(), SaturateWidenedDIVFIX(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeExtractedBinOp(), llvm::TargetLowering::scalarizeExtractedVectorLoad(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), scalarizeVectorStore(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), signExtendBitcastSrcVector(), signExtendBitcastSrcVector(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::LoongArchTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyMul24(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCIntoEq(), simplifySetCCWithCTPOP(), sinkProxyReg(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), splatPartsI64WithVL(), llvm::AMDGPUTargetLowering::split64BitValue(), SplitAndExtendv16i1(), splitAndLowerShuffle(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), llvm::SITargetLowering::splitBinaryVectorOp(), SplitEVL(), SplitOpsAndApply(), SplitScalar(), splitStores(), splitStoreSplat(), SplitStrictFPVectorOp(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::SITargetLowering::splitUnaryVectorOp(), llvm::PPCTargetLowering::splitValueIntoRegisterParts(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), SplitVector(), llvm::AMDGPUTargetLowering::splitVector(), splitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), SplitVectorOp(), splitVectorOp(), SplitVectorReductionOp(), llvm::AMDGPUTargetLowering::SplitVectorStore(), splitVectorStore(), SplitVPOp(), splitVSETCC(), llvm::AMDGPUTargetLowering::storeStackInputValue(), stripModuloOnShift(), takeInexpensiveLog2(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), translateSetCCForBranch(), translateSetCCForBranch(), truncateAVX512SetCCNoBWI(), truncateScalarIntegerArg(), truncateVecElts(), truncateVecElts(), truncateVectorWithNARROW(), truncateVectorWithPACK(), truncateVectorWithPACKSS(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), TryCombineBaseUpdate(), tryCombineCRC32(), tryCombineExtendRShTrunc(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineMULLWithUZP1(), tryCombineNeonFcvtFP16ToI16(), tryCombineShiftImm(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), TryDistrubutionADDVecReduce(), tryExtendDUPToExtractHigh(), tryFoldMADwithSRL(), tryFoldSelectIntoOp(), tryFormConcatFromShuffle(), tryLowerToBSL(), tryLowerToSLI(), TryMatchTrue(), TryMULWIDECombine(), trySimplifySrlAddToRshrnb(), trySQDMULHCombine(), trySwapVSelectOperands(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), tryToFoldExtendSelectLoad(), tryToFoldExtOfAtomicLoad(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), tryToReplaceScalarFPConversionWithSVE(), tryToWidenSetCCOperands(), TryWideExtMulCombine(), unpack64(), unpackF64OnLA32DSoftABI(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), UnrollVectorOp(), UnrollVectorOverflowOp(), unrollVectorShift(), valueToCarryFlag(), vectorizeExtractedCast(), visitORCommutative(), widenAbs(), widenCtPop(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), WidenVector(), widenVectorOpsToi8(), widenVectorToPartType(), and WinDBZCheckDenominator().

◆ getNode() [5/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
ArrayRef< SDValue > Ops )

Definition at line 10891 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [6/24]

◆ getNode() [7/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2 )

Definition at line 7589 of file SelectionDAG.cpp.

References DL, and getNode().

◆ getNode() [8/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2,
const SDNodeFlags Flags )

Definition at line 7618 of file SelectionDAG.cpp.

References llvm::ISD::ABDS, llvm::ISD::ABDU, AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, AddNodeIDNode(), llvm::ISD::AND, assert(), llvm::ISD::AssertNoFPClass, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, canonicalizeCommutativeBinop(), llvm::cast(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::DELETED_NODE, DL, llvm::dyn_cast(), llvm::ISD::EntryToken, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMUL, FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FREM, llvm::ISD::FSUB, getAllOnesConstant(), getAnyExtOrTrunc(), llvm::SDNode::getAsZExtVal(), getConstant(), llvm::SDNode::getConstantOperandAPInt(), getDataLayout(), getExtractVectorElt(), getFPExtendOrRound(), getNode(), getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPOISON(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), getSExtOrTrunc(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::EVT::getSizeInBits(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), getVScale(), getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::ConstantSDNode::isAllOnes(), llvm::isConstOrConstSplat(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::ConstantSDNode::isZero(), llvm::Log2_32_Ceil(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, N, NewSDValueDbgMsg(), llvm::ISD::OR, llvm::ISD::POISON, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDSAT, llvm::ISD::SCMP, llvm::ISD::SDIV, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, simplifyFPBinop(), simplifyShift(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SSUBSAT, llvm::ISD::SUB, std::swap(), llvm::ISD::TargetConstant, llvm::to_underlying(), llvm::ISD::TokenFactor, llvm::ISD::UADDSAT, llvm::ISD::UCMP, llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UNDEF, llvm::ISD::UREM, llvm::ISD::USUBSAT, and llvm::ISD::XOR.

◆ getNode() [9/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2,
SDValue N3 )

Definition at line 8176 of file SelectionDAG.cpp.

References DL, and getNode().

◆ getNode() [10/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2,
SDValue N3,
const SDNodeFlags Flags )

Definition at line 8184 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddNodeIDNode(), assert(), llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::DELETED_NODE, DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMA, llvm::ISD::FMAD, FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), FoldSetCC(), llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::get(), llvm::SDNode::getAsAPIntVal(), llvm::SDNode::getAsZExtVal(), llvm::APInt::getBitsSet(), llvm::APInt::getBitWidth(), getDataLayout(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::hasKnownScalarFactor(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isFloatingPoint(), isGuaranteedNotToBePoison(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), isZero(), llvm_unreachable, N, NewSDValueDbgMsg(), llvm::ISD::POISON, SDValue(), llvm::ISD::SELECT, llvm::ISD::SETCC, simplifySelect(), llvm::ISD::UNDEF, llvm::ISD::VECTOR_COMPRESS, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VECTOR_SPLICE, and llvm::ISD::VSELECT.

◆ getNode() [11/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2,
SDValue N3,
SDValue N4 )

Definition at line 8446 of file SelectionDAG.cpp.

References DL, and getNode().

◆ getNode() [12/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2,
SDValue N3,
SDValue N4,
const SDNodeFlags Flags )

Definition at line 8439 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [13/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2,
SDValue N3,
SDValue N4,
SDValue N5 )

Definition at line 8461 of file SelectionDAG.cpp.

References DL, and getNode().

◆ getNode() [14/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue N1,
SDValue N2,
SDValue N3,
SDValue N4,
SDValue N5,
const SDNodeFlags Flags )

Definition at line 8454 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [15/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue Operand )

Definition at line 6435 of file SelectionDAG.cpp.

References DL, and getNode().

◆ getNode() [16/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
EVT VT,
SDValue Operand,
const SDNodeFlags Flags )

Definition at line 6443 of file SelectionDAG.cpp.

References llvm::ISD::ABS, AbstractManglingParser< Derived, Alloc >::Ops, AddNodeIDNode(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), llvm::ISD::BITREVERSE, llvm::EVT::bitsGT(), llvm::EVT::bitsLE(), llvm::EVT::bitsLT(), llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, ComputeNumSignBits(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DELETED_NODE, DL, llvm::ISD::EXTRACT_VECTOR_ELT, FoldBUILD_VECTOR(), FoldConstantArithmetic(), llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREEZE, llvm::APInt::getBitsSetFrom(), getConstant(), getConstantFP(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), getNode(), getNOT(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPOISON(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::EVT::getSizeInBits(), getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), getVScale(), getVTList(), llvm::SDNodeFlags::hasNonNeg(), llvm::isa(), llvm::EVT::isFloatingPoint(), isGuaranteedNotToBeUndefOrPoison(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm_unreachable, MaskedValueIsZero(), llvm::ISD::MERGE_VALUES, N, NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::ISD::POISON, llvm::ISD::SCALAR_TO_VECTOR, SDValue(), llvm::SDNodeFlags::setNonNeg(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, llvm::ISD::TargetConstant, llvm::ISD::TokenFactor, transferDbgValues(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.

◆ getNode() [17/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
SDVTList VTList )

Definition at line 11208 of file SelectionDAG.cpp.

References DL, and getNode().

◆ getNode() [18/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
SDVTList VTList,
ArrayRef< SDValue > Ops )

Definition at line 11027 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [19/24]

◆ getNode() [20/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
SDVTList VTList,
SDValue N )

Definition at line 11213 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [21/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
SDVTList VTList,
SDValue N1,
SDValue N2 )

Definition at line 11219 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [22/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
SDVTList VTList,
SDValue N1,
SDValue N2,
SDValue N3 )

Definition at line 11225 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [23/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
SDVTList VTList,
SDValue N1,
SDValue N2,
SDValue N3,
SDValue N4 )

Definition at line 11231 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNode() [24/24]

SDValue SelectionDAG::getNode ( unsigned Opcode,
const SDLoc & DL,
SDVTList VTList,
SDValue N1,
SDValue N2,
SDValue N3,
SDValue N4,
SDValue N5 )

Definition at line 11237 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, and getNode().

◆ getNodeIfExists() [1/2]

SDNode * SelectionDAG::getNodeIfExists ( unsigned Opcode,
SDVTList VTList,
ArrayRef< SDValue > Ops )

getNodeIfExists - Get the specified node if it's already available, or else return NULL.

Definition at line 11823 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, and getNodeIfExists().

◆ getNodeIfExists() [2/2]

◆ getNoMergeSiteInfo()

bool llvm::SelectionDAG::getNoMergeSiteInfo ( const SDNode * Node) const
inline

Return NoMerge info associated with Node.

Definition at line 2555 of file SelectionDAG.h.

References I.

◆ getNOT()

◆ getObjectPtrOffset() [1/2]

SDValue llvm::SelectionDAG::getObjectPtrOffset ( const SDLoc & SL,
SDValue Ptr,
SDValue Offset )
inline

◆ getObjectPtrOffset() [2/2]

◆ getOpcode_EXTEND()

unsigned llvm::SelectionDAG::getOpcode_EXTEND ( unsigned Opcode)
inlinestatic

◆ getOpcode_EXTEND_VECTOR_INREG()

unsigned llvm::SelectionDAG::getOpcode_EXTEND_VECTOR_INREG ( unsigned Opcode)
inlinestatic

◆ getOptLevel()

CodeGenOptLevel llvm::SelectionDAG::getOptLevel ( ) const
inline

Definition at line 497 of file SelectionDAG.h.

Referenced by llvm::FunctionLoweringInfo::set().

◆ getORE()

OptimizationRemarkEmitter & llvm::SelectionDAG::getORE ( ) const
inline

Definition at line 512 of file SelectionDAG.h.

◆ getPass()

const Pass * llvm::SelectionDAG::getPass ( ) const
inline

◆ getPCSections()

MDNode * llvm::SelectionDAG::getPCSections ( const SDNode * Node) const
inline

Return PCSections associated with Node, or nullptr if none exists.

Definition at line 2527 of file SelectionDAG.h.

◆ getPOISON()

◆ getPseudoProbeNode()

SDValue SelectionDAG::getPseudoProbeNode ( const SDLoc & Dl,
SDValue Chain,
uint64_t Guid,
uint64_t Index,
uint32_t Attr )

Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing, as well as the attributes attr of the probe.

Definition at line 9680 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddNodeIDNode(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), llvm::Guid, N, NewSDValueDbgMsg(), and SDValue().

◆ getPSI()

ProfileSummaryInfo * llvm::SelectionDAG::getPSI ( ) const
inline

Definition at line 513 of file SelectionDAG.h.

◆ getPtrExtendInReg()

SDValue SelectionDAG::getPtrExtendInReg ( SDValue Op,
const SDLoc & DL,
EVT VT )

Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value.

This may be either a zero extend or a sign extend.

Definition at line 1606 of file SelectionDAG.cpp.

References DL, and getZeroExtendInReg().

◆ getPtrExtOrTrunc()

SDValue SelectionDAG::getPtrExtOrTrunc ( SDValue Op,
const SDLoc & DL,
EVT VT )

Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics.

Definition at line 1600 of file SelectionDAG.cpp.

References DL, and getZExtOrTrunc().

Referenced by getLoadStackGuard().

◆ getReducedAlign()

Align SelectionDAG::getReducedAlign ( EVT VT,
bool UseABI )

In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack.

In such cases we attempt to break the vector down to a legal type and return the ABI alignment for that instead.

Definition at line 2693 of file SelectionDAG.cpp.

References DL, getContext(), getDataLayout(), getMachineFunction(), llvm::TargetFrameLowering::getStackAlign(), llvm::EVT::getTypeForEVT(), and llvm::EVT::isVector().

Referenced by llvm::TargetLowering::expandVECTOR_COMPRESS(), and llvm::TargetLowering::expandVectorSplice().

◆ getRegister()

SDValue SelectionDAG::getRegister ( Register Reg,
EVT VT )

Definition at line 2323 of file SelectionDAG.cpp.

References AddNodeIDNode(), getVTList(), N, llvm::ISD::Register, and SDValue().

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), buildCallOperands(), createCMovFP(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), emitLockedStackOp(), EmitUnrolledSetTag(), extractPtrauthBlendDiscriminators(), extractPtrauthBlendDiscriminators(), getADAEntry(), llvm::MipsTargetLowering::getAddrGPRel(), getCopyFromReg(), getCopyFromReg(), getCopyToReg(), getCopyToReg(), getDefaultScalableVLOps(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), llvm::MipsTargetLowering::getGlobalReg(), llvm::MipsTargetLowering::getOpndList(), getPopFromX87Reg(), getPrefetchNode(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), lowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), llvm::SITargetLowering::PostISelFolding(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), selectConstantAddr(), llvm::PPCTargetLowering::SelectForceXFormMode(), selectImmSeq(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), selectSOffset(), and splatPartsI64WithVL().

◆ getRegisterMask()

◆ getRoot()

◆ getScatterVP()

◆ getSelect()

SDValue llvm::SelectionDAG::getSelect ( const SDLoc & DL,
EVT VT,
SDValue Cond,
SDValue LHS,
SDValue RHS,
SDNodeFlags Flags = SDNodeFlags() )
inline

Helper function to make it easier to build Select's if you just have operands and don't want to check for vector.

Definition at line 1343 of file SelectionDAG.h.

References assert(), Cond, DL, getNode(), LHS, RHS, llvm::ISD::SELECT, and llvm::ISD::VSELECT.

Referenced by llvm::TargetLowering::BuildUDIV(), combineAnd(), combineAndnp(), combineConcatVectorOps(), combineFMinNumFMaxNum(), combineLogicBlendIntoPBLENDV(), combineMaskedLoadConstantMask(), combineSelect(), commuteSelect(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorFindLastActive(), foldBinOpIntoSelectIfProfitable(), foldBinOpIntoSelectIfProfitable(), foldSelectWithIdentityConstant(), llvm::TargetLowering::getNegatedExpression(), LowerADDSAT_SUBSAT(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), LowerFMINIMUM_FMAXIMUM(), lowerFREM(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), lowerINT_TO_FP_vXi64(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), lowerSELECT(), LowerShift(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBlend(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerZERO_EXTEND_Mask(), narrowExtractedVectorSelect(), PerformADDCombineWithOperands(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSelectCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), signExtendBitcastSrcVector(), signExtendBitcastSrcVector(), takeInexpensiveLog2(), tryFoldSelectIntoOp(), tryToFoldExtendOfConstant(), tryToFoldExtendSelectLoad(), UnrollVectorOverflowOp(), and useInversedSetcc().

◆ getSelectCC()

◆ getSelectionDAGInfo()

const SelectionDAGTargetInfo & llvm::SelectionDAG::getSelectionDAGInfo ( ) const
inline

◆ getSetCC()

SDValue llvm::SelectionDAG::getSetCC ( const SDLoc & DL,
EVT VT,
SDValue LHS,
SDValue RHS,
ISD::CondCode Cond,
SDValue Chain = SDValue(),
bool IsSignaling = false )
inline

Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue.

Definition at line 1314 of file SelectionDAG.h.

References assert(), Cond, DL, getCondCode(), getNode(), llvm::EVT::isVector(), LHS, RHS, llvm::ISD::SETCC, llvm::ISD::SETCC_INVALID, llvm::ISD::STRICT_FSETCC, and llvm::ISD::STRICT_FSETCCS.

Referenced by llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), combineAdd(), combineAnd(), combineBitcast(), combineExtractVectorElt(), combineExtSetcc(), combineFMinNumFMaxNum(), combineOr(), combinePredicateReduction(), combineSelect(), combineSetCC(), combineShiftAnd1ToBitTest(), combineSubOfBoolean(), combineToExtendBoolVectorInReg(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVectorSizedSetCCEquality(), combineVSelectWithAllOnesOrZeros(), commuteSelect(), ConvertCarryFlagToCarryValue(), convertIntLogicToFPLogic(), llvm::TargetLowering::CTTZTableLookup(), emitOrXorXorTree(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandVECTOR_COMPRESS(), foldAndOrOfSETCC(), FoldSetCC(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldVectorXorShiftIntoCmp(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), getDataClassTest(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), llvm::AMDGPUTargetLowering::getScaledLogInput(), llvm::TargetLowering::getSqrtInputTest(), llvm::TargetLowering::LegalizeSetCCCondCode(), lower1BitShuffle(), LowerADDSAT_SUBSAT(), lowerBUILD_VECTOR(), lowerCttzElts(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), LowerEXTEND_VECTOR_INREG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), lowerFMAXIMUM_FMINIMUM(), LowerFMINIMUM_FMAXIMUM(), llvm::HexagonTargetLowering::LowerFormalArguments(), lowerFREM(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::SITargetLowering::lowerGET_ROUNDING(), lowerINT_TO_FP_vXi64(), LowerIntVSETCC_AVX512(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUAddSubO(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVectorCTLZInRegLUT(), LowerVSETCC(), performBitcastCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMulVectorCmpZeroCombine(), performOrXorChainCombine(), performSELECTCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSETCCCombine(), performSETCCCombine(), performSETCCCombine(), performSignExtendSetCCCombine(), performVSelectCombine(), performXORCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), reverseZExtICmpCombine(), scalarizeExtractedBinOp(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::TargetLowering::softenSetCCOperands(), truncateAVX512SetCCNoBWI(), tryDemorganOfBooleanCondition(), trySwapVSelectOperands(), useInversedSetcc(), and widenVectorOpsToi8().

◆ getSetCCVP()

SDValue llvm::SelectionDAG::getSetCCVP ( const SDLoc & DL,
EVT VT,
SDValue LHS,
SDValue RHS,
ISD::CondCode Cond,
SDValue Mask,
SDValue EVL )
inline

Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an SDValue.

Definition at line 1331 of file SelectionDAG.h.

References assert(), Cond, DL, getCondCode(), getNode(), LHS, RHS, and llvm::ISD::SETCC_INVALID.

Referenced by llvm::TargetLowering::LegalizeSetCCCondCode().

◆ getSetFPEnv()

◆ getSExtOrTrunc()

◆ getShiftAmountConstant() [1/2]

SDValue SelectionDAG::getShiftAmountConstant ( const APInt & Val,
EVT VT,
const SDLoc & DL )

◆ getShiftAmountConstant() [2/2]

SDValue SelectionDAG::getShiftAmountConstant ( uint64_t Val,
EVT VT,
const SDLoc & DL )

Definition at line 1806 of file SelectionDAG.cpp.

References assert(), DL, getConstant(), getDataLayout(), and llvm::EVT::isInteger().

Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), combineExtractWithShuffle(), combinePMULH(), combineXorToBitfieldInsert(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), expandMulToNAFSequence(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVPCTPOP(), extractShiftForRotate(), foldSubCtlzNot(), foldVSelectToSignBitSplatMask(), llvm::TargetLowering::forceExpandMultiply(), llvm::TargetLowering::forceExpandWideMUL(), getCopyFromParts(), getCopyToParts(), GetExponent(), getLimitedPrecisionExp2(), getShiftAmountConstant(), llvm::AMDGPUTargetLowering::loadInputValue(), LowerCTPOP(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), matchBSwapHWordOrAndAnd(), llvm::SITargetLowering::passSpecialInputs(), performBitcastCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), and visitORCommutative().

◆ getShiftAmountOperand()

SDValue SelectionDAG::getShiftAmountOperand ( EVT LHSTy,
SDValue Op )

Return the specified value casted to the target's desired shift amount type.

getShiftAmountOperand - Return the specified value casted to the target's desired shift amount type.

Definition at line 2463 of file SelectionDAG.cpp.

References getDataLayout(), getZExtOrTrunc(), and llvm::EVT::isVector().

Referenced by LowerCTPOP(), and UnrollVectorOp().

◆ getSignedConstant()

◆ getSignedTargetConstant()

◆ getSplat()

SDValue llvm::SelectionDAG::getSplat ( EVT VT,
const SDLoc & DL,
SDValue Op )
inline

Returns a node representing a splat of one value into all lanes of the provided vector type.

This is a utility which returns either a BUILD_VECTOR or SPLAT_VECTOR depending on the scalability of the desired vector type.

Definition at line 918 of file SelectionDAG.h.

References assert(), DL, getSplatBuildVector(), getSplatVector(), llvm::EVT::isScalableVector(), and llvm::EVT::isVector().

Referenced by combineToExtendBoolVectorInReg(), llvm::TargetLowering::expandVPCTTZElements(), getConstant(), getConstantFP(), lowerVECTOR_SHUFFLE(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), refineUniformBase(), scalarizeBinOpOfSplats(), and takeInexpensiveLog2().

◆ getSplatBuildVector()

SDValue llvm::SelectionDAG::getSplatBuildVector ( EVT VT,
const SDLoc & DL,
SDValue Op )
inline

◆ getSplatSourceVector()

◆ getSplatValue()

SDValue SelectionDAG::getSplatValue ( SDValue V,
bool LegalTypes = false )

If V is a splat vector, return its scalar source operand by extracting that element from the source vector.

If LegalTypes is true, this method may only return a legally-typed splat value. If it cannot legalize the splatted value it will return SDValue().

Definition at line 3236 of file SelectionDAG.cpp.

References llvm::EVT::bitsLT(), getContext(), getExtractVectorElt(), llvm::EVT::getScalarType(), getSplatSourceVector(), llvm::EVT::isInteger(), and SDValue().

Referenced by canLowerSRLToRoundingShiftForVT(), findMoreOptimalIndexType(), foldIndexIntoBase(), PerformVSetCCToVCTPCombine(), and refineUniformBase().

◆ getSplatVector()

◆ GetSplitDestVTs()

std::pair< EVT, EVT > SelectionDAG::GetSplitDestVTs ( const EVT & VT) const

Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.

GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.

Definition at line 13504 of file SelectionDAG.cpp.

References getContext(), llvm::EVT::getHalfNumVectorElementsVT(), and llvm::EVT::isVector().

Referenced by llvm::TargetLowering::expandVectorNaryOpBySplitting(), LowerCVTPS2PH(), LowerMULO(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceReductionResults(), SplitStrictFPVectorOp(), llvm::SITargetLowering::splitTernaryVectorOp(), SplitVector(), SplitVectorOp(), splitVectorOp(), SplitVPOp(), and splitVSETCC().

◆ getSrcValue()

SDValue SelectionDAG::getSrcValue ( const Value * v)

Construct a node to track a Value* through the backend.

Definition at line 2398 of file SelectionDAG.cpp.

References AddNodeIDNode(), getVTList(), N, and SDValue().

◆ getStackArgumentTokenFactor()

SDValue SelectionDAG::getStackArgumentTokenFactor ( SDValue Chain)

Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.

getStackArgumentTokenFactor - Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.

This is used in tail call lowering to protect stack arguments from being clobbered.

Definition at line 8472 of file SelectionDAG.cpp.

References llvm::dyn_cast(), getEntryNode(), getNode(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::ISD::TokenFactor, and users.

◆ getStepVector() [1/2]

SDValue SelectionDAG::getStepVector ( const SDLoc & DL,
EVT ResVT )

Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...>

Definition at line 2115 of file SelectionDAG.cpp.

References DL, llvm::EVT::getScalarSizeInBits(), and getStepVector().

◆ getStepVector() [2/2]

◆ getStore() [1/4]

SDValue SelectionDAG::getStore ( SDValue Chain,
const SDLoc & dl,
SDValue Val,
SDValue Ptr,
MachineMemOperand * MMO )

◆ getStore() [2/4]

SDValue SelectionDAG::getStore ( SDValue Chain,
const SDLoc & dl,
SDValue Val,
SDValue Ptr,
MachinePointerInfo PtrInfo,
Align Alignment,
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
const AAMDNodes & AAInfo = AAMDNodes() )

Helper function to build ISD::STORE nodes.

This function will set the MOStore flag on MMOFlags, but you can set it if you want. The MOLoad and MOInvariant flags must not be set.

Definition at line 9874 of file SelectionDAG.cpp.

References assert(), getMachineFunction(), getStore(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, Ptr, Size, and llvm::MachinePointerInfo::V.

Referenced by combineStore(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), getIndexedStore(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getStore(), getStore(), getStore(), getTruncStore(), LowerATOMIC_STORE(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), LowerF128Store(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFP_TO_SINT_STORE(), LowerMemOpCallTo(), lowerMSAStoreIntr(), llvm::RISCVTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerReturn(), LowerSTORE(), LowerStore(), lowerStoreF128(), lowerStoreI1(), LowerTruncateVectorStore(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), LowerVASTART(), LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), memsetStore(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformTruncatingStoreCombine(), reduceMaskedStoreToScalarStore(), llvm::TargetLowering::scalarizeVectorStore(), scalarizeVectorStore(), ShrinkLoadReplaceStoreWithStore(), splitStores(), splitStoreSplat(), splitVectorStore(), llvm::AMDGPUTargetLowering::storeStackInputValue(), and StoreTailCallArgumentsToStackSlot().

◆ getStore() [3/4]

SDValue llvm::SelectionDAG::getStore ( SDValue Chain,
const SDLoc & dl,
SDValue Val,
SDValue Ptr,
MachinePointerInfo PtrInfo,
MaybeAlign Alignment = MaybeAlign(),
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
const AAMDNodes & AAInfo = AAMDNodes() )
inline

◆ getStore() [4/4]

◆ getStoreVP()

◆ getStrictFPExtendOrRound()

std::pair< SDValue, SDValue > SelectionDAG::getStrictFPExtendOrRound ( SDValue Op,
SDValue Chain,
const SDLoc & DL,
EVT VT )

Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation).

Definition at line 1478 of file SelectionDAG.cpp.

References assert(), llvm::EVT::bitsEq(), llvm::EVT::bitsGT(), DL, getIntPtrConstant(), llvm::SDValue::getNode(), getNode(), SDValue(), llvm::ISD::STRICT_FP_EXTEND, and llvm::ISD::STRICT_FP_ROUND.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), and LowerUINT_TO_FP_i32().

◆ getStridedLoadVP() [1/2]

SDValue SelectionDAG::getStridedLoadVP ( EVT VT,
const SDLoc & DL,
SDValue Chain,
SDValue Ptr,
SDValue Stride,
SDValue Mask,
SDValue EVL,
MachineMemOperand * MMO,
bool IsExpanding = false )

◆ getStridedLoadVP() [2/2]

◆ getStridedStoreVP()

◆ getStrlen()

◆ getSubtarget() [1/2]

◆ getSubtarget() [2/2]

template<typename STC>
const STC & llvm::SelectionDAG::getSubtarget ( ) const
inline

Definition at line 501 of file SelectionDAG.h.

◆ getSymbolFunctionGlobalAddress()

SDValue SelectionDAG::getSymbolFunctionGlobalAddress ( SDValue Op,
Function ** TargetFunction = nullptr )

Return a GlobalAddress of the function from the current module with name matching the given ExternalSymbol.

Additionally can provide the matched function. Panic if the function doesn't exist.

Definition at line 12714 of file SelectionDAG.cpp.

References assert(), llvm::cast(), llvm::GlobalValue::getAddressSpace(), getDataLayout(), llvm::Module::getFunction(), getGlobalAddress(), llvm::GlobalValue::getParent(), llvm::isa(), and llvm::report_fatal_error().

Referenced by llvm::NVPTXTargetLowering::LowerCall().

◆ getTarget()

◆ getTargetBlockAddress()

◆ getTargetConstant() [1/3]

SDValue llvm::SelectionDAG::getTargetConstant ( const APInt & Val,
const SDLoc & DL,
EVT VT,
bool isOpaque = false )
inline

Definition at line 711 of file SelectionDAG.h.

References DL, and getConstant().

◆ getTargetConstant() [2/3]

SDValue llvm::SelectionDAG::getTargetConstant ( const ConstantInt & Val,
const SDLoc & DL,
EVT VT,
bool isOpaque = false )
inline

Definition at line 715 of file SelectionDAG.h.

References DL, and getConstant().

◆ getTargetConstant() [3/3]

SDValue llvm::SelectionDAG::getTargetConstant ( uint64_t Val,
const SDLoc & DL,
EVT VT,
bool isOpaque = false )
inline

Definition at line 707 of file SelectionDAG.h.

References DL, and getConstant().

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), buildPCRelGlobalAddress(), buildRegSequence16(), buildRegSequence32(), llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), canonicalizeBitSelect(), llvm::AArch64TargetLowering::changeStreamingMode(), checkCVTFixedPointOperandWithFBits(), llvm::SITargetLowering::CollectTargetIntrinsicOperands(), combineADC(), combineAddOrSubToADCOrSBB(), combineAndMaskToShift(), combineAndOrForCcmpCtest(), combineBitcastToBoolVector(), combineBrCond(), combineCMov(), combineCommutableSHUFP(), combineCompareEqual(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractWithShuffle(), combineFP16_TO_FP(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineKSHIFT(), combineStore(), combineTargetShuffle(), llvm::VETargetLowering::combineTRUNCATE(), combineVectorShiftImm(), combineX86CloadCstore(), combineX86ShuffleChain(), combineX86SubCmpForFlags(), createGPRPairNode(), createGPRPairNode2xi32(), createMMXBuildVector(), createSetFPEnvNodes(), createVariablePermute(), EmitAVX512Test(), emitCmp(), emitLockedStackOp(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::RISCVSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), expandBitCastI128ToF128(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), expandFP_TO_UINT_SSE(), ExtractBitFromMaskVector(), extractPtrauthBlendDiscriminators(), extractPtrauthBlendDiscriminators(), llvm::PPC::get_VSPLTI_elt(), getADAEntry(), getAL(), getAVX2GatherNode(), getCopyFromParts(), getDataClassTest(), getGatherNode(), getGeneralPermuteNode(), getIntOperandsFromRegisterString(), getJumpTableDebugInfo(), getLeftShift(), getPack(), getPermuteNode(), getPrefetchNode(), getPTrue(), getScatterNode(), getSETCC(), getSHUFPDImmForMask(), getSPDenormModeValue(), getStepVector(), getTargetExtractSubreg(), getTargetInsertSubreg(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUniformBase(), getV4X86ShuffleImm8ForMask(), getVAArg(), getVShift(), getVSlidedown(), getVSlideup(), getZeroVector(), insert1BitVector(), InvertCarryFlag(), isVMOVModifiedImm(), isWorthFoldingIntoOrrWithShift(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), LowerABD(), LowerABS(), LowerADDRSPACECAST(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::PPCTargetLowering::LowerAsmOperandForConstraint(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), llvm::SITargetLowering::LowerAsmOperandForConstraint(), llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::VETargetLowering::lowerATOMIC_FENCE(), LowerBITREVERSE(), LowerBuildVectorv4x32(), llvm::SITargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), LowerCMP_SWAP(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), LowerCTTZ(), LowerCTTZ(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128Load(), LowerF128Store(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP2(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), llvm::AMDGPUTargetLowering::LowerFLOG2(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), LowerFMINIMUM_FMAXIMUM(), llvm::VETargetLowering::LowerFormalArguments(), LowerFP_TO_FP16(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), lowerGetVectorLength(), LowerINTRINSIC_W_CHAIN(), lowerLaneOp(), lowerLoadF128(), lowerLoadI1(), LowerMLOAD(), LowerMUL(), llvm::RISCVTargetLowering::LowerOperation(), LowerPREFETCH(), LowerPtrAuthGlobalAddressStatically(), lowerReductionSeq(), llvm::SITargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), LowerRotate(), LowerSELECTWithCmpZero(), llvm::SITargetLowering::lowerSET_FPENV(), llvm::SITargetLowering::lowerSET_ROUNDING(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsInsertPS(), lowerShuffleAsShift(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleWithSHUFPD(), lowerShuffleWithSSE4A(), LowerSMELdrStr(), LowerSTORE(), lowerStoreF128(), lowerStoreI1(), lowerUINT_TO_FP_vXi32(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2X128Shuffle(), lowerV4F64Shuffle(), lowerV8F64Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_SHF(), lowerVECTOR_SHUFFLE_VSHF(), lowerVECTOR_SHUFFLE_XVSHUF(), LowerVectorCTLZ_GFNI(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), LowerVectorMatch(), lowerVectorXRINT_XROUND(), LowerVSETCC(), optimizeLogicalImm(), llvm::packConstantV2I16(), parseTexFail(), performActiveLaneMaskCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), PerformHWLoopCombine(), PromoteMVEPredVector(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), llvm::PPCTargetLowering::SelectAddressRegImm(), selectConstantAddr(), selectI64Imm(), selectI64Imm(), selectI64ImmDirect(), selectI64ImmDirectPrefix(), selectImm(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), tryLowerToSLI(), tryOrrWithShift(), trySimplifySrlAddToRshrnb(), tryToConvertShuffleOfTbl2ToTbl4(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), and llvm::SITargetLowering::wrapAddr64Rsrc().

◆ getTargetConstantFP() [1/3]

SDValue llvm::SelectionDAG::getTargetConstantFP ( const APFloat & Val,
const SDLoc & DL,
EVT VT )
inline

Definition at line 746 of file SelectionDAG.h.

References DL, and getConstantFP().

◆ getTargetConstantFP() [2/3]

SDValue llvm::SelectionDAG::getTargetConstantFP ( const ConstantFP & Val,
const SDLoc & DL,
EVT VT )
inline

Definition at line 749 of file SelectionDAG.h.

References DL, and getConstantFP().

◆ getTargetConstantFP() [3/3]

SDValue llvm::SelectionDAG::getTargetConstantFP ( double Val,
const SDLoc & DL,
EVT VT )
inline

Definition at line 743 of file SelectionDAG.h.

References DL, and getConstantFP().

◆ getTargetConstantPool() [1/2]

◆ getTargetConstantPool() [2/2]

SDValue llvm::SelectionDAG::getTargetConstantPool ( MachineConstantPoolValue * C,
EVT VT,
MaybeAlign Align = std::nullopt,
int Offset = 0,
unsigned TargetFlags = 0 )
inline

Definition at line 786 of file SelectionDAG.h.

References llvm::CallingConv::C, getConstantPool(), and llvm::Offset.

◆ getTargetExternalSymbol()

◆ getTargetExtractSubreg()

SDValue SelectionDAG::getTargetExtractSubreg ( int SRIdx,
const SDLoc & DL,
EVT VT,
SDValue Operand )

A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.

getTargetExtractSubreg - A convenience function for creating TargetOpcode::EXTRACT_SUBREG nodes.

Definition at line 11803 of file SelectionDAG.cpp.

References DL, getMachineNode(), getTargetConstant(), and SDValue().

Referenced by llvm::SITargetLowering::buildRSRC(), convertToF16(), expandBitCastF128ToI128(), LowerF64Op(), LowerFNEGorFABS(), lowerGR128Binary(), lowerGR128ToI128(), LowerINTRINSIC_W_CHAIN(), narrowIfNeeded(), NarrowVector(), ReplaceCMP_SWAP_128Results(), and ReplaceCMP_SWAP_64Results().

◆ getTargetFrameIndex()

◆ getTargetGlobalAddress()

◆ getTargetInsertSubreg()

SDValue SelectionDAG::getTargetInsertSubreg ( int SRIdx,
const SDLoc & DL,
EVT VT,
SDValue Operand,
SDValue Subreg )

A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.

getTargetInsertSubreg - A convenience function for creating TargetOpcode::INSERT_SUBREG nodes.

Definition at line 11813 of file SelectionDAG.cpp.

References DL, getMachineNode(), getTargetConstant(), and SDValue().

Referenced by convertFromF16(), LowerF64Op(), LowerFNEGorFABS(), and Widen().

◆ getTargetJumpTable()

◆ getTargetLoweringInfo()

const TargetLowering & llvm::SelectionDAG::getTargetLoweringInfo ( ) const
inline

Definition at line 504 of file SelectionDAG.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), buildFromShuffleMostly(), canonicalizeShuffleWithOp(), combineAdd(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndNotOrIntoAndNotAnd(), combineAndnp(), combineAndShuffleNot(), combineBEXTR(), combineBinOpOfZExt(), combineBitcast(), combineBitcastToBoolVector(), combineBITREVERSE(), combineBT(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineExtractVectorElt(), combineFMA(), combineFMADDSUB(), combineFMinNumFMaxNum(), combineFneg(), combineGatherScatter(), combineKSHIFT(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLRINT_LLRINT(), combineMaskedLoad(), combineMaskedStore(), combineMOVMSK(), combineOr(), combinePDEP(), combinePMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAsExtAnd(), combineSelectOfTwoConstants(), combineSetCC(), combineShiftAnd1ToBitTest(), combineShuffle(), combineShuffleToFMAddSub(), combineStore(), combineTargetShuffle(), combineTESTP(), combineToVCPOP(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineTruncSelectToSMaxUSat(), combineVectorInsert(), combineVectorMulToSraBitcast(), combineVectorShiftImm(), combineVectorShiftVar(), combineVEXTRACT_STORE(), combineVPMADD(), combineVPMADD52LH(), combineVSelectToBLENDV(), combineVTRUNC(), combineX86GatherScatter(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), combineXor(), createMMXBuildVector(), createSetFPEnvNodes(), detectEvenOddMultiplyOperand(), EltsFromConsecutiveLoads(), expandBitCastF128ToI128(), expandBitCastI128ToF128(), ExpandPowI(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVectorFindLastActive(), foldAndOrOfSETCC(), foldBoolSelectToLogic(), foldCONCAT_VECTORS(), foldExtendedSignBitTest(), foldExtractSubvectorFromShuffleVector(), foldSelectWithIdentityConstant(), foldShuffleOfConcatUndefs(), foldSubCtlzNot(), foldToMaskedStore(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), formSplatFromShuffles(), getADAEntry(), getAddressForMemoryInput(), getAVX2GatherNode(), getAVX512Node(), getAVX512TruncNode(), getBT(), getConstVector(), getConstVector(), getContainerForFixedLengthVector(), getContainerForFixedLengthVector(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), getGatherNode(), getJumpTableDebugInfo(), getKnownUndefForVectorBinop(), getLifetimeNode(), getLoadStackGuard(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetValue(), getPredicateForFixedLengthVector(), getPredicateForScalableVector(), getPrefetchNode(), getPTest(), getRegistersForValue(), getScatterNode(), getSVEPredicateBitCast(), getTagSymNode(), getUniformBase(), getVCIXISDNodeWCHAIN(), getZeroVector(), getzOSCalleeAndADA(), getZT0FrameIndex(), isAddSubOrSubAdd(), isBLACompatibleAddress(), isConsecutiveLSLoc(), isKnownToBeAPowerOfTwo(), IsNOT(), isPackedVectorType(), LowerABD(), LowerADDRSPACECAST(), LowerADDSAT_SUBSAT(), LowerADDSUBO_CARRY(), LowerATOMIC_STORE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerCTPOP(), LowerCTPOP(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFMINIMUM_FMAXIMUM(), LowerFSINCOS(), lowerGR128ToI128(), lowerI128ToGR128(), LowerMemOpCallTo(), LowerMSCATTER(), LowerMULO(), LowerRotate(), LowerShiftParts(), lowerShuffleAsElementInsertion(), lowerShuffleAsShift(), LowerStore(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), LowerVASTART(), LowerVASTART(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsShift(), LowerVectorAllEqual(), LowerVSETCC(), LowerXALUO(), matchLSNode(), matchRotateSub(), matchSplatAsGather(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), narrowInsertExtractVectorBinOp(), narrowShuffle(), patchMatchingInput(), performAddCSelIntoCSinc(), performAddSubIntoVectorOp(), PerformANDCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), performBuildVectorCombine(), performConcatVectorsCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformExtendCombine(), PerformExtractEltToVMOVRRD(), performExtractLastActiveCombine(), PerformFADDCombineWithOperands(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performFpToIntCombine(), performGatherLoadCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), PerformLOADCombine(), PerformMinMaxFpToSatCombine(), PerformORCombine(), PerformPREDICATE_CASTCombine(), performScatterStoreCombine(), performSelectCombine(), PerformShiftCombine(), PerformSTORECombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), performVectorDeinterleaveCombine(), PerformVMOVhrCombine(), PerformVMOVNCombine(), performVMSKLTZCombine(), performVP_TRUNCATECombine(), PerformVQMOVNCombine(), PerformVSetCCToVCTPCombine(), PerformXORCombine(), performXORCombine(), PromoteMaskArithmetic(), reduceBuildVecToShuffleWithZero(), refineIndexType(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), scalarizeExtractedBinOp(), shouldTransformMulToShiftsAddsSubs(), ShrinkLoadReplaceStoreWithStore(), simplifyMul24(), transformCallee(), tryWidenMaskForShuffle(), tryWidenMaskForShuffle(), widenAbs(), widenBuildVec(), widenCtPop(), widenShuffleMask(), and widenVectorToPartType().

◆ getTokenFactor()

◆ getTruncStore() [1/3]

SDValue SelectionDAG::getTruncStore ( SDValue Chain,
const SDLoc & dl,
SDValue Val,
SDValue Ptr,
EVT SVT,
MachineMemOperand * MMO )

Definition at line 9970 of file SelectionDAG.cpp.

References getStore(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getTruncStore() [2/3]

◆ getTruncStore() [3/3]

SDValue llvm::SelectionDAG::getTruncStore ( SDValue Chain,
const SDLoc & dl,
SDValue Val,
SDValue Ptr,
MachinePointerInfo PtrInfo,
EVT SVT,
MaybeAlign Alignment = MaybeAlign(),
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
const AAMDNodes & AAInfo = AAMDNodes() )
inline

Definition at line 1519 of file SelectionDAG.h.

References getEVTAlign(), getTruncStore(), llvm::MachineMemOperand::MONone, and Ptr.

◆ getTruncStoreVP() [1/2]

◆ getTruncStoreVP() [2/2]

◆ getTruncStridedStoreVP()

◆ getUNDEF()

SDValue llvm::SelectionDAG::getUNDEF ( EVT VT)
inline

Return an UNDEF node. UNDEF does not have a useful SDLoc.

Definition at line 1175 of file SelectionDAG.h.

References getNode(), and llvm::ISD::UNDEF.

Referenced by addShuffleForVecExtend(), buildFromShuffleMostly(), buildMergeScalars(), buildScalarToVector(), llvm::TargetLowering::BuildUDIV(), canonicalizeShuffleMaskWithHorizOp(), collectConcatOps(), CollectOpsToWiden(), combineArithReduction(), combineBasicSADPattern(), combineBinOpToReduce(), combineBitcast(), combineBitcastToBoolVector(), combineBlendOfPermutes(), combineBVOfConsecutiveLoads(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfExtracts(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFP_EXTEND(), combineFP_TO_xINT_SAT(), combineINSERT_SUBVECTOR(), combineLRINT_LLRINT(), combineMaskedLoadConstantMask(), combineSelect(), combineSetCCAtomicArith(), combineShuffleOfBitcast(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineSVEReductionOrderedFP(), combineTargetShuffle(), combineToHorizontalAddSub(), combineTruncateWithSat(), combineTruncToVnclip(), combineVectorPack(), combineVPDPBUSDPattern(), combineVqdotAccum(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), combineXorSubCTLZ(), CompactSwizzlableVector(), concatSubVectors(), convertLocVTToValVT(), convertShiftLeftToScale(), convertToScalableVector(), convertToScalableVector(), createMMXBuildVector(), EltsFromConsecutiveLoads(), emitErrorAndReplaceIntrinsicResults(), emitFloatCompareMask(), emitIntrinsicWithChainErrorMessage(), EmitTruncSStore(), emitVectorComparison(), ExpandBVWithShuffles(), ExpandHorizontalBinOp(), expandV4F32ToV2F64(), ExtendToType(), extractSubVector(), FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), FoldConstantBuildVector(), foldConstantFPMath(), foldExtractSubvectorFromShuffleVector(), FoldSetCC(), getConstVector(), getConstVector(), getCopyFromPartsVector(), getDeinterleaveShiftAndTrunc(), getExtLoad(), getExtLoad(), getExtLoadVP(), getExtLoadVP(), getExtStridedLoadVP(), getGeneralPermuteNode(), getHopForBuildVector(), getInvertedVectorForFMA(), getKnownUndefForVectorBinop(), getLoad(), getLoad(), getLoadVP(), getLoadVP(), getNode(), getNode(), getNode(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getSplatSourceVector(), getStore(), getStridedLoadVP(), getTargetVShiftNode(), getTruncStore(), getTruncStoreVP(), getTruncStridedStoreVP(), getVectorShuffle(), getVectorShuffle(), getWideningInterleave(), insert1BitVector(), isAddSubOrSubAdd(), isFNEG(), isHopBuildVector(), isHorizontalBinOpPart(), joinDwords(), lower1BitShuffle(), LowerAsSplatVectorLoad(), lowerAtomicArith(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), lowerBuildVectorViaDominantValues(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), LowerCTTZ(), lowerDisjointIndicesShuffle(), LowerEXTEND_VECTOR_INREG(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), LowerFLDEXP(), lowerFMAXIMUM_FMINIMUM(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::R600TargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerINT_TO_FP_vXi64(), LowerINTRINSIC_W_CHAIN(), llvm::MipsTargetLowering::lowerLOAD(), LowerMSCATTER(), LowerMUL(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateStore(), lowerReductionSeq(), LowerSCALAR_TO_VECTOR(), lowerScalarInsert(), lowerScalarSplat(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSpecificExtension(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithSSE4A(), lowerShuffleWithUndefHalf(), lowerShuffleWithUNPCK256(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerTruncateVectorStore(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerVECTOR_COMPRESS(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_XVPERM(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVZIP(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsInsertPS(), matchShuffleWithUNPCK(), matchSplatAsGather(), NormalizeBuildVector(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performBuildVectorCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performDupLane128Combine(), performLDNT1Combine(), PerformMinMaxCombine(), performMulCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performSHLCombine(), performSPLIT_PAIR_F64Combine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSTNT1Combine(), PerformTruncatingStoreCombine(), performUnpackCombine(), performUzpCombine(), PerformVECTOR_REG_CASTCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), performVP_TRUNCATECombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), ReplaceAddWithADDP(), replaceAtomicSwap128(), ReplaceCMP_SWAP_64Results(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), simplifyFPBinop(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), simplifyShift(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), truncateVectorWithPACK(), tryBuildVectorShuffle(), tryCombineMULLWithUZP1(), tryToFoldExtendOfConstant(), tryToReplaceScalarFPConversionWithSVE(), UnrollVectorOp(), UnrollVectorOverflowOp(), vectorizeExtractedCast(), widenSubVector(), widenVec(), WidenVector(), WidenVector(), and widenVectorToPartType().

◆ getUniformityInfo()

const UniformityInfo * llvm::SelectionDAG::getUniformityInfo ( ) const
inline

Definition at line 507 of file SelectionDAG.h.

Referenced by llvm::FunctionLoweringInfo::set().

◆ getVAArg()

SDValue SelectionDAG::getVAArg ( EVT VT,
const SDLoc & dl,
SDValue Chain,
SDValue Ptr,
SDValue SV,
unsigned Align )

VAArg produces a result and token chain, and takes a pointer and a source value as input.

Definition at line 10869 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, getNode(), getTargetConstant(), getVTList(), and Ptr.

◆ getValidMaximumShiftAmount() [1/2]

std::optional< unsigned > SelectionDAG::getValidMaximumShiftAmount ( SDValue V,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.

Definition at line 3346 of file SelectionDAG.cpp.

References assert(), llvm::Depth, getValidShiftAmountRange(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by canCreateUndefOrPoison(), getValidMaximumShiftAmount(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyMultipleUseDemandedBits().

◆ getValidMaximumShiftAmount() [2/2]

std::optional< unsigned > SelectionDAG::getValidMaximumShiftAmount ( SDValue V,
unsigned Depth = 0 ) const

If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.

Definition at line 3358 of file SelectionDAG.cpp.

References llvm::Depth, llvm::APInt::getAllOnes(), getValidMaximumShiftAmount(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

◆ getValidMinimumShiftAmount() [1/2]

std::optional< unsigned > SelectionDAG::getValidMinimumShiftAmount ( SDValue V,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.

Definition at line 3325 of file SelectionDAG.cpp.

References assert(), llvm::Depth, getValidShiftAmountRange(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by combineGatherScatter(), computeKnownBits(), ComputeNumSignBits(), and getValidMinimumShiftAmount().

◆ getValidMinimumShiftAmount() [2/2]

std::optional< unsigned > SelectionDAG::getValidMinimumShiftAmount ( SDValue V,
unsigned Depth = 0 ) const

If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.

Definition at line 3337 of file SelectionDAG.cpp.

References llvm::Depth, llvm::APInt::getAllOnes(), getValidMinimumShiftAmount(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

◆ getValidShiftAmount() [1/2]

std::optional< unsigned > SelectionDAG::getValidShiftAmount ( SDValue V,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it.

Definition at line 3303 of file SelectionDAG.cpp.

References assert(), llvm::Depth, getValidShiftAmountRange(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by checkSignTestSetCCCombine(), combinei64TruncSrlConstant(), getValidShiftAmount(), matchTruncateWithPACK(), and llvm::TargetLowering::SimplifyDemandedBits().

◆ getValidShiftAmount() [2/2]

std::optional< unsigned > SelectionDAG::getValidShiftAmount ( SDValue V,
unsigned Depth = 0 ) const

If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it.

Definition at line 3316 of file SelectionDAG.cpp.

References llvm::Depth, llvm::APInt::getAllOnes(), getValidShiftAmount(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

◆ getValidShiftAmountRange()

std::optional< ConstantRange > SelectionDAG::getValidShiftAmountRange ( SDValue V,
const APInt & DemandedElts,
unsigned Depth ) const

If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the valid constant range.

Definition at line 3254 of file SelectionDAG.cpp.

References assert(), llvm::BitWidth, computeKnownBits(), llvm::Depth, llvm::dyn_cast(), llvm::ConstantRange::fromKnownBits(), llvm::KnownBits::getMaxValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::APInt::uge(), llvm::APInt::ugt(), and llvm::APInt::ult().

Referenced by ComputeNumSignBits(), getValidMaximumShiftAmount(), getValidMinimumShiftAmount(), and getValidShiftAmount().

◆ getValueType()

SDValue SelectionDAG::getValueType ( EVT VT)

Definition at line 2033 of file SelectionDAG.cpp.

References llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::EVT::isSimple(), N, SDValue(), and llvm::MVT::SimpleTy.

Referenced by addShuffleForVecExtend(), combineShiftRightArithmetic(), convertLocVTToValVT(), customLegalizeToWOpWithSExt(), customLegalizeToWOpWithSExt(), emitRepmovs(), emitRepstos(), FoldConstantArithmetic(), getAArch64Cmp(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getNode(), getNode(), LowerBUILD_VECTOR_i1(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::LowerCallResult(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::SITargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP_TO_INT_SAT(), LowerINSERT_VECTOR_ELT_i1(), lowerMSACopyIntr(), llvm::MSP430TargetLowering::LowerShifts(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performGatherLoadCombine(), performLD1Combine(), PerformMinMaxCombine(), PerformMinMaxFpToSatCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), performScatterStoreCombine(), performSETCCCombine(), performSignExtendCombine(), performSignExtendInRegCombine(), performSRACombine(), performST1Combine(), PerformUMinFpToSatCombine(), PromoteMaskArithmetic(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceVPICKVE2GRResults(), scalarizeExtractedBinOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::softenSetCCOperands(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateScalarIntegerArg(), truncateVectorWithPACKSS(), UnpackFromArgumentSlot(), UnrollVectorOp(), and unrollVectorShift().

◆ getVectorIdxConstant()

SDValue SelectionDAG::getVectorIdxConstant ( uint64_t Val,
const SDLoc & DL,
bool isTarget = false )

Definition at line 1819 of file SelectionDAG.cpp.

References DL, getConstant(), and getDataLayout().

Referenced by buildFromShuffleMostly(), combineArithReduction(), combineAVX512SetCCToKMOV(), combineBitcast(), combineBitcastToBoolVector(), combineCompareEqual(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFP16_TO_FP(), combineFP_EXTEND(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineKSHIFT(), combineMinMaxReduction(), combineSelect(), combineTargetShuffle(), combineTruncateWithSat(), combineVectorSizedSetCCEquality(), convertIntLogicToFPLogic(), CustomNonLegalBITCASTResults(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), ExtendToType(), ExtractBitFromMaskVector(), foldExtractSubvectorFromShuffleVector(), GeneratePerfectShuffle(), getCopyFromPartsVector(), getCopyToPartsVector(), getDataClassTest(), getExtractSubvector(), getExtractVectorElt(), getExtractVectorizedValue(), getInsertSubvector(), getInsertVectorElt(), getMaskNode(), getScalarMaskingNode(), getShuffleHalfVectors(), insert1BitVector(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), lowerAddSubToHorizontalOp(), LowerAVXCONCAT_VECTORS(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORvXi1(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerCONCAT_VECTORSvXi1(), LowerEXTRACT_SUBVECTOR(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFMINIMUM_FMAXIMUM(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), lowerFPToIntToFP(), LowerFSINCOS(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP_vXi64(), lowerLaneOp(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerZERO_EXTEND_Mask(), matchPMADDWD_2(), narrowExtractedVectorBinOp(), performBuildVectorCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performSunpkloCombine(), performTruncateCombine(), PerformVQDMULHCombine(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), scalarizeVectorStore(), SplitAndExtendv16i1(), SplitVector(), llvm::AMDGPUTargetLowering::splitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryToReplaceScalarFPConversionWithSVE(), vectorizeExtractedCast(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), and widenVectorToPartType().

◆ getVectorShuffle()

SDValue SelectionDAG::getVectorShuffle ( EVT VT,
const SDLoc & dl,
SDValue N1,
SDValue N2,
ArrayRef< int > Mask )

Return an ISD::VECTOR_SHUFFLE node.

The number of elements in VT, which must be a vector type, must match the number of mask elements NumElts. An integer mask element equal to -1 is treated as undefined.

Definition at line 2142 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddNodeIDNode(), llvm::all_of(), assert(), commuteShuffle(), llvm::copy(), llvm::dyn_cast(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getNode(), llvm::SDNode::getOperand(), getSplatBuildVector(), llvm::BuildVectorSDNode::getSplatValue(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::isNullConstant(), llvm::SDValue::isUndef(), N, NewSDValueDbgMsg(), llvm::BitVector::none(), llvm::Offset, SDValue(), llvm::Splat, and llvm::ISD::VECTOR_SHUFFLE.

Referenced by addShuffleForVecExtend(), buildFromShuffleMostly(), llvm::TargetLowering::buildLegalVectorShuffle(), BuildVSLDOI(), combineAddOfPMADDWD(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBITREVERSE(), combineBlendOfPermutes(), combineBVOfConsecutiveLoads(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineFP_ROUND(), combineHorizOpWithShuffle(), combineINSERT_SUBVECTOR(), combineMinMaxReduction(), combinePMULDQ(), combineSelect(), combineShuffleOfBitcast(), combineShuffleOfSplatVal(), combineSIntToFP(), combineToExtendBoolVectorInReg(), combineToHorizontalAddSub(), combineVPDPBUSDPattern(), createVariablePermute(), EltsFromConsecutiveLoads(), ExpandBVWithShuffles(), expandV4F32ToV2F64(), foldExtractSubvectorFromShuffleVector(), foldShuffleOfConcatUndefs(), formSplatFromShuffles(), GeneratePerfectShuffle(), getCommutedVectorShuffle(), getPack(), getScalarMaskingNode(), getShuffleHalfVectors(), getShuffleVectorZeroOrUndef(), getSToVPermuted(), getTargetVShiftNode(), getVectorShuffle(), isFNEG(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerAsSplatVectorLoad(), lowerBuildVectorAsBlend(), LowerBuildVectorv4x32(), LowerConvertLow(), lowerDisjointIndicesShuffle(), LowerEXTEND_VECTOR_INREG(), LowerMUL(), LowerMULH(), LowerReverse_VECTOR_SHUFFLE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsLanePermuteAndSHUFP(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSpecificExtension(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithUNPCK256(), LowerSIGN_EXTEND(), lowerToAddSubOrFMAddSub(), LowerTruncateVecI1(), LowerUINT_TO_FP_i64(), lowerV16I8Shuffle(), lowerV2I64Shuffle(), lowerV4I32Shuffle(), lowerV8F16Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(), lowerVECTOR_SHUFFLEAsVRGatherVX(), LowerVECTOR_SHUFFLEUsingMovs(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), partitionShuffleOfConcats(), performBuildShuffleExtendCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performMulCombine(), performSelectCombine(), PerformTruncatingStoreCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), PerformVQDMULHCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), ReplaceAddWithADDP(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), splitAndLowerShuffle(), truncateVectorWithPACK(), tryWidenMaskForShuffle(), tryWidenMaskForShuffle(), vectorizeExtractedCast(), and widenShuffleMask().

◆ getVPLogicalNOT()

SDValue SelectionDAG::getVPLogicalNOT ( const SDLoc & DL,
SDValue Val,
SDValue Mask,
SDValue EVL,
EVT VT )

Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL).

Definition at line 1626 of file SelectionDAG.cpp.

References DL, getBoolConstant(), and getNode().

◆ getVPPtrExtOrTrunc()

SDValue SelectionDAG::getVPPtrExtOrTrunc ( const SDLoc & DL,
EVT VT,
SDValue Op,
SDValue Mask,
SDValue EVL )

Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT, by either truncating it or performing either vector-predicated zero or sign extension as appropriate extension for the pointer's semantics.

This function just redirects to getVPZExtOrTrunc right now.

Definition at line 1632 of file SelectionDAG.cpp.

References DL, and getVPZExtOrTrunc().

◆ getVPZeroExtendInReg()

SDValue SelectionDAG::getVPZeroExtendInReg ( SDValue Op,
SDValue Mask,
SDValue EVL,
const SDLoc & DL,
EVT VT )

Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.

Definition at line 1581 of file SelectionDAG.cpp.

References assert(), llvm::EVT::bitsLE(), DL, getConstant(), llvm::APInt::getLowBitsSet(), getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementCount(), llvm::EVT::isInteger(), and llvm::EVT::isVector().

◆ getVPZExtOrTrunc()

SDValue SelectionDAG::getVPZExtOrTrunc ( const SDLoc & DL,
EVT VT,
SDValue Op,
SDValue Mask,
SDValue EVL )

Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT, by performing either vector-predicated zext or truncating it.

The Op will be returned as-is if Op and VT are vectors containing integer with same width.

Definition at line 1637 of file SelectionDAG.cpp.

References llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), DL, and getNode().

Referenced by getVPPtrExtOrTrunc().

◆ getVRegDbgValue()

SDDbgValue * SelectionDAG::getVRegDbgValue ( DIVariable * Var,
DIExpression * Expr,
Register VReg,
bool IsIndirect,
const DebugLoc & DL,
unsigned O )

Creates a VReg SDDbgValue node.

VReg.

Definition at line 11913 of file SelectionDAG.cpp.

References assert(), llvm::cast(), DL, and llvm::SDDbgOperand::fromVReg().

◆ getVScale()

◆ getVTList() [1/5]

SDVTList SelectionDAG::getVTList ( ArrayRef< EVT > VTs)

Definition at line 11311 of file SelectionDAG.cpp.

References llvm::copy(), and llvm::ArrayRef< T >::size().

◆ getVTList() [2/5]

SDVTList SelectionDAG::getVTList ( EVT VT)

Return an SDVTList that represents the list of values specified.

Definition at line 11244 of file SelectionDAG.cpp.

References llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), and makeVTList().

Referenced by AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), llvm::X86TargetLowering::BuildFILD(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), llvm::AArch64TargetLowering::changeStreamingMode(), CloneNodeWithValues(), combineADC(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineADDX(), combineBitcast(), combineBitcastToBoolVector(), combineBVZEXTLOAD(), combineCMov(), combineCMP(), combineSBB(), combineSetCC(), combineStore(), combineSubSetcc(), combineSUBX(), combineSVEPrefetchVecBaseImmOff(), combineTargetShuffle(), CombineVLDDUP(), combineX86AddSub(), combineXorSubCTLZ(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), ConvertCarryFlagToCarryValue(), ConvertCarryValueToCarryFlag(), convertFPToInt(), convertIntToFP(), createLoadLR(), createMemMemNode(), createSetFPEnvNodes(), createStoreLR(), EltsFromConsecutiveLoads(), EmitCmp(), emitCmp(), emitComparison(), emitIntrinsicWithCCAndChain(), EmitMaskedTruncSStore(), emitRepmovs(), emitRepstos(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::RISCVSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTest(), EmitTruncSStore(), EmitUnrolledSetTag(), Expand64BitShift(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandIntMINMAX(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), ExpandREAD_REGISTER(), llvm::TargetLowering::expandREM(), expandV4F32ToV2F64(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), FixupMMXIntrinsicTypes(), foldAndOrOfSETCC(), GeneratePerfectShuffle(), getAArch64XALUOOp(), llvm::MipsTargetLowering::getAddrGPRel(), getAddrSpaceCast(), getAssertAlign(), getAtomic(), getAtomicLoad(), getAVX2GatherNode(), getBasicBlock(), getBlockAddress(), getBoundedStrlen(), getBROADCAST_LOAD(), getCALLSEQ_END(), getCALLSEQ_START(), getConstant(), getConstantFP(), getConstantPool(), getConstantPool(), getCopyFromParts(), getCopyFromReg(), getCopyFromReg(), llvm::RegsForValue::getCopyFromRegs(), getCopyToReg(), getCopyToReg(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExternalSymbol(), getFlagsOfCmpZeroFori1(), getFPBinOp(), getFPTernOp(), getFrameIndex(), getGatherNode(), getGetFPEnv(), getGlobalAddress(), getIndexedStoreVP(), getInvertedVectorForFMA(), getJumpTable(), getLabelNode(), getLifetimeNode(), getLoad(), getLoadFFVP(), getLoadVP(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMachineNode(), getMad64_32(), getMaskedLoad(), getMaskedStore(), getMCSymbol(), getMDNode(), getMergeValues(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getNode(), getPopFromX87Reg(), getPseudoProbeNode(), getRegister(), getRegisterMask(), getScatterNode(), getSetFPEnv(), getSrcValue(), getStore(), getStoreVP(), getStridedLoadVP(), getStridedStoreVP(), getTargetExternalSymbol(), GetTLSADDR(), getTruncStoreVP(), getTruncStridedStoreVP(), getVAArg(), getVCIXISDNodeWCHAIN(), getVectorShuffle(), getX86XALUOOp(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), legalizeSVEGatherPrefetchOffsVec(), LowerABD(), LowerABS(), LowerADDSAT_SUBSAT(), LowerADDSUBO_CARRY(), lowerADDSUBO_CARRY(), LowerATOMIC_STORE(), llvm::VETargetLowering::lowerATOMIC_SWAP(), lowerAtomicArithWithLOCK(), lowerBUILD_VECTORAsBroadCastLoad(), LowerBUILD_VECTORToVIDUP(), lowerBuildVectorAsBroadcast(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerCMP_SWAP(), LowerCTLZ(), LowerCTTZ(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerEH_SJLJ_SETJMP(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), LowerFSINCOS(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMSCATTER(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), lowerOverflowArithmetic(), LowerPARITY(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), llvm::HexagonTargetLowering::LowerREADSTEADYCOUNTER(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerSELECTWithCmpZero(), LowerSETCCCARRY(), lowerShuffleAsBroadcast(), LowerSTORE(), LowerStore(), lowerSTOREVector(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerUADDSUBO_CARRY(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_vXi32(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorExtend(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), mutateStrictFPToFP(), narrowLoadToVZLoad(), PerformADDVecReduce(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), PerformExtractFpToIntStores(), performFlagSettingCombine(), performGatherLoadCombine(), PerformHWLoopCombine(), performLD1Combine(), performMaskedGatherScatterCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), performRNDRCombine(), performScatterStoreCombine(), PerformSETCCCombine(), performSignExtendInRegCombine(), PerformUMLALCombine(), PerformVDUPCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVhrCombine(), reassociateCSELOperandsForCSE(), ReplaceATOMIC_LOAD_128Results(), replaceAtomicSwap128(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), replaceCMP_XCHG_128Results(), ReplaceINTRINSIC_W_CHAIN(), replaceLoadVector(), ReplaceLongIntrinsic(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), ReplaceTcgen05Ld(), SelectionDAG(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), SplitStrictFPVectorOp(), TryCombineBaseUpdate(), tryMemPairCombine(), tryToWidenSetCCOperands(), UnrollVectorOverflowOp(), valueToCarryFlag(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), and widenVectorOpsToi8().

◆ getVTList() [3/5]

SDVTList SelectionDAG::getVTList ( EVT VT1,
EVT VT2 )

Definition at line 11251 of file SelectionDAG.cpp.

References llvm::EVT::getRawBits().

◆ getVTList() [4/5]

SDVTList SelectionDAG::getVTList ( EVT VT1,
EVT VT2,
EVT VT3 )

Definition at line 11269 of file SelectionDAG.cpp.

References llvm::EVT::getRawBits().

◆ getVTList() [5/5]

SDVTList SelectionDAG::getVTList ( EVT VT1,
EVT VT2,
EVT VT3,
EVT VT4 )

Definition at line 11289 of file SelectionDAG.cpp.

References llvm::EVT::getRawBits().

◆ getZeroExtendInReg()

◆ getZExtOrTrunc()

SDValue SelectionDAG::getZExtOrTrunc ( SDValue Op,
const SDLoc & DL,
EVT VT )

Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it.

Definition at line 1503 of file SelectionDAG.cpp.

References llvm::EVT::bitsGT(), DL, getNode(), llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by combineAnd(), combineAndLoadToBZHI(), combineBitcast(), combineBitcastvxi1(), combineCompareEqual(), combineExtractVectorElt(), combineExtractWithShuffle(), combineOr(), combinePredicateReduction(), combineSCALAR_TO_VECTOR(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSetCC(), combineSetCCMOVMSK(), combineShiftAnd1ToBitTest(), combineShuffleOfScalars(), combineToVCPOP(), combineXor(), ConvertCarryFlagToCarryValue(), ConvertCarryValueToCarryFlag(), createPSADBW(), createVariablePermute(), createVPDPBUSD(), earlyExpandDIVFIX(), emitMemMemReg(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), Expand64BitShift(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandVectorFindLastActive(), llvm::TargetLowering::expandVPCTTZElements(), foldAddSubBoolOfMaskedVal(), foldCONCAT_VECTORS(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldSelectOfCTTZOrCTLZ(), getBitcastedZExtOrTrunc(), getExtOrTrunc(), getExtOrTrunc(), getFlagsOfCmpZeroFori1(), getPTest(), getPtrExtOrTrunc(), getShiftAmountOperand(), getTargetVShiftNode(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::TargetLowering::LegalizeSetCCCondCode(), lowerBALLOTIntrinsic(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerCTPOP(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerF64ToF16Safe(), lowerFCMPIntrinsic(), LowerFGETSIGN(), LowerFunnelShift(), lowerICMPIntrinsic(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerLoad(), llvm::SystemZTargetLowering::LowerOperationWrapper(), LowerShift(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowervXi8MulWithUNPCK(), lowerX86CmpEqZeroToCtlzSrl(), performAnyAllCombine(), performBITCASTCombine(), performBitcastCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performRNDRCombine(), performSETCC_BITCASTCombine(), performSETCCCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformUMinFpToSatCombine(), PerformVSetCCToVCTPCombine(), replaceBoolVectorBitcast(), llvm::X86TargetLowering::ReplaceNodeResults(), takeInexpensiveLog2(), TryMatchTrue(), visitORCommutative(), widenAbs(), and widenCtPop().

◆ hasDebugValues()

bool llvm::SelectionDAG::hasDebugValues ( ) const
inline

Return true if there are any SDDbgValue nodes associated with this SelectionDAG.

Definition at line 1989 of file SelectionDAG.h.

◆ haveNoCommonBitsSet()

bool SelectionDAG::haveNoCommonBitsSet ( SDValue A,
SDValue B ) const

Return true if A and B have no common bits set.

As an example, this can allow an 'add' to be transformed into an 'or'.

Definition at line 6278 of file SelectionDAG.cpp.

References A(), assert(), B(), computeKnownBits(), llvm::KnownBits::haveNoCommonBitsSet(), and haveNoCommonBitsSetCommutative().

Referenced by getPointerConstIncrement(), and isADDLike().

◆ InferPtrAlign()

◆ init() [1/2]

void llvm::SelectionDAG::init ( MachineFunction & NewMF,
OptimizationRemarkEmitter & NewORE,
MachineFunctionAnalysisManager & AM,
const TargetLibraryInfo * LibraryInfo,
UniformityInfo * UA,
ProfileSummaryInfo * PSIin,
BlockFrequencyInfo * BFIin,
MachineModuleInfo & MMI,
FunctionVarLocs const * FnVarLocs )
inline

Definition at line 476 of file SelectionDAG.h.

References init().

◆ init() [2/2]

void SelectionDAG::init ( MachineFunction & NewMF,
OptimizationRemarkEmitter & NewORE,
Pass * PassPtr,
const TargetLibraryInfo * LibraryInfo,
UniformityInfo * UA,
ProfileSummaryInfo * PSIin,
BlockFrequencyInfo * BFIin,
MachineModuleInfo & MMI,
FunctionVarLocs const * FnVarLocs )

Prepare this SelectionDAG to process code in the given MachineFunction.

Definition at line 1369 of file SelectionDAG.cpp.

References llvm::TargetSubtargetInfo::getSelectionDAGInfo(), getSubtarget(), and llvm::TargetSubtargetInfo::getTargetLowering().

Referenced by init().

◆ isADDLike()

bool SelectionDAG::isADDLike ( SDValue Op,
bool NoWrap = false ) const

Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::ADD node.

or(x,y) == add(x,y) iff haveNoCommonBitsSet(x,y) xor(x,y) == add(x,y) iff isMinSignedConstant(y) && !NoWrap If NoWrap is true, this will not match ISD::XOR.

Definition at line 5820 of file SelectionDAG.cpp.

References haveNoCommonBitsSet(), llvm::isMinSignedConstant(), llvm::ISD::OR, and llvm::ISD::XOR.

Referenced by isBaseWithConstantOffset().

◆ isBaseWithConstantOffset()

bool SelectionDAG::isBaseWithConstantOffset ( SDValue Op) const

Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD.

This handles the equivalence: X|Cst == X+Cst iff X&Cst = 0.

Definition at line 5830 of file SelectionDAG.cpp.

References llvm::isa(), and isADDLike().

Referenced by getBaseWithConstantOffset(), getBaseWithOffsetUsingSplitOR(), InferPtrAlign(), llvm::SITargetLowering::isReassocProfitable(), LowerAsSplatVectorLoad(), and replaceZeroVectorStore().

◆ isBoolConstant()

◆ isConstantFPBuildVectorOrConstantFP()

bool SelectionDAG::isConstantFPBuildVectorOrConstantFP ( SDValue N) const

Test whether the given value is a constant FP or similar node.

Definition at line 14003 of file SelectionDAG.cpp.

References llvm::isa(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), N, and llvm::ISD::SPLAT_VECTOR.

Referenced by canonicalizeCommutativeBinop(), and isConstantValueOfAnyType().

◆ isConstantIntBuildVectorOrConstantInt()

◆ isConstantValueOfAnyType()

bool llvm::SelectionDAG::isConstantValueOfAnyType ( SDValue N) const
inline
Returns
true if N is any kind of constant or build_vector of constants, int or float. If a vector, it may not necessarily be a splat.

Definition at line 2491 of file SelectionDAG.h.

References isConstantFPBuildVectorOrConstantFP(), isConstantIntBuildVectorOrConstantInt(), and N.

Referenced by llvm::AMDGPUTargetLowering::performSelectCombine(), and simplifySelect().

◆ isEqualTo()

bool SelectionDAG::isEqualTo ( SDValue A,
SDValue B ) const

Test whether two SDValues are known to compare equal.

This is true if they are the same value, or if one is negative zero and the other positive zero.

Definition at line 6212 of file SelectionDAG.cpp.

References A(), B(), and llvm::dyn_cast().

Referenced by combineSelect().

◆ isGuaranteedNotToBePoison() [1/2]

bool llvm::SelectionDAG::isGuaranteedNotToBePoison ( SDValue Op,
const APInt & DemandedElts,
unsigned Depth = 0 ) const
inline

Return true if this function can prove that Op is never poison.

The DemandedElts argument limits the check to the requested vector elements.

Definition at line 2235 of file SelectionDAG.h.

References llvm::Depth, and isGuaranteedNotToBeUndefOrPoison().

◆ isGuaranteedNotToBePoison() [2/2]

bool llvm::SelectionDAG::isGuaranteedNotToBePoison ( SDValue Op,
unsigned Depth = 0 ) const
inline

Return true if this function can prove that Op is never poison.

Definition at line 2229 of file SelectionDAG.h.

References llvm::Depth, and isGuaranteedNotToBeUndefOrPoison().

Referenced by getNode().

◆ isGuaranteedNotToBeUndefOrPoison() [1/2]

◆ isGuaranteedNotToBeUndefOrPoison() [2/2]

bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison ( SDValue Op,
const APInt & DemandedElts,
bool PoisonOnly = false,
unsigned Depth = 0 ) const

Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits.

The DemandedElts argument limits the check to the requested vector elements.

Definition at line 5424 of file SelectionDAG.cpp.

References llvm::ISD::ADD, llvm::all_of(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, canCreateUndefOrPoison(), llvm::cast(), llvm::APInt::clearBit(), llvm::APInt::clearBits(), llvm::ISD::CONDCODE, llvm::ISD::CopyFromReg, llvm::ISD::CTPOP, llvm::Depth, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FrameIndex, llvm::ISD::FREEZE, llvm::APInt::getBitWidth(), llvm::APInt::getOneBitSet(), llvm::getShuffleDemandedElts(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isFixedLengthVector(), isGuaranteedNotToBeUndefOrPoison(), llvm::isIntOrFPConstant(), llvm::APInt::isZero(), MaxRecursionDepth, llvm::ISD::MUL, llvm::ISD::OR, llvm::peekThroughInsertVectorElt(), llvm::ISD::POISON, PoisonOnly, llvm::ISD::SADDSAT, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSHLSAT, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::Sub, llvm::ISD::TargetFrameIndex, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, llvm::APInt::ugt(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UNDEF, llvm::ISD::USHLSAT, llvm::ISD::USUBSAT, llvm::ISD::VALUETYPE, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zext().

◆ isKnownNeverNaN() [1/2]

bool SelectionDAG::isKnownNeverNaN ( SDValue Op,
bool SNaN = false,
unsigned Depth = 0 ) const

Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.

If SNaN is true, returns if Op is known to never be a signaling NaN (it may still be a qNaN).

Definition at line 5835 of file SelectionDAG.cpp.

References llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), and isKnownNeverNaN().

◆ isKnownNeverNaN() [2/2]

bool SelectionDAG::isKnownNeverNaN ( SDValue Op,
const APInt & DemandedElts,
bool SNaN = false,
unsigned Depth = 0 ) const

Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN in DemandedElts.

If SNaN is true, returns if Op is known to never be a signaling NaN (it may still be a qNaN).

Definition at line 5849 of file SelectionDAG.cpp.

References assert(), llvm::ISD::AssertNoFPClass, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::CallingConv::C, llvm::Depth, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::fcNan, llvm::ISD::FCOPYSIGN, llvm::fcSNan, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FP_ROUND, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::APInt::getBitsSet(), llvm::APInt::getOneBitSet(), getTarget(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), I, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isFixedLengthVector(), isKnownNeverNaN(), isKnownNeverSNaN(), llvm::APInt::isZero(), MaxRecursionDepth, Options, llvm::ISD::SELECT, llvm::APInt::shl(), llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::APInt::zext().

Referenced by arebothOperandsNotNan(), combineFMinNumFMaxNum(), combineSelect(), emitFloatCompareMask(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), isKnownNeverNaN(), isKnownNeverNaN(), llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), isKnownNeverSNaN(), isKnownNeverSNaN(), isLegalToCombineMinNumMaxNum(), lowerFMAXIMUM_FMINIMUM(), and LowerFMINIMUM_FMAXIMUM().

◆ isKnownNeverSNaN() [1/2]

bool llvm::SelectionDAG::isKnownNeverSNaN ( SDValue Op,
const APInt & DemandedElts,
unsigned Depth = 0 ) const
inline

◆ isKnownNeverSNaN() [2/2]

bool llvm::SelectionDAG::isKnownNeverSNaN ( SDValue Op,
unsigned Depth = 0 ) const
inline
Returns
true if Op is known to never be a signaling NaN.

Definition at line 2302 of file SelectionDAG.h.

References llvm::Depth, and isKnownNeverNaN().

◆ isKnownNeverZero()

bool SelectionDAG::isKnownNeverZero ( SDValue Op,
unsigned Depth = 0 ) const

◆ isKnownNeverZeroFloat()

bool SelectionDAG::isKnownNeverZeroFloat ( SDValue Op) const

◆ isKnownToBeAPowerOfTwo()

◆ isKnownToBeAPowerOfTwoFP()

bool SelectionDAG::isKnownToBeAPowerOfTwoFP ( SDValue Val,
unsigned Depth = 0 ) const

Test if the given fp value is known to be an integer power-of-2, either positive or negative.

Definition at line 4703 of file SelectionDAG.cpp.

References llvm::Depth, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isConstOrConstSplatFP(), isKnownToBeAPowerOfTwo(), llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.

◆ isSafeToSpeculativelyExecute()

bool llvm::SelectionDAG::isSafeToSpeculativelyExecute ( unsigned Opcode) const
inline

Some opcodes may create immediate undefined behavior when used with some values (integer division-by-zero for example).

Therefore, these operations are not generally safe to move around or change.

Definition at line 2578 of file SelectionDAG.h.

References llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIV, llvm::ISD::UDIVREM, and llvm::ISD::UREM.

Referenced by isSafeToSpeculativelyExecuteNode(), and performBUILD_VECTORCombine().

◆ isSafeToSpeculativelyExecuteNode()

bool llvm::SelectionDAG::isSafeToSpeculativelyExecuteNode ( const SDNode * N) const
inline

Check if the provided node is save to speculatively executed given its current arguments.

So, while udiv the opcode is not safe to speculatively execute, a given udiv node may be if the denominator is known nonzero.

Definition at line 2596 of file SelectionDAG.h.

References isKnownNeverZero(), isSafeToSpeculativelyExecute(), N, and llvm::ISD::UDIV.

Referenced by foldSelectWithIdentityConstant().

◆ isSplatValue() [1/2]

bool SelectionDAG::isSplatValue ( SDValue V,
bool AllowUndefs = false ) const

Test whether V has a splatted value.

Helper wrapper to main isSplatValue function.

Definition at line 3170 of file SelectionDAG.cpp.

References assert(), llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), isSplatValue(), and llvm::EVT::isVector().

◆ isSplatValue() [2/2]

bool SelectionDAG::isSplatValue ( SDValue V,
const APInt & DemandedElts,
APInt & UndefElts,
unsigned Depth = 0 ) const

Test whether V has a splatted value for all the demanded elements.

isSplatValue - Return true if the vector V has the same value across all DemandedElts.

On success UndefElts will indicate the elements that have UNDEF values instead of the splat value, this is only guaranteed to be correct for DemandedElts.

NOTE: The function will return true for a demanded splat of UNDEF values.

For scalable vectors, we don't know the number of lanes at compile time. Instead, we use a 1 bit APInt to represent a conservative value for all lanes; that is, that one bit value is implicitly splatted across all lanes.

Definition at line 2979 of file SelectionDAG.cpp.

References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::cast(), llvm::Depth, llvm::ISD::EXTRACT_SUBVECTOR, llvm::APInt::extractBits(), llvm::APInt::getAllOnes(), llvm::APInt::getBitWidth(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSplat(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), I, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), isSplatValue(), llvm::EVT::isVector(), isZero(), llvm::APInt::isZero(), MaxRecursionDepth, llvm::ISD::OR, llvm::APIntOps::ScaleBitMask(), llvm::APInt::setBit(), llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SUB, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::APInt::zext().

Referenced by canonicalizeShuffleWithOp(), combineConcatVectorOps(), combineShuffleOfSplatVal(), combineX86ShuffleChain(), getSplatSourceVector(), isOnlyUsedByStores(), isSplatValue(), isSplatValue(), LowerRotate(), lowerShuffleAsSplitOrBlend(), lowerVECTOR_SHUFFLE(), llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitVector(), and tryCombineMULLWithUZP1().

◆ isUndef()

◆ Legalize()

void SelectionDAG::Legalize ( )

This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object.

This is the entry point for the file.

Note that this is an involved process that may invalidate pointers into the graph.

Definition at line 6055 of file LegalizeDAG.cpp.

References allnodes_begin(), allnodes_end(), AssignTopologicalOrder(), DeleteNode(), llvm::SmallPtrSetImpl< PtrType >::erase(), getNode(), getRoot(), llvm::SmallPtrSetImpl< PtrType >::insert(), Legalizer, N, and RemoveDeadNodes().

◆ LegalizeOp()

bool SelectionDAG::LegalizeOp ( SDNode * N,
SmallSetVector< SDNode *, 16 > & UpdatedNodes )

Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object.

Returns
true if N is a valid, legal node after calling this.

This essentially runs a single recursive walk of the Legalize process over the given node (and its operands). This can be used to incrementally legalize the DAG. All of the nodes which are directly replaced, potentially including N, are added to the output parameter UpdatedNodes so that the delta to the DAG can be understood by the caller.

When this returns false, N has been legalized in a way that make the pointer passed in no longer valid. It may have even been deleted from the DAG, and so it shouldn't be used further. When this returns true, the N passed in is a legal node, and can be immediately processed as such. This may still have done some work on the DAG, and will still populate UpdatedNodes with any new nodes replacing those originally in the DAG.

Definition at line 6104 of file LegalizeDAG.cpp.

References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallPtrSetImpl< PtrType >::insert(), Legalizer, and N.

◆ LegalizeTypes()

bool SelectionDAG::LegalizeTypes ( )

This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target.

Returns "true" if it made any changes.

Note that this is an involved process that may invalidate pointers into the graph.

Definition at line 1053 of file LegalizeTypes.cpp.

References llvm::DAGTypeLegalizer::run().

◆ LegalizeVectors()

bool SelectionDAG::LegalizeVectors ( )

This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target.

This is necessary as a separate step from Legalize because unrolling a vector operation can introduce illegal types, which requires running LegalizeTypes again.

This returns true if it made any changes; in that case, LegalizeTypes is called again before Legalize.

Note that this is an involved process that may invalidate pointers into the graph.

Definition at line 2409 of file LegalizeVectorOps.cpp.

◆ makeEquivalentMemoryOrdering() [1/2]

SDValue SelectionDAG::makeEquivalentMemoryOrdering ( LoadSDNode * OldLoad,
SDValue NewMemOp )

If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.

This ensures that the new memory node will have the same relative memory dependency position as the old load. Returns the new merged load chain.

Definition at line 12706 of file SelectionDAG.cpp.

References assert(), llvm::SDValue::getNode(), llvm::SDValue::getValue(), llvm::isa(), makeEquivalentMemoryOrdering(), and SDValue().

◆ makeEquivalentMemoryOrdering() [2/2]

SDValue SelectionDAG::makeEquivalentMemoryOrdering ( SDValue OldChain,
SDValue NewMemOpChain )

◆ makeStateFunctionCall()

SDValue SelectionDAG::makeStateFunctionCall ( unsigned LibFunc,
SDValue Ptr,
SDValue InChain,
const SDLoc & DLoc )

Helper used to make a call to a library function that has one argument of pointer type.

Such functions include 'fegetmode', 'fesetenv' and some others, which are used to get or set floating-point state. They have one argument of pointer type, which points to the memory region containing bits of the floating-point state. The value returned by such function is ignored in the created call.

Parameters
LibFuncReference to library function (value of RTLIB::Libcall).
PtrPointer used to save/load state.
InChainIngoing token chain.
Returns
Outgoing chain token.

Definition at line 14151 of file SelectionDAG.cpp.

References assert(), getContext(), getDataLayout(), getExternalSymbol(), llvm::SDValue::getValueType(), llvm::Type::getVoidTy(), Ptr, llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), and llvm::TargetLowering::CallLoweringInfo::setLibCallee().

◆ MaskedValueIsAllOnes()

bool SelectionDAG::MaskedValueIsAllOnes ( SDValue Op,
const APInt & Mask,
unsigned Depth = 0 ) const

Return true if '(Op & Mask) == Mask'.

MaskedValueIsAllOnes - Return true if '(Op & Mask) == Mask'.

Op and Mask are known to be the same type.

Definition at line 2949 of file SelectionDAG.cpp.

References computeKnownBits(), and llvm::Depth.

◆ MaskedValueIsZero() [1/2]

bool SelectionDAG::MaskedValueIsZero ( SDValue V,
const APInt & Mask,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

Return true if 'Op & Mask' is known to be zero in DemandedElts.

MaskedValueIsZero - Return true if 'V & Mask' is known to be zero in DemandedElts.

We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.

We use this predicate to simplify operations downstream. Mask is known to be zero for bits that V cannot have.

Definition at line 2935 of file SelectionDAG.cpp.

References computeKnownBits(), and llvm::Depth.

◆ MaskedValueIsZero() [2/2]

bool SelectionDAG::MaskedValueIsZero ( SDValue V,
const APInt & Mask,
unsigned Depth = 0 ) const

◆ MaskedVectorIsZero()

bool SelectionDAG::MaskedVectorIsZero ( SDValue V,
const APInt & DemandedElts,
unsigned Depth = 0 ) const

Return true if 'Op' is known to be zero in DemandedElts.

MaskedVectorIsZero - Return true if 'Op' is known to be zero in DemandedElts.

We use this predicate to simplify operations downstream.

Definition at line 2943 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::Depth, and llvm::KnownBits::isZero().

Referenced by combineOr(), computeVectorKnownZeroElements(), isTargetShuffleEquivalent(), matchBinaryShuffle(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().

◆ matchBinOpReduction()

SDValue SelectionDAG::matchBinOpReduction ( SDNode * Extract,
ISD::NodeType & BinOp,
ArrayRef< ISD::NodeType > CandidateBinOps,
bool AllowPartials = false )

Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract.

The reduction must use one of the opcodes listed in /p CandidateBinOps and on success /p BinOp will contain the matching opcode. Returns the vector that is being reduced on, or SDValue() if a reduction was not matched. If AllowPartials is set then in the case of a reduction pattern that only matches the first few stages, the extracted subvector of the start of the reduction is returned.

Definition at line 13150 of file SelectionDAG.cpp.

References llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::SDValue::getConstantOperandAPInt(), getContext(), getExtractSubvector(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::isNullConstant(), llvm_unreachable, llvm::Log2_32(), llvm::none_of(), and SDValue().

Referenced by combineArithReduction(), combineBasicSADPattern(), combineMinMaxReduction(), combinePredicateReduction(), combineVPDPBUSDPattern(), and MatchVectorAllEqualTest().

◆ MorphNodeTo()

SDNode * SelectionDAG::MorphNodeTo ( SDNode * N,
unsigned Opc,
SDVTList VTs,
ArrayRef< SDValue > Ops )

This mutates the specified node to have the specified return type, opcode, and operands.

MorphNodeTo - This mutates the specified node to have the specified return type, opcode, and operands.

Note that MorphNodeTo returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one. Note that the SDLoc need not be the same.

Using MorphNodeTo is faster than creating a new node and swapping it in with ReplaceAllUsesWith both because it often avoids allocating a new node, and because it doesn't require CSE recalculation for any of the node's users.

However, note that MorphNodeTo recursively deletes dead nodes from the DAG. As a consequence it isn't appropriate to use from within the DAG combiner or the legalizer which maintain worklists that would need to be updated when deleting things.

Definition at line 11584 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddNodeIDNode(), llvm::dyn_cast(), llvm::SmallPtrSetImplBase::empty(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), N, llvm::SDVTList::NumVTs, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), RemoveDeadNodes(), SDValue(), llvm::Use::set(), and llvm::SDVTList::VTs.

Referenced by CloneNodeWithValues(), llvm::NVPTXTargetLowering::LowerCall(), mutateStrictFPToFP(), and SelectNodeTo().

◆ mutateStrictFPToFP()

SDNode * SelectionDAG::mutateStrictFPToFP ( SDNode * Node)

Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments.

The node must be a strict FP node.

Definition at line 11637 of file SelectionDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), getVTList(), llvm_unreachable, MorphNodeTo(), RemoveDeadNode(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), SDValue(), and llvm::SDNode::setNodeId().

◆ operator=()

SelectionDAG & llvm::SelectionDAG::operator= ( const SelectionDAG & )
delete

References LLVM_ABI, and SelectionDAG().

◆ RemoveDeadNode()

void SelectionDAG::RemoveDeadNode ( SDNode * N)

◆ RemoveDeadNodes() [1/2]

void SelectionDAG::RemoveDeadNodes ( )

This method deletes all unreachable nodes in the SelectionDAG.

RemoveDeadNodes - This method deletes all unreachable nodes in the SelectionDAG.

Definition at line 1023 of file SelectionDAG.cpp.

References allnodes(), getRoot(), llvm::HandleSDNode::getValue(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), RemoveDeadNodes(), and setRoot().

Referenced by Legalize(), MorphNodeTo(), RemoveDeadNode(), and RemoveDeadNodes().

◆ RemoveDeadNodes() [2/2]

void SelectionDAG::RemoveDeadNodes ( SmallVectorImpl< SDNode * > & DeadNodes)

This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.

RemoveDeadNodes - This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.

Definition at line 1043 of file SelectionDAG.cpp.

References llvm::ISD::DELETED_NODE, llvm::SmallVectorTemplateCommon< T, typename >::empty(), I, N, llvm::SelectionDAG::DAGUpdateListener::Next, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::Use::set(), and llvm::SDNode::use_empty().

◆ ReplaceAllUsesOfValuesWith()

void SelectionDAG::ReplaceAllUsesOfValuesWith ( const SDValue * From,
const SDValue * To,
unsigned Num )

Like ReplaceAllUsesOfValueWith, but for multiple values at once.

ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.

This correctly handles the case where there is an overlap between the From values and the To values.

The same value may appear in both the From and To list. The Deleted vector is handled the same way as for ReplaceAllUsesWith.

Definition at line 12525 of file SelectionDAG.cpp.

References copyExtraInfo(), llvm::SDValue::getNode(), llvm::SDValue::getResNo(), llvm::Use::getUser(), ReplaceAllUsesOfValueWith(), llvm::Use::set(), llvm::sort(), transferDbgValues(), Uses, and llvm::SDNode::uses().

◆ ReplaceAllUsesOfValueWith()

void SelectionDAG::ReplaceAllUsesOfValueWith ( SDValue From,
SDValue To )

Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.

ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.

The Deleted vector is handled the same way as for ReplaceAllUsesWith.

Definition at line 12350 of file SelectionDAG.cpp.

References copyExtraInfo(), llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getResNo(), getRoot(), llvm::SDUse::getUser(), llvm::SDNode::isDivergent(), ReplaceAllUsesWith(), llvm::Use::set(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), adjustSubwordCmp(), combineBitcast(), combineCarryDiamond(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineExtractWithShuffle(), combineMOVDQ2Q(), combineOp_VLToVWOp_VL(), combineSelect(), combineSetCCAtomicArith(), combineSIntToFP(), combineTargetShuffle(), combineVSelectToBLENDV(), combineX86INT_TO_FP(), emitIntrinsicWithCCAndChain(), EmitTest(), expandMultipleResultFPLibCall(), lowerBUILD_VECTORAsBroadCastLoad(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), makeEquivalentMemoryOrdering(), mutateStrictFPToFP(), performConcatVectorsCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDivRemCombine(), performExtractVectorEltCombine(), PerformHWLoopCombine(), performIntToFpCombine(), PerformORCombineToSMULWBT(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), performUnpackCombine(), PerformVDUPCombine(), performVectorDeinterleaveCombine(), PerformVMOVhrCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), performVP_REVERSECombine(), reduceANDOfAtomicLoad(), reduceVSXSwap(), ReplaceAllUsesOfValuesWith(), SkipExtensionForVMULL(), tryToFoldExtOfAtomicLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), and widenBuildVec().

◆ ReplaceAllUsesWith() [1/3]

void SelectionDAG::ReplaceAllUsesWith ( SDNode * From,
const SDValue * To )

ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.

This can cause recursive merging of nodes in the DAG.

This version can replace From with any result values. To must match the number and types of values returned by From.

Definition at line 12300 of file SelectionDAG.cpp.

References copyExtraInfo(), getNode(), llvm::SDNode::getNumValues(), getRoot(), llvm::SDUse::getUser(), llvm::SDNode::isDivergent(), ReplaceAllUsesWith(), SDValue(), llvm::Use::set(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

◆ ReplaceAllUsesWith() [2/3]

void SelectionDAG::ReplaceAllUsesWith ( SDNode * From,
SDNode * To )

ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.

This can cause recursive merging of nodes in the DAG.

This version assumes that for each value of From, there is a corresponding value in To in the same position with the same type.

Definition at line 12242 of file SelectionDAG.cpp.

References assert(), copyExtraInfo(), getNode(), llvm::SDNode::getNumValues(), getRoot(), llvm::SDUse::getUser(), llvm::SDNode::getValueType(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::isDivergent(), SDValue(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

◆ ReplaceAllUsesWith() [3/3]

void SelectionDAG::ReplaceAllUsesWith ( SDValue FromN,
SDValue To )

Modify anything using 'From' to use 'To' instead.

ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.

This can cause recursive merging of nodes in the DAG. Use the first version if 'From' is known to have a single result, use the second if you have two nodes with identical results (or if 'To' has a superset of the results of 'From'), use the third otherwise.

These methods all take an optional UpdateListener, which (if not null) is informed about nodes that are deleted and modified due to recursive changes in the dag.

These functions only replace all existing uses. It's possible that as these replacements are being performed, CSE may cause the From node to be given new uses. These new uses of From are left in place, and not automatically transferred to To.

This can cause recursive merging of nodes in the DAG.

This version assumes From has a single result value.

Definition at line 12189 of file SelectionDAG.cpp.

References assert(), copyExtraInfo(), llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getResNo(), getRoot(), llvm::SDUse::getUser(), llvm::SDNode::isDivergent(), llvm::Use::set(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by emitComparison(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerAVXCONCAT_VECTORS(), lowerShufflePairAsUNPCKAndPermute(), mutateStrictFPToFP(), performCONDCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), PerformHWLoopCombine(), PerformLongShiftCombine(), performSETCCCombine(), reassociateCSELOperandsForCSE(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), SelectNodeTo(), tryCombineMULLWithUZP1(), and tryMemPairCombine().

◆ RepositionNode()

void llvm::SelectionDAG::RepositionNode ( allnodes_iterator Position,
SDNode * N )
inline

Move node N in the AllNodes list to be immediately before the given iterator Position.

This may be used to update the topological ordering when the list of nodes is modified.

Definition at line 1970 of file SelectionDAG.h.

References N.

Referenced by insertDAGNode(), and insertDAGNode().

◆ salvageDebugInfo()

◆ SelectNodeTo() [1/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT )

These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands.

SelectNodeTo - These are wrappers around MorphNodeTo that accept a machine opcode.

Note that target opcodes are stored as ~TargetOpcode in the node opcode field. The resultant node is returned.

Definition at line 11477 of file SelectionDAG.cpp.

References getVTList(), N, and SelectNodeTo().

Referenced by SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), SelectNodeTo(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), and tryOrrWithShift().

◆ SelectNodeTo() [2/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT,
ArrayRef< SDValue > Ops )

◆ SelectNodeTo() [3/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT,
SDValue Op1 )

◆ SelectNodeTo() [4/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT,
SDValue Op1,
SDValue Op2 )

◆ SelectNodeTo() [5/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT,
SDValue Op1,
SDValue Op2,
SDValue Op3 )

◆ SelectNodeTo() [6/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT1,
EVT VT2 )

Definition at line 11518 of file SelectionDAG.cpp.

References getVTList(), N, and SelectNodeTo().

◆ SelectNodeTo() [7/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT1,
EVT VT2,
ArrayRef< SDValue > Ops )

◆ SelectNodeTo() [8/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT1,
EVT VT2,
EVT VT3,
ArrayRef< SDValue > Ops )

◆ SelectNodeTo() [9/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
EVT VT1,
EVT VT2,
SDValue Op1,
SDValue Op2 )

◆ SelectNodeTo() [10/10]

SDNode * SelectionDAG::SelectNodeTo ( SDNode * N,
unsigned MachineOpc,
SDVTList VTs,
ArrayRef< SDValue > Ops )

◆ setFlagInserter()

void llvm::SelectionDAG::setFlagInserter ( FlagInserter * FI)
inline

Definition at line 518 of file SelectionDAG.h.

Referenced by llvm::SelectionDAG::FlagInserter::FlagInserter().

◆ setFunctionLoweringInfo()

void llvm::SelectionDAG::setFunctionLoweringInfo ( FunctionLoweringInfo * FuncInfo)
inline

Definition at line 485 of file SelectionDAG.h.

◆ setGraphAttrs()

void SelectionDAG::setGraphAttrs ( const SDNode * N,
const char * Attrs )

Set graph attributes for a node. (eg. "color=red".)

setGraphAttrs - Set graph attributes for a node.

(eg. "color=red".)

Definition at line 191 of file SelectionDAGPrinter.cpp.

References llvm::errs(), and N.

◆ setGraphColor()

void SelectionDAG::setGraphColor ( const SDNode * N,
const char * Color )

Convenience for setting node color attribute.

setGraphColor - Convenience for setting node color attribute.

Definition at line 221 of file SelectionDAGPrinter.cpp.

References llvm::errs(), and N.

◆ setNodeMemRefs()

◆ setRoot()

◆ setSubgraphColor()

void SelectionDAG::setSubgraphColor ( SDNode * N,
const char * Color )

Convenience for setting subgraph color attribute.

setSubgraphColor - Convenience for setting subgraph color attribute.

Definition at line 265 of file SelectionDAGPrinter.cpp.

References llvm::errs(), and N.

◆ shouldOptForSize()

◆ SignBitIsZero()

bool SelectionDAG::SignBitIsZero ( SDValue Op,
unsigned Depth = 0 ) const

Return true if the sign bit of Op is known to be zero.

SignBitIsZero - Return true if the sign bit of Op is known to be zero.

We use this predicate to simplify operations downstream.

Definition at line 2919 of file SelectionDAG.cpp.

References llvm::BitWidth, llvm::Depth, llvm::APInt::getSignMask(), and MaskedValueIsZero().

Referenced by canReduceVMulWidth(), checkSignTestSetCCCombine(), combineUIntToFP(), llvm::TargetLowering::expandABD(), getCmp(), LowerVSETCC(), matchExtFromI32orI32(), and performVectorNonNegToFPCombine().

◆ simplifyFPBinop()

SDValue SelectionDAG::simplifyFPBinop ( unsigned Opcode,
SDValue X,
SDValue Y,
SDNodeFlags Flags )

◆ simplifySelect()

SDValue SelectionDAG::simplifySelect ( SDValue Cond,
SDValue TVal,
SDValue FVal )

Try to simplify a select/vselect into 1 of its operands or a constant.

Definition at line 10773 of file SelectionDAG.cpp.

References llvm::CallingConv::C, Cond, F, isBoolConstant(), isConstantValueOfAnyType(), SDValue(), and T.

Referenced by combineSelect(), and getNode().

◆ simplifyShift()

SDValue SelectionDAG::simplifyShift ( SDValue X,
SDValue Y )

Try to simplify a shift into 1 of its operands or a constant.

Definition at line 10796 of file SelectionDAG.cpp.

References getConstant(), getUNDEF(), llvm::isNullOrNullSplat(), llvm::ISD::matchUnaryPredicate(), SDValue(), X, and Y.

Referenced by getNode().

◆ SplitEVL()

◆ SplitScalar()

◆ SplitVector() [1/2]

std::pair< SDValue, SDValue > llvm::SelectionDAG::SplitVector ( const SDValue & N,
const SDLoc & DL )
inline

Split the vector with EXTRACT_SUBVECTOR and return the low/high part.

Definition at line 2449 of file SelectionDAG.h.

References DL, GetSplitDestVTs(), N, and SplitVector().

◆ SplitVector() [2/2]

◆ SplitVectorOperand()

std::pair< SDValue, SDValue > llvm::SelectionDAG::SplitVectorOperand ( const SDNode * N,
unsigned OpNo )
inline

◆ transferDbgValues()

void SelectionDAG::transferDbgValues ( SDValue From,
SDValue To,
unsigned OffsetInBits = 0,
unsigned SizeInBits = 0,
bool InvalidateDbg = true )

◆ UnrollVectorOp()

◆ UnrollVectorOverflowOp()

◆ updateDivergence()

◆ UpdateNodeOperands() [1/6]

SDNode * SelectionDAG::UpdateNodeOperands ( SDNode * N,
ArrayRef< SDValue > Ops )

◆ UpdateNodeOperands() [2/6]

SDNode * SelectionDAG::UpdateNodeOperands ( SDNode * N,
SDValue Op )

Mutate the specified node in-place to have the specified operands.

UpdateNodeOperands - Mutate the specified node in-place to have the specified operands.

If the resultant node already exists in the DAG, this does not modify the specified node, instead it returns the node that already exists. If the resultant node does not exist in the DAG, the input node is returned. As a degenerate case, if you specify the same input operands as the node already has, the input node is returned.

Definition at line 11337 of file SelectionDAG.cpp.

References assert(), N, and updateDivergence().

Referenced by foldADDIForFasterLocalAccesses(), llvm::SITargetLowering::legalizeTargetIndependentNode(), makeEquivalentMemoryOrdering(), moveBelowOrigChain(), llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine(), UpdateNodeOperands(), UpdateNodeOperands(), and UpdateNodeOperands().

◆ UpdateNodeOperands() [3/6]

SDNode * SelectionDAG::UpdateNodeOperands ( SDNode * N,
SDValue Op1,
SDValue Op2 )

Definition at line 11362 of file SelectionDAG.cpp.

References assert(), N, and updateDivergence().

◆ UpdateNodeOperands() [4/6]

SDNode * SelectionDAG::UpdateNodeOperands ( SDNode * N,
SDValue Op1,
SDValue Op2,
SDValue Op3 )

◆ UpdateNodeOperands() [5/6]

SDNode * SelectionDAG::UpdateNodeOperands ( SDNode * N,
SDValue Op1,
SDValue Op2,
SDValue Op3,
SDValue Op4 )

◆ UpdateNodeOperands() [6/6]

SDNode * SelectionDAG::UpdateNodeOperands ( SDNode * N,
SDValue Op1,
SDValue Op2,
SDValue Op3,
SDValue Op4,
SDValue Op5 )

◆ viewGraph() [1/2]

void SelectionDAG::viewGraph ( )

Definition at line 159 of file SelectionDAGPrinter.cpp.

References viewGraph().

Referenced by viewGraph().

◆ viewGraph() [2/2]

void SelectionDAG::viewGraph ( const std::string & Title)

Pop up a GraphViz/gv window with the DAG rendered using 'dot'.

viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'.

Definition at line 146 of file SelectionDAGPrinter.cpp.

References llvm::errs(), getMachineFunction(), getName(), and llvm::ViewGraph().

◆ WidenVector()

SDValue SelectionDAG::WidenVector ( const SDValue & N,
const SDLoc & DL )

Widen the vector up to the next power of two using INSERT_SUBVECTOR.

Definition at line 13587 of file SelectionDAG.cpp.

References DL, getContext(), getInsertSubvector(), getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), N, and llvm::NextPowerOf2().

◆ willNotOverflowAdd()

bool llvm::SelectionDAG::willNotOverflowAdd ( bool IsSigned,
SDValue N0,
SDValue N1 ) const
inline

Determine if the result of the addition of 2 nodes can never overflow.

Definition at line 2126 of file SelectionDAG.h.

References computeOverflowForAdd(), and OFK_Never.

Referenced by combineAdd(), combineShiftToAVG(), and promoteExtBeforeAdd().

◆ willNotOverflowMul()

bool llvm::SelectionDAG::willNotOverflowMul ( bool IsSigned,
SDValue N0,
SDValue N1 ) const
inline

Determine if the result of the mul of 2 nodes can never overflow.

Definition at line 2166 of file SelectionDAG.h.

References computeOverflowForMul(), and OFK_Never.

◆ willNotOverflowSub()

bool llvm::SelectionDAG::willNotOverflowSub ( bool IsSigned,
SDValue N0,
SDValue N1 ) const
inline

Determine if the result of the sub of 2 nodes can never overflow.

Definition at line 2146 of file SelectionDAG.h.

References computeOverflowForSub(), and OFK_Never.

Referenced by llvm::TargetLowering::expandABD().

◆ DAGUpdateListener

friend struct DAGUpdateListener
friend

DAGUpdateListener is a friend so it can manipulate the listener stack.

Definition at line 402 of file SelectionDAG.h.

References N.

Member Data Documentation

◆ MaxRecursionDepth

◆ NewNodesMustHaveLegalTypes

bool llvm::SelectionDAG::NewNodesMustHaveLegalTypes = false

When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types.

This is important after type legalization since any illegally typed nodes generated after this point will not experience type legalization.

Definition at line 398 of file SelectionDAG.h.

Referenced by combineBinOpOfExtractToReduceTree(), FoldConstantArithmetic(), getConstant(), and getNode().


The documentation for this class was generated from the following files: