Integration issues in RF CMOS
Outline
RF CMOS chips/ SoC
- integration of RF blocks - digital noise and crosstalk - coping with common substrate and GND Packaging techniques - low parasitic packages - multichip modules/ SiP Summary
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J.Dbrowski, Intro to RF Front-End Design
Integration of RF blocks
The high level of integration means that interconnects are short On-chip interconnects still not transmission lines d<< ,
e.g. = v/f =1.5108/5.6109 = 2.7cm and 50 design concepts are mostly used only at the LNA input and PA output.
The substrate loss and coupling mean that layout techniques
such as matching, guard rings, and isolation trenches have to be employed. Cross-chip coupling is a major issue and difficult to simulate, sometimes making it necessary to go through several design iterations. techniques such as zero-IF or low-IF architectures, mean that a wide range of CAD tools must be integrated into a single design environment.
J.Dbrowski, Intro to RF Front-End Design 2
The close integration of digital and analog functions, and
Matching between blocks
LNA
Zout Zin
IQ mixer
It is good to know the input impedance of Mixer when designing LNA. Usually, iterations needed or both circuits are merged Zin of Mixer has strong impact on LNA gain, center frequency, NF and other specs. Zin and Zout usually much larger than 50 Ohm, they jointly should resonate at RF frequency In Mixer most focus on low nonlinear distortions and less on its NF
J.Dbrowski, Intro to RF Front-End Design 3
RF CMOS technology
Transistors are not a limit but passive elements and packaging are
Std. nMOS device
New nMOS device for 45nm process. fmax = 450 GHz
In 0.18-m technology, nMOS can achieve fmax =150 GHz with careful layout optimization. NFmin = 1 dB of the nMOS device at 2.45 GHz
J.Dbrowski, Intro to RF Front-End Design
Complete 802.11a chip in 0.18m CMOS today optimal for integration of RF front-end and digital baseband
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Three classes of RF CMOS processes
Bulk CMOS - Std process as for digital, poor isolation in
substrate, low performance of passives (guard-rings and deeptrench isolation techniques needed) metals, MIM capacitors, and a higher substrate resistivity (more process steps, extra masks) silicon implanted oxide (SIMOX) technology, transistors that are isolated from the substrate
Bulk CMOS with RF technology enhancements extra thick Silicon on Insulator (SOI) - bonded-wafer approach or a thin
J.Dbrowski, Intro to RF Front-End Design
Digital noise and crosstalk
Noise produced by operating circuits
- switching noise in substrate (also crosstalk from LO or Tx) - switching noise in power supply and GND (must be separate for digital and RF) - noise is sensed by reverse-biased junctions, contacts and by body effect Substrate noise and crosstalk can be modeled but difficult
Voltage transient Deep trench hampers some substrate current
Digital GND
Biasing contact
Analog GND
Biasing contact
Current spike
substrate
J.Dbrowski, Intro to RF Front-End Design
Placement and biasing of guard rings
Bulk-source voltage in RF part must be minimized by connecting MOS bulk to local reference GND
Guard for RF blocks Guard provides return path for currents injected to substrate A number of substrate contacts filling spare places on chip
Conductive epoxy for heavily doped substrate shorts substrate currents to external GND using several bondwires
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J.Dbrowski, Intro to RF Front-End Design
Coupling between bondwires
pitch Parallel/series bondwires L=1nH/mm, M=0.5nH/mm if pitch =150m and1mm above the GND plane M If closer to GND plane then M smaller I M
Leff = (L-M)/2 = 0.25nH/mm Leff = (L+M)/2 = 0.75nH/mm for each bondwire
Bond pads implemented preferably in top metal layers to minimize capacitance to substrate
J.Dbrowski, Intro to RF Front-End Design 8
Reducing crosstalk by virtual GND
Differential circuits avoid crosstalk evoked by parasitic impedance to reference GND Virtual GND
Virtual GND
+Vin
M1
M2
-Vin
+Vin
M1
M2
-Vin
VB
Bond wire
VB
Crosstalk and noise by other currents in GND Impedance in common GND
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Crosstalk by inductive coupling
J.Dbrowski, Intro to RF Front-End Design
Signal transfer between blocks
Reference variation is likely due to impedance in common GND
Signal can be transferred together with its reference through a dedicated path to avoid the variations on common GND
J.Dbrowski, Intro to RF Front-End Design 10
Correction of LC tanks
Critical for LNA input matching and gain at RF frequency Critical for VCO to lock at desired LO frequency
Discrete correction (switches + inductors /or capacitors) Continuous correction (varactors)
Vin
Lg Cgs Ls1 Ls2 Ls3
Out
In particular package parasitics can change input matching conditions
Zin
J.Dbrowski, Intro to RF Front-End Design
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RF packaging
Leadless packaging preferred.
Paddle package enables good on-chip GND which is connected through Down-Bonds. The effective GND inductance is smaller compared to leaded packages
J.Dbrowski, Intro to RF Front-End Design
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RF flip chips
Die
avoid bond wires
0.1nH
Interconnect layers
Solder bumps
Substrate
But the chip cannot be probed! Gnd RF Gnd Two styles of interconnects: - Coplanar waveguide (3 solder bumps are needed), more immune to crosstalk. - Microstrip (1 solder bump needed) more common in RF chips Can operate up to 50-60 GHz
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Gnd
RF
J.Dbrowski, Intro to RF Front-End Design
Characterization of package connections
Advantage of Flip-chip
J.Dbrowski, Intro to RF Front-End Design 14
Multichip modules
Multichip modules
MCM-L (laminate) MCM-C (ceramic) MCM-D (deposited)
Multilayer substrate can maintain different passives of enhanced performance Very useful in microwave applications
J.Dbrowski, Intro to RF Front-End Design
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Summary
Integration of RF blocks is a challenge, many
interactions and crosstalk likely Standard CMOS substrates usually avoided for RF Submicron CMOS technology requires design for RF correction /IQ mismatch can be corrected digitally Integration with digital BB even more demanding digital noise must be separated from RF Packaging critical, expensive Multichip modules /SiP/ enable passives with enhanced performance RF chips /SoC/ for research purposes usually bondwired on board directly /cheapest solution
J.Dbrowski, Intro to RF Front-End Design
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