Exception and Interrupt Handling in ARM
Seminar Course: Architectures and Design Methods for Embedded Systems
Author: Ahmed Fathy Abdelrazek (Infotech Master Student) Advisor: Dominik Lcke
1
Contents
Introducing ARM Exceptions Interrupts Interrupt handling schemes Summary
Introducing ARM
Modes of operation
ARM processor has 7 modes of operation.
Switching between modes can be done manually through modifying the mode bits in the CPSR register.
Most application programs execute in user mode Non user modes (called privileged modes) are entered to serve interrupts or exceptions The system mode is special mode for accessing protected resources. It dont use registers used by exception hanlders, so it
cant be corrupted by any exception handler error!!!
3
Introducing ARM
Modes of operation
Processor Mode Description Normal program execution mode Fast data processing mode For general purpose interrupts A protected mode for the operating system When data or instruction fetch is aborted For undefined instructions Privileged mode for OS Tasks User (usr) FIQ (fiq) IRQ (irq) Supervisor (svc) Abort (abt) Undefined (und) System (sys)
Switching between these modes requires saving/loading register values
Introducing ARM
ARM register set
ARM processor has 37 32-bit registers. 31 registers are general purpose registers. 6 registers are control registers Registers are named from R0 to R16 with some registers banked in different modes R13 is the stack pointer SP (Banked) R14 is subroutine link register LR (Banked) R15 is progrm counter PC R16 is current program status register CPSR (Banked)
5
Introducing ARM
ARM register set
More banked registers, so context switching is faster
Contents
Introducing ARM Exceptions Interrupts Interrupt handling schemes Summary
Exceptions
What is an exception?
An exception is any condition that needs to halt normal execution of the instructions
Examples
Resetting ARM core Failure of fetching instructions HWI SWI
8
Exceptions
Exceptions and modes
Each exception causes the ARM core to enter a specific mode.
Exception Fast Interrupt Request Interrupt Request SWI and RESET Pre-fetch or data abort Undefined Instruction Mode FIQ IRQ SVC ABT UND Purpose Fast interrupt handling Normal interrupt handling Protected mode for OS Memory protection handling SW emulation of HW coprocessors
Exceptions
Vector table
It is a table of addresses that the ARM core branches to when an exception is raised and there is always branching instructions that direct the core to the ISR.
At this place in memory, we find a branching instruction
ldr pc, [pc, #_IRQ_handler_offset]
10
Exceptions
Exception priorities
decide which of the currently raised exceptions is more important
Exception Reset
Decide if the exception handler itself can be interrupted during execution or not?
Priority 1 2 3 4 5 6 6
I bit 1 1 1 1 1 1 1
F bit 1 1 -
Both are caused by an instruction entering the execution stage of the ARM instruction pipeline
Data Abort FIQ IRQ Prefetch abort SWI Undefined instruction
11
Exceptions
Link Register Offset
This register is used to return the PC to the appropriate place in the interrupted task since this is not always the old PC value.It is modified depending on the type of exception.
The PC has advanced beyond the instruction causing the exception. Upon exit of the prefetch abort exception handler, software must re-load the PC back one instruction from the PC saved at the time of the exception.
Exception
Reset Data Abort FIQ, IRQ, prefetch Abort SWI, Undefined Instruction
Returning Address
None LR-8 LR-4 LR
12
Exceptions
Entering exception handler
1. Save the address of the next instruction in the appropriate Link Register LR. 2. Copy CPSR to the SPSR of new mode. 3. Change the mode by modifying bits in CPSR. 4. Fetch next instruction from the vector table.
Leaving exception handler
1. Move the Link Register LR (minus an offset) to the PC. 2. Copy SPSR back to CPSR, this will automatically changes the mode back to the previous one. 3. Clear the interrupt disable flags (if they were set).
13
Contents
Introducing ARM Exceptions Interrupts Interrupt handling schemes Summary
14
Interrupts
Assigning interrupts
It is up to the system designer who can decide which HW peripheral can produce which interrupt. But system designers have adopted a standard design for assigning interrupts:
SWI are used to call privileged OS routines. IRQ are assigned to general purpose interrupts like periodic timers. FIQ is reserved for one single interrupt source that requires fast response time.
15
Interrupts
Interrupt latency
It is the interval of time from an external interrupt signal being raised to the first fetch of an instruction of the ISR of the raised interrupt signal. System architects try to achieve two main goals:
To handle multiple interrupts simultaneously.
To minimize the interrupt latency.
And this can be done by 2 methods:
allow nested interrupt handling give priorities to different interrupt sources
16
Interrupts
Enabling and disabling Interrupt
This is done by modifying the CPSR, this is done using only 3 ARM instruction: MRS To read CPSR MSR To store in CPSR BIC Bit clear instruction ORR OR instruction
Enabling an IRQ/FIQ Interrupt:
MRS BIC MSR r1, cpsr r1, r1, #0x80/0x40 cpsr_c, r1
Disabling an IRQ/FIQ Interrupt:
MRS ORR MSR r1, cpsr r1, r1, #0x80/0x40 cpsr_c, r1
17
Interrupts
Interrupt stack
Stacks are needed extensively for context switching between different modes when interrupts are raised. The design of the exception stack depends on two factors: OS Requirements. Target hardware. A good stack design tries to avoid stack overflow because it cause instability in embedded systems.
18
Interrupts
Interrupt stack
Two design decisions need to be made for the stacks: The location The size
User stack Interrupt stack User stack Heap
Heap
Traditional memory layout
Code Code
Interrupt stack Vector Table Vector Table
The benefit of this layout is that the vector table remains untouched if a stack overflow occured!!
19
Contents
Introducing ARM Exceptions Interrupts Interrupt handling schemes Summary
20
Interrupt handling schemes
Non-nested interrupt handling scheme
Interrupt
This is the simplest interrupt handler. Interrupts are disabled until control is returned back to the interrupted task.
One interrupt can be served at a time. Not suitable for complex embedded systems.
Disable interrupts Save context Interrupt handler ISR Restore context
Return to task
Enable interrupts
21
Interrupt handling schemes
Nested interrupt handling scheme(1)
Interrupt
Handling more than one interrupt at a time is possible by enabling interrupts before fully serving the current interrupt.
Latency is improved. System is more complex.
Disable interrupts Save context Interrupt handler ISR
No difference between interrupts by priorities, so normal interrupts can block critical interrupts.
Enable interrupts somewhere here
Restore context
Return to task
22
Interrupt handling schemes
Nested interrupt handling scheme(2)
Not complete Handler
The handler tests a flag that is updated by the ISR Re enabling interrupts requires switching out of current interrupt mode to either SVC or system mode. Context switch involves emptying the IRQ stack into reserved blocks of memory on SVC stack called stack frames.
Prepare stack. Switch mode. Construct a frame. Enable interrupts.
Interrupt Complete serving interrupt
Interrupt
23
Interrupt handling schemes
Prioritized simple interrupt handling
associate a priority level with a particular interrupt source. Handling prioritization can be done by means of software or hardware. When an interrupt signal is raised, a fixed amount of comparisons is done. So the interrupt latency is deterministic. But this could be considered a disadvantage!!
24
Interrupt handling schemes
Other schemes
Re-entrant interrupt handler: re-enable interrupts earlier
There are some other schemes, which are actually modifications to the previous schemes as follows: and support priorities, so the latency is reduced.
Prioritized standard interrupt handler: arranges priorities in
a special way to reduce the time needed to decide on which interrupt will be handled.
Prioritized grouped interrupt handler: groups some
interrupts into subset which has a priority level, this is good for large amount of interrupt sources.
25
Contents
Introducing ARM Exceptions Interrupts Interrupt handling schemes Summary
26
Summary
Availability of different modes of operation in ARM helps in exception handling in a structured way. Context switching is one of the main issues affecting interrupt latency, and this is resolved in ARM FIQ mode by increasing number of banked registers. We cant decide on one interrupt handling scheme to be used as a standard in all systems, it depends on the nature of the system:
What type of interrupts are there? How many interrupts are there?
27
Thanks For listening, Waiting for questions
28
