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You are here: Home Programming VHDL Code for Half Adder and Half Subtractor January 10, 2014 11:02 am
VHDL Code for Half Adder and Half Subtractor
Posted by Coding Talks on July 27, 2012
VHDL Code for Half Adder and Half Subtractor
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library ieee; use ieee.std_logic_1164.all; entity bejoy_ha is port (a,b : in bit ; s,c : out bit); end bejoy_ha; architecture arc of bejoy_ha is begin s<= a xor b; c <= a and b;
VHDL Code for Half Subtractor :
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library ieee; use ieee.std_logic_1164.all; entity bejoy_hs is port (x,y,en : in bit ; d,b : out bit; y1: inout bit); end bejoy_hs; architecture arc of bejoy_hs is begin process (en,y1) begin if en='1' then d<= x xor y; y1<= not (y); b <= x and y1; end if; end process; end arc;
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Filed in: Programming, VHDL Tags: code, Half Adder, Half Subtractor, tutorial, vhdl
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