TWO AND ONE STAGES OTA
F. Maloberti
Department of Electronics
Integrated Microsystem Group
University of Pavia, 27100 Pavia, Italy
[email protected]
tel. +39-382-505205; fax. +39-0382-505677
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FUNDAMENTAL OF OPERATIONAL AMPLIFIER
The ideal operational amplifier is a voltage controlled voltage source
with infinite gain, infinite input impedance and zero output impedance.
+
_
A(v+ - v )
In all applications the op-amp is used in feedback configuration.
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The feedback configuration:
Z2
V1
V2
Z1
V0
Z3
+
Z4
V0
Z4 Z1 + Z2
Z2
= V 2 --------------------- --------------------- V 1 ------Z3 + Z4 Z1
Z1
If the gain of the op-amp is not infinite, an error of the order of 1/A
results. This error must be smaller or comparable to the
impedance matching.
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If impedances are implemented with capacitors and switches, it
result that, after a transient, the load of the op-amp is made of
pure capacitors. Their voltage can be obtained with stages having
high output resistance (transconductance operational amplifier).
C
_
- Q (t)
+
g
+
Q
v 0 ( 0 ) = ------C0
v
m i
r
0
C0
+
1
1
v i ( 0 ) = Q ------- + ----
C0 C
Q
V i ( t ) = V 0 ( t ) ---C
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g m
v 0()
Q
v 0 ( ) ---- = --------------C
r0
gmr 0
Q
v 0 ( ) = ---- -----------------------C 1 + gmr 0
---The output resistance must be high in order to have v 0 ( ) Q
C
Q
+
C
g
r
0
v
m i
v 0(t ) = v o (0 ) + [v 0() v 0(0 )][1 e
C0
v 0 (t)
C
------gm
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PERFORMANCE CHARATCTERISTICS
Actual op-amps deviate from ideal behavior. The differences are described by the performance characteristics.
DC differential gain:
is the open loop voltage gain measured at DC with a small differential
input signal. Typically Ad = 80 - 100 dB
vout
vi n
+
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Common mode gain:
is the open loop voltage gain with a small signal applied to both the
input terminals. Acm = 20 - 40 dB.
vout
v
in
Common mode rejection ratio:
is defined as the ratio between the differential gain and the common
mode gain. Typically CMRR = 40 - 80 dB
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Power supply rejection ratio:
if a small signal is applied in series with the positive or negative power
supply, it is transferred to the output with a given gain Aps+ (or Aps-).
The ratios between differential gain and power supply gains furnish
the two PSRRs.
vo=A ps vps
+
vps
Typically:
PSRR = 90 dB (DC)
PSRR = 60 dB (1KHZ)
PSRR = 30 dB (100 KHZ)
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Input offset voltage:
in real circuits if the two input terminals are set at the same voltage the
output saturates close to VDD or to VSS.
vos
Offset compensates the effect.
Typically |Vos| = 5 - 15 mV
vout
+
Input common mode range:
it is the maximum range of the common mode input voltage which do
not produce a significant variation of the differential gain.
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Output voltage swing:
is the swing of the output node without generating a defined amount
of harmonic distortion.
Equivalent input noise:
The noise performances can be described in terms of an equivalent
voltage source at the input of the op-amp.
Typically Vn = 40 - 50 nV/ Hz at 1 kHz;
in a wide band (1MHz) it results 10 - 50 V RMS
2
vn
[dB]
+
|vn|
vout
log(f)
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Unity-gain bandwidth (ft):
is the frequency at which the open
loop gain is zero. It is also the -3 dB
bandwidth for unity-gain closed loop
conditions. Typically ft = 20 MHz
|A 0|
[dB]
+
vout
fT
log(f)
Slew rate:
it is the maximum slope of the output voltage for a steply signal applied at the
input. Usually measured with the op-amp in the buffer configuration. The positive slew rate can be different from the negative slew rate, depending on the
specific design. Typically 5-20 V/sec. For micropower operations they drops
to much lower levels.
v
out
vout
slope
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Settling time:
if the phase margin is not good enough the response to an input step
can be affected by some ringing. The settling time is the time required
to settle the output within a given range (usually 0.1%) of the final
value.
Power dissipation:
it depends on the request of speed and bandwidth of the circuit. Typically, for 5 V supply, is around 1 mW. For lower supply the power consumption doesnt scale proportionally
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Technology
0.8 m CMOS
Supply voltage
3.3 V
DC gain
80 dB
gain-bandwidth
20 MHz
Slew rate
5 V/sec
Settling time 1V, Cl=4pf
400 n sec
CMRR
40 dB
PSRR, DC
90 dB
PSRR, 1 kHz
60 dB
PSRR, 100 kHz
30 dB
Offset
6 mV
Input common range
2V
Output swing
2.5 V
Input referred noise
100 nV/Hz at 1 kHz
Power dissipation
1 mW
Area
100 x 100 m
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Differ.
Gain
Differ.
S. End.
2nd gain
Stage
Output
Stage
Basic Op-Amp Internal Functions
Key requirement:
Need absolute stability in unity gain closed loop conditions when
driving maximum load.
Use minimum number of gain stages.
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Two stages op-amp (transconductance)
M7
MB
I Ref
M1
M2
M6
C c Out
M5
M3
M4
Key design issue:
Open loop DC gain
DC offset
PSRR
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Open loop DC gain:
W W
W
W
--------K
---------K
g m1
g m5
L1 L5
L1 L5
A v = A 1 A 2 = ------------------------------- ------------------------------- --------------------------------- = -------------------------------------g ds2 + g ds4 g ds5 + g ds6
I7 I6
W W
I Ref ------ -----L7 L6
DC offset:
The input offset is composed of two terms:
Systematic offset
Random offset
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Systematic offset:
It is assumed that the device are perfectly matched.
The systematic offset can be reduced to zero with a careful design.
For zero input differential signal the scheme is equivalent to:
MB
I Ref
1/2 M7
M6
Out
M1
M5
M3
The transistors M6 and M7 must operate is saturation. Hence:
( W L )3
1 ( W L )7
--------------------- = --- --------------------2 ( W L )6
( W L )5
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Random offset:
Due to the geometrical mismatching and process dependent
inaccuracies.
-A 1
vos1
-A 2
vos2
v os
v os2
= v os1 ----------- v os1
A1
Dominated by the offset of the input stage
Higher than bipolar counterpart
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For zero input signal, the output is:
R2
R1
I
V = I 1 R 2 I 2 R 2 = --- R
2
V is neutralized with an input offset voltage such that:
gm1R 0 v 0s = V
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1 I R
v 0s = --- ---------- -------2 g m1 R 0
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Bipolar:
I
------- 26mV
gm
Mosfet:
V GS V T h
I
------- = ----------------------------- 150 300mV
2
gm
Assuming:
R
----------- = 0.01
2R 0
it results:
v os, bip = 0.26mV
v os, MOS = 1.5 3mV
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Power supply rejection:
vn+
V
DD
M7
MB
I Ref
M1
M3
C c Out
M2
4
3
vn-
M6
M5
M4
DD
A signal on the positive bias line determines a modulation in the reference
current, which, in turn, gives an equal modulation of the currents in M5 and
M6 if the condition of the zero systematic offset is fulfilled.
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A signal on the negative bias line is divided by the network made
by M7, M1, M3. The signal on node 4 (by symmetry equal to the
one on 3) is given by:
vv 4 = v - ------------------------------------------------------1 + g m1 g m3 r ds1 r ds7
v gs5 = v - v 4
v - A2
v 0 = v gs5 A 2 = -------------------------------------------g m1 g m3 r ds1 r ds7
The DC PSRR is usually larger than the DC gain.
At high frequency the PSRR is determined only in the second
stage
The impedance of the compensation capacitances Cc decreases,
resulting an effective shorting of gate to drain of M5.
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n
VDD
rds6
v-n
M5
It results:
v out
1 g m5
= -------------------------------------------+
+
r
1
g
m5
ds6
vn
r ds6
v out
= ------------------------------------ 1
---------1 g m5 + r ds6
vn
The negative supply PSRR is approximately 0 dB at the unity gain
frequency of the op-amp.
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Coupling through the virtual ground
Gives an high frequency
contribution to the PSRR when the
op-amp is used as integrator.
Due to the capacitive coupling
between power supply lines and
the input led.
+
v 0 = [ v n V n ]
VDD
C+
CI
vout
C-
VSS
Put input transistors in well attached to source. The body effect,
which changes VTh, hence VGS, is eliminated.
Careful layout: no crossover, shielding.
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FREQUENCY RESPONSE AND COMPENSATION
A two gain stages scheme with poles in the same frequency range
needs compensation.
A single pole system is always stable.
Strategy: approach single pole performance by splitting the two
poles apart.
P1
Cc
I1
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P2
I2
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Miller capacitance moves p1 at lower frequency.
Shunt feedback moves p2 ar higher frequency
Small signal equivalent circuit for two stages operational amplifier.
v
R
g v
m1 in
Cc
C
1
R2
g
C2
v
m2 1
v 1 ( g 1 + sC 1 ) + ( v 1 v 0 ) sC c + g m1 v in = 0
v 0 ( g 2 + sC 2 ) + ( v 0 v 1 ) sC c + g m2 v 1 = 0
sC
1 ----------cg m2
V0
--------- = g m1 R 1 g m2 R 2 ----------------------------------------------------------------------------------------------------------------------------------------2
V in
1 + sR 1 R 2 g m2 C c + S R 1 R 2 [ C 1 C 2 + ( C 1 + C 2 ) C c
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The circuit displays two poles and a zero in the right half plane.
1
p 1 ---------------------------------g m2 R 2 R 1 C c
g m2 C c
p 2 --------------------------------------------------------C 1C 2 + (C 1 + C 2)C c
g m2
z = + ---------Cc
since in practice Cc > C1; Cc C2 and gm1 > 1/R1; gm2 > 1/R2 it results:
1
p 1 --------------R 1C 1
g m2
1
p 2 ---------- --------------C 2 R 2C 2
Assuming p1 as dominant, the unity gain angular frequency wT is:
g m1
1
T = p 1 A 0 = ---------------------------------- g m1 g m2 R 1 R 2 = ---------Cc
g m2 R 2 R 1 C c
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The locations of the second pole p2 and of the zero with respect to wT
are derived by considering:
g m2 C c
p2
=
---------- ------- for stability > 2 to 4;
------g m1 C 2
T
m2
z = g
---------------g m1
T
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if Cc > C2 and gm2 > gm1
|A|
[dB]
log(f)
with left half-plane zero
log(f)
-90
-180
-270
The right half-plane worsen the phase margin.
In bipolar technology gm2 >> gm1 because the current in the
second stage is normally higher than the one in the first stage.
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In CMOS technology because is proportional to the square root of
I; moreover, the transconductance of the input pair must be high
in order to reduce their thermal noise contribution.
In real situations the obtainable phase margin does not guarantee
the stability.
Eliminating right half-plane zero:
Source follower
Zero nulling resistor
The zero is due to a signal feedforward
to a point that is 180 out of phase
I2
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Solution: eliminate feedforward with a source follower
I2
I2
Disadvantages:
Area
Power dissipation
Actually creates a doublet in the feedback path. Potentially not stable.
Alternative, a substrate emitter follower may be used. (The bipolar
transistor is smaller and has higher gm)
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Zero nulling resistor:
Zeros position is pushed away with a resistance in series with Cc
1
R z Cc
It results:
V 0 A 0 [ 1 + s ( R z 1 g m2 ) C c ]
--------- ----------------------------------------------------------------------V in
s
s
1 + ----1
+ ------
p 1
p 2
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The pole locations are closed to the original
The zero is moved depending on Rz
1
z = ------------------------------------1
C c ---------- R z
g m2
If Rz = 1/gm2 the zero is moved at the infinite
If Rz = 1/gm2 the zero is located in the left half-plane
Implementation:
V
DD
V0
V1
1
1
g m2 = ------- + ------Rn Rp
VS S
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In non saturation:
W
1
------- = k ' n ------ [ V DD V 1 V Th, n ]
L n
Rn
W
1
------- = k ' p ------ [ V 1 V ss V Th, p ]
L p
Rp
W
------ and ------ such that:
Choose W
W
W
k ' n ------ = k ' p ------
L n
L p
and:
W
g m2 = k n ------ [ V DD V SS V T h, n V T h, p ]
L n
Problem: Supply sensitivity.
Since the swing of the node 1 is A2 less than the output swing, only
one transistor with supply independent bias can be used.
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SLEW RATE
M4
M3
M5
M1
M2
Cc
IB2
IB1
CL
(CL includes the feedback capacitor)
For large input signal:
M1, M4 are off so the current IB1 charges Cc through M2. Assuming
M5 able to drive the current request by Cc, CL and IB2
SR +
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V
= ----------+t
max
IB1
= -------Cc
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M2, M5 are off so the current IB1 mirrored by M4 discharges Cc;
CL is discharged by IB2
V
SR - = ----------t
max
IB2
= ---------------------Cc + CL
In order to have SR+ = SR- it must be:
IB1
IB2
-------- = ---------------------Cc
Cc + CL
Since
g m1
= ---------- ,
Cc
it results
IB1
SR = ---------- T = ( V GS 1 V Th ) T
g m1
For
T = 2 5 10
, (VGS - VTh) = 600 mV, SR 10 V/sec.
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SINGLE STAGE SCHEMES
High gain is get with a cascode scheme.
Telescopic cascode
Mirrored cascode
Folded cascode
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Telescopic cascode:
J DC gain (gmrds)2
J Low power consumption
J Only one high impedance node:
compensated with a capacitance load
(if necessary)
L Low output swing
L Reference of the input close to the
negative supply
L Two bus lines (VB1, VB2)
B1
M7
M8
M5
M6
M3
+
VB2
M1
M4
M2
M9
L 5 Transistors in series
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Mirrored cascode:
M10
J Optimum input common mode
range
J Only 4 transistors in series
M12
M2
M1
VB1
M13
J Improved output swing
L Speed of the mirror
L Higher power consumption
M11
M3
M4
M5
M6
M7
M8
Out
B2
M9
V outmax = V B 1max + V GS 4 V sat
V B 1max = V DD V sat V GS 4
V outmax = V DD 2V sat
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V outmax = V GS 7 + V sat
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Conventional Folded cascode:
M10
M11
VB3
_
M2
M1
M3
B2
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M9
M4
M5
M6
M7
M8
VB1
Out
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Modified Folded cascode:
M10
M11
VB3
_
+
M2
M1
VB1
M4
M3
M5
MA
M6
Out
B2
M9
M8
M7
MB
Modified in order to improve the going down output swing
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TWO STAGES AMPLIFIER VS SINGLE STAGE
AMPLIFIER
Two stages:
J Voltage gain less affected by resistive loading
J Maximum signal swing
J Less bussing of bias lines
L Requires additional capacitor for frequency compensation
L More power consumption
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Single stage:
J No need for additional compensation capacitor
J Lower power consumption
J Better CMRR
L Lower signal swing
L More bussing of bias lines
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CLASS AB AMPLIFIER
Class AB: a circuit which can have an output current which is larger
than its DC quiescent current.
Two stages amplifier with class AB second stage
M6 and M7 act as a level
shifter
M8 and M9 act as a class AB
push-pull amplifier
M4
M3
M8
M6
M1
M2
M9
g m8 + g m9
A 2 = ------------------------------g ds8 + g ds9
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VB
M5
M7
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The quiescent current in the output stage is bias voltage and technological
variation dependent.
V DD = V GS 8 + V GS 6 + V GS 9
neglecting the body effect:
2 L
2 L
2 L
V DD = V T h, p + 2V T h, n + ------- ------ I 6 + ------- ------ I + ------- ------ I
k 'n W 6
k 'p W 8
k 'n W 9
2 L
V DD V T h, p 2V T h, n ------- ------ I 6
k 'n W 6
I = --------------------------------------------------------------------------------------------------2 L
2 L
------- ------ + ------- ------
k 'p W 8
k 'n W 9
Typically with VDD = 5V the numerator is around 1.6 V; if it is assumed VDD
= (5 0.5)V and DVTh = 200 mV, it results that the numerator can change
from 0.7 V to 2.5 V; hence, Imin = 0.3 Inom; Imax = 2.5 Inom
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Single stage class AB amplifier (only inverting)
The input pair M1 and M2
operate source followers
and it drives the common
gate stages M3 and M4
M5
M6
VB
V B = V Th, n + V Th, p + V ov, n + V ov, p
I 1 = I 2 = I Bias
for Vin > 0 I1
M7
M2 M3
for Vin = 0
M1 M4
and I2
I out = K 8, 9 I 1 K 5, 6 I 2
IB
VB
VB
M10
VB
M8
M9
IB
K8,9 and K5,6 mirror factors (assumed equal)
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2 W
2 W
V B + V in = V GS 2 + V GS 4 = V T h, n + V T h, p + ------- ------ + ------- ------ I 2
k ' p L 4
k 'n L 2
V B V in = V GS 1 + V GS 3
2 W
2 W
= V T h, n + V T h, p + ------- ------ + ------- ------ I 1
k ' p L 1
k 'n L 3
It results:
I out = K 8, 9 ( I 1 I 2 ) = K 8, 9 V B V in
Iout
until I1 or I2 goes to zero, for a larger
Vin, Iout increases quadratically with
Vin
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Vin
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Small signal gain:
A v = 2G m r out
Gm is the transconductance of the cross coupled input stage
In
M2
gm2 (vin - vA )
A
M4
-gm4 v
A
g m2 ( V in V A ) = g m4 V A
VA
I out = g m4 V A
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g m2 V in
= ---------------------------g m2 + g m4
g m2 g m4
= ---------------------------- V in = G m V in
g m2 + g m4
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FULLY DIFFERENTIAL SCHEMES
The use of fully differential paths through analog signal processor
gives benefits on:
PSRR
Dynamic range
Clock feedthrough cancellation
Consider an integrator and its fully differential version
C
in R
in+ R
+
out
in - R
+ - +
out -
out
C
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J Noise from the power supply and clock feedthrough are common
mode signal.
J The output swing is (Vmax+ - Vmax- = 2Vmax) doubled. Since the
noise is unchanged, the dynamic range improves by 6 dB.
L Single ended to differential and double ended to single ended
converters are necessary
L Larger area
L More bussing of bias lines
L Common mode feedback is necessary
SE/DE
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Different.
Processor
DE/SE
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The blocks SE/DE and DE/SE increase the complexity and introduce
noise. Differential approach is convenient if the differential processor
contains more than 4 stages.
C
in R
in+ R
+
out
in - R
+ - +
out
out
The feedback around the op-amp control the difference of the input
terminal voltages and not their mean value. In turn, there is no control
on the output common mode voltage.
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M10
M11
VB3
_
M2
M1
M3
Out-
M5
B2
M9
M7
VB1
M4
Out+
M6
VB4
M8
VB5
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B2
CMFB
or VB3 or VB5
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COMMON MODE FEEDBACK
Continuous time
Sampled data
Continuous time feedback:
I out
V
M3
V+
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M1
M2
V-
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VB is such that M1 and M2 are in the linear region; (W/L)1 = (W/L)2
M1 and M2 are like the parallel of two voltage dependent resistance
2
1 W
I 1 = --- k ' ------ [ 2 ( V + V Th ) V DS V DS ]
L 1
2
2
1 W
I 2 = --- k ' ------ [ 2 ( V - V Th ) V DS V DS ]
L 1
2
2
1 W
I out = I 1 + I 2 = --- k ' ------ [ V B V DS V Th ]
L 3
2
With a differential signal Iout = cost
With a common mode signal:
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for positive, Iout increase
for negative, Iout decrease
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FULLY DIFFERENTIAL FOLDED CASCODE WITH CMFB
M9
VB1
M10
_
+
M1
M2
M3
V B2
V
V
B3
M5
B3
M7
V B5
VCM
M4
Out -
M11
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Out +
M6
M8
M12
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M9
VB1
+
V B2
Out
M10
_
M1
M2
M3
M4
V B3
V B4
V B5
M6
M5
M8
M7
M11
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Out +
M12
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Problems:
Dynamic range
Linearity
Compensation of the non linearities of the n-channel and p-channel
CMFB cell.
V+
out
I
I
V-
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Simple data feedback:
The common mode feedback operates on slowly variable signal. It can
be implemented at discrete time interval.
The sampled data feedback is essential for low bias voltage and low
power.
J Lineartity (mean value
with capacitors)
V+
I Ref
1
J Low power consumption
J No limitation to the
dynamic range
L Clock phases necessary
L Clock feedthrough effect
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VI Out
2
C
C'
2
1
2
1
2
C
VCM
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MICROPOWER OP-AMPS
Required in battery operated system (pocket calculators, pace makers,
hearing aids, electronic telephone, ...)
Consumption < 1 A
Use of MOS transistors in weak inversion (subthreshold)
Low current has, as consequence, low slew rate.
C
M5
1
M3
M1
M4
M6
M2
B/C
M7
M8
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AMPLIFIER WITH ADAPTIVE BIAS
M3
M4
M6
M5
M1
D(I 2-I 1)
D(I 1-I 2)
M2
M7
1
M8
I
Basic idea:
Generate |I1 - I2| and increase the current in the differential stage by
D|I1 - I2|.
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I 0
= ----------------1 D
Since |I1 - I2| = [I0 +D |I1 - I2|]:
I1 I2
For transistors in weak inversion
vi
------------- = tanh
2nv T
The increase of the current in the differential stages becomes significant around:
vi
D tanh -------------- = 1
2nv T
Typical performances
DC gain
ft
SR
I0
Itot
95 dB
130 kHz
0.1 V/ sec
0.5 A
2.5 A
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CLASS AB SINGLE STAGE WITH DYNAMIC BIASING
M7
M8
Bias3
In+
Bias1
M2
M3
In-
Out+
OutM1
M4
Bias4
Bias2
M5
M6
In order to have a maximum output swing the bias voltages BIAS1 BIAS2 must be kept as close as possible to the bias voltages
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During the slewing the current source of the output cascodes can be
pushed in the linear region, hence loosing the advantage of the AB
operation.
The problem is solved with the dynamic biasing
M7 M8
M2 M3
OutM1 M4
Bias2
M5 M6
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NOISE
The noise of an operational amplifier is described with an input
referred voltage source Vn.
The spectrum of Vn is made of a white term and 1/f term.
Vn is due to the contributions, referred to the input, of the noise
generators associated to all the transistors of the circuit (assumed
uncorrelated).
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consider the input stage of a two stages op-amp.
vn3
vn4
M3
M4
v n1
vn2
M2
M1
M5
The output noise voltage is given by:
2
1
2
2
2
2
2
2
2
V n, out = [ ( V n1 + V n2 ) g m1 + ( V n3 + V n4 ) g m3 ] -------------------------------
g ds2 + g ds4
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Where it is assume gm1 = gm2; gm3 = gm4 (it is assumed that the noise
source of M5 does not contribute) moreover since usually W1 =W2;
L1 = L2; W3 =W4; L3 =L4; V2n1 = V2n2; V2n3 = V2n4;
if we refer Vn,out to the input, we get:
2
g m3 2 2
V nout
V n, out
2
2
2
-------------- = V n, in = ---------------- ( g ds2 + g ds4 ) = 2 V n1 + ---------- V n3
2
2
g m1
A1
g m1
The contribution of the active loads is reduced by the square of
the ratio gm3/gm1
It is worth to remember that
gm =
2
Vn
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W
2C ox ------ I
L
KF
8 kT
1
--------- f
= --- ------- + -------------------2 WL
3
g
m 2C ox
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The attenuation by the factor (gm3/gm1)2 gives, for the white term:
2
V n, in,
2
2V n1 1
3 I 3 W L 3
g m3
2
+ ---------- = 2V n1 1 + ----------------------------
1 I 1 W L 1
g m1
and for the 1/f term:
2
V n, in, 1 f
KF1
K F 3 I 3 L 1
= ------------------------------------ 1 + -----------------------
2
2
1 C ox W 1 L 1
K F 1 I 1 L 3
Where KF1 and KF2 are the flicker noise coefficient of the type of transistor of
which M1 and M3 are made.
The white contribution of the active load is reduced by choosing (W/L)input >>
(W/L)load
The 1/f noise contribution of the active load is reduced by choosing Linput <
Lload
If the above conditions are satisfied the input noise is dominated by the input
pair.
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Cascode scheme:
The noise is contributed by the input
pair and the current sources of the
cascode load
vn4
M4
M3
Out
M2
2
V n, in
= 2 V n1
g m4 2 2
+ ---------- V n4
g m1
vn1
M1
I1
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Folded Cascode scheme:
M2
v n1
M1
M3
Out
M4
v
I1
n5
M5
The noise contributed by the same source as in the cascode and
by the current source M2
2
V n, in
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= 2
2
V n1
2
g m2 2
2 g m5
2
+ ---------- V n2 + ---------- V n5
g m1
g m1
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Two stages amplifier: (feedforward + zero nulling compensation)
Cc
Rz
Out
+
v
v
m 1 i1
n1
v
r1
C1
+
n2
g v
m 2 i2
C2
The noise is modelled with two input referred noise sources: one
at the input of the first stage and the other at the input of the
second stage.
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[dB] p
out
v
n1
out
v
n2
2
log(f)
[dB] p
2
log(f)
1/|Av1|
In the low frequency range the noise is dominated by Vn1.
In the high frequency range the noise is dominated by Vn2.
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Frequency response:
The input referred noise generator is transmitted to the output as a
conventional input signal
The feedback network around the op-amp must be taken into account.
One stage amplifier:
Out
+
The cutoff frequency is:
g v
m i
r
0
C0
p1 = -gm/C0
[dB]
v
out
v
n
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1
log(f)
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Power of the noise:
We consider only the white term.
One stage amplifier:
df
4 kT
df
8
8
1 dx
1
2
2
V n0 = V n ---------------------------2- = 2 --- kT ---------- ------------------------------------------------2- = 2 --- kT -------------- --------------2- = --- ------3 C0
3
3 2C 0 0 1 + x
g m1 1 + ( 2 fC g )
1
+
s
p
0
0
1
0
m1
Two stages amplifier: we consider only the white term contributed by the
noise source of the second stage.
8 kT
2
V n2 = 2' --- ----------
3 g m2
V n0 =
df
2
--------------------------V
0 n2
2
1 + s p2
g m2
p = -------------------C1 + C2
2
4
kT
2
V n0 = --- ' ------------------------3 ( C1 + C2 )
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LAYOUT
Rules:
Use poly connection only for signal, never for current because the offset
RI 15 mV.
Minimize the line length, especially for lines connecting high impedance
nodes (if they are not the dominant node).
Use matched structure. If necessary common centroid arrangement.
Respect symmetries (even respect power devices).
Only straight-line transistors.
Separate (or shield) the input from the output line, to avoid feedback.
Shielding of high impedance nodes to avoid noise injection from the
power supply and the substrate.
Regular shape and use a layout oriented design.
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Stacked layout:
C sb = C db = C jb W ( d + 2x j )
Source
L
Drain
Structure A:
d
C sb
1
W
= --- C db = C jb ----- ( d + 2x j )
2
2
w
Drain
Source
Structure B:
w/2
2W
C sb = C db = C jb --------- ( d + 2x j )
3
w/3
Drain
Drain
Source
Source
Drain
Drain
Source
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Capacitances are further reduced if the diffusion area is shared
between different transistors
Key point: use of equal width transistors (or part of transistors)
Transistors with arbitrary width are not allowed
Placement and routing:
If we divide a transistor in an
odd number of parallel
transistors the resulting
stack has the source on one
side and the drain on the
other side
If we divide a transistor in an
even number of parts the
resulting stack has source or
drain on the two sides.
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Drain
Drain
Source
Source
Drain
Drain
Source
Source
Drain
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Example:
1
200
150
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4
3
150
200
5
4
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Routing into stacks: use of comb connections or serpentine connections.
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Fully differential folded cascode. Example
Features, symmetry, common centroid input pair, minimum mine length.
2
M10
M9
VB1
10
10
11
13
13
13
13
13
13
12
M2
M1
4
M3
VB2
4
M4
Out
Out
M6
VB3
2
M5
VB4
VB5
M13
6
2
M8
2
M7
M11
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M12
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VDD
VB1
VB2
V+
V_
VB4
VB5
VB3
VSS
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