MICROCONTROLLERS &

EMBEDDED SYSTEMS
MODULE-V

Contents
PIC 16F877
Introduction
Pin Diagram
Architecture
Architectural description
Data Memory
Addressing modes
PCON register
Program Memory
Data EEPROM
OPTION register
Instruction Set
Interrupts
Reading from Data EEPROM Memory
Writing to Data EEPROM Memory
Architectural description(contd..)
Ports
CCP Modules
Serial communication
A/D Converter
Program for Square wave generation

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Introduction
PIC Peripheral Interface Controller
RISC Processor with Harvard architecture
16F877 belongs to the category of CMOS 8 bit Flash MCs.
Non Volatile memory (PEROM)
Easier and faster than EEPROM
No waiting time for erasure
About 1000 write/erase cycles are possible
8K x 14 words flash program memory
Data memory
368 x 8 bytes of RAM
256 x 8 bytes of EEPROM

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Power consumption is v.low

Operating frequencies vary from DC to 20 MHz
Wide operating voltage range: 2.0 V to 5.5 V
High Sink/Source Current: 25 mA

3 Timers+ Watchdog Timer(WDT)

Timer 08 bit/counter
Timer 116 bit/counter
Timer 28 bit timer
5 I/O ports
PORT A,B,C,D,E
Eight level deep hardware stack
8 channel 10 bit ADC
Two capture/compare/PWM (CCP) modules

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Two serial ports (USART & MSSP) and a parallel 8 bit wide slave
port(PSP)

Power-up Timer (PWRT)

Oscillator Start-up Timer (OST)
Power on Reset (POR)
Brown out Reset (BOR)
Selectable oscillator options

14 interrupt sources
35 instructions
Non-overlapping instruction set
200ns instruction cycle

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CPU pipelines instruction fetching and execution in order to

achieve an execution of one instruction at every cycle
Direct, indirect and relative addressing modes

Programmable code protection

Power saving SLEEP mode
In circuit debugger
Low voltage programming
40 pin PDIP

Pin Diagram

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Pins 11&32 VDD

Pins 12 & 31Vss
Pin 13OSC/CLKIN
Pin 14OSC/CLKOUT

Bi-directional I/O Ports

PORTA Pins(2-7)
PORTE Pins(8-10)
Alternate function is analog I/Ps to ADC(AD0-AD7)

PORTC Pins(15-18) & Pins(23-26)

PORTD Pins(19-22) & Pins (27-30)
Parallel Slave Port & Serial Communication port

PORTB Pins (33-40)

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PIC Architecture

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Simplified Architectural
diagram

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ALU
8 bits wide

Perform operations on W register and any other register

file( or immediate constant)
May affect various flags in the STATUS register
Carry (C)
Digit Carry (DC)
Zero (Z)

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CPU Registers

W or working register
STATUS register
FSR [Indirect Memory Address pointer]
INDF

PCLATH5 bits
PCL8 bits

8 bits

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W(Working) Register
Contains one of the source operands during the
execution of instructions
May serve as a destination for the result
Used only for ALU operations and is not an addressable
register.

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PCLATH
PCLATH is a 8-bit register which can be used to decide the upper 5
bits of the program counter.
PCLATH is not the upper 5 bits of the program counter.

PCLATH can be read from or written to without affecting the

program counter.
The upper 3 bits of PCLATH remain zero and they serve no
purpose.
Any write to PCL will cause the contents of PCLATH to be
transferred into higher memory locations of the 13 bit Program
counter(PC).

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PCL
PCL is actually the lower 8-bits of the 13-bit program
counter.
This is both readable and writable register.

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8 level Stack
8-level deep x 13-bit wide(same as PC) stack
The stack space is not part of either program or data space and the
stack pointer is not readable or writable.
PCLATH is not affected by a PUSH or POP operation.
The PC is pushed onto the stack when a CALL instruction is
executed, or an interrupt causes a branch.
The stack is popped in the event of a RETURN,RETLW or a RETFIE
instruction execution.
The stack operates as a circular buffer

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There are no status bits to indicate stack overflow or stack

underflow conditions.

There are no instructions/mnemonics called PUSH or POP.

Program memory paging
The CALL and GOTO instructions provide
only 11 bits of address to allow branching
within any 2K program memory page.
Upper 2 bits come from PCLATH to form
the effective 13 bit address
The user must ensure that the page
select bits are programmed so that the
desired program memory page is
addressed.
If a return from a CALL instruction (or
interrupt) is executed, the entire 13-bit
PC is popped off the stack.

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STATUS Register

(ADDRESS 03h, 83h, 103h, 183h)

The STATUS register contains the arithmetic status of

the ALU(bits 0-2).
The RESET status(bits 3-4).
The bank select bits for data memory(bits 5-7).
RP1,RP0 Direct addressing mode
IRP Indirect addressing mode

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Data Memory Organization

Register file is a term used for memory locations that are
addressed by an instruction.
The data memory(register file) is partitioned into multiple
banks which contain the General Purpose Registers and the
Special Function Registers.
Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank
select bits.

Each bank extends up to 7Fh (128 bytes).

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The lower address locations of each bank are reserved

for the Special Function Registers (I/O Ports + Control
registers).
CPU(core) & Peripheral modules access the SFRs for
controlling the device operation.

Above the Special Function Registers are General

Purpose Registers, implemented as static RAM/
processors on chip RAM (8 bit).
Some of the SFRs are mirrored in all the banks.

The register file can be accessed either directly

or
Indirectly through the File Selection Register (FSR).

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PIC 16F877 Register File Map

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Direct Addressing Mode

All instructions which use direct addressing mode,
Uses 7 bits of the instruction and the 8th & 9th bits
from RP0 & RP1 bits in the STATUS register.
Lower 7 bits of instruction code along with RP0 & RP1
bits forms the effective 9 bit address in direct
addressing mode.

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FSR (File Selection Register)

Indirect data memory address pointer
Pointer used for indirect memory addressing in the
whole register file.
For indirect addressing the address byte need to be
written in the FSR and then use INDF instruction.
So the FSR points to the desired memory location.

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INDF (INDirect through FSR)

Not a physical register.
Addressing INDF will cause indirect addressing

(FSR) or INDirect through FSR

Any instruction using the INDF register actually accesses
the register pointed to by the FSR.

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Indirect Addressing Mode

The 9 bit address of the location in the register file to be
accessed is formed by concatenating 8 bit FSR & IRP bit
Instruction which uses 00H as the direct address which
is INDF results in indirect addressing
IRP bit is used for indirect addressing

IRP bit and FSR decide the effective 9 bit address.

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PCON Register
The Power Control (PCON) Register
contains flag bits to allow
differentiation between a
Power-on Reset(POR)
Brown-out Reset (BOR)
Watchdog Reset (WDT)
External MCLR Reset.
bit 7-2 Unimplemented: Read as '0
bit 1: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset
occurs)

bit 0: Brown-out Reset

Status bit
1 = No Brown-out Reset
occurred
0 = A Brown-out Reset
occurred (must be set in
software after a Brown-out
Reset occurs)
The brown out reset circuit
can be enabled/disabled
using its configuration bit
BODEN.

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Program Memory
Organization
13-bit program counter capable
of addressing an 8K x 14 program
memory space.
The RESET vector is at 0000h
and the interrupt vector is at
0004h.
To prevent unwanted write
WRT0
WRT cannot be accessed through
user program
Code protect to prevent external
read/write
MC can read as well as execute
code

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CPU Architecture

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Data EEPROM
256 bytes of EEPROM data memory
Not located in the register files
Read & write is possible

Can be protected from external reading/writing

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Data EEPROM & FLASH Program Memory

Readable & writable
6 SFRs

EECON1
EECON2
EEDATA
EEDATAH
EEADR
EEADRH

A write operation causes an erase-then-write operation to

take place on the specified byte or word.

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Program memory can contain up to 14 bit numbers other than

valid instructions.

Executing a program memory location containing data that

form an invalid instruction, results in the execution of a NOP
instruction.
The EEPROM data memory allows single-byte read and
writes.
The Flash program memory allows single-word reads and
four-word block writes.
The write time is controlled by an on-chip timer.
It will vary with voltage and temperature as well as from
chip to chip.

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The EEPROM data memory allows byte read and write

operations without interfering with the normal operation of
the microcontroller.
The FLASH program memory allows non-intrusive read
access.
Writing to program memory will cease the execution of
instructions until the write is complete.
The program memory cannot be accessed during the write.
When the write completes, the next instruction in the pipeline
is executed.

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EECON1

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Control register for accessing the program or data

EEPROM memory.

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EECON2,EEDATA & EEADR

EECON2 is not a physical register
Used in write to Data EEPROM operation.

EEDATA EEPROM Data register

EEADR EEPROM Address register(00H-FFH)

Flash Program memory

EEDATH:EEDATA holds the 14-bit data for read/write
EEADRH:EEADR holds the 13-bit address of the program
memory location being accessed(0000H-1FFFH)

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EEADR register pair can be address up to a maximum of 256 bytes

of data EEPROM or up to a maximum of 8K words of program
EEPROM.
When selecting a data address value, only the LS (least significant)
Byte of the address is written to the EEADR register.
When selecting a program address value, the MS Byte of the address
is written to the EEADRH register and the LS Byte is written to the
EEADR register.
If the device contains less memory than the full address range of the
address register pair, the Most Significant bits of the registers are
not implemented.
For example, if the device has 128 bytes of data EEPROM, the Most
Significant bit of EEADR is not implemented on access to data EEPROM.

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Option Register

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Contains various control bits to configure the TMR0 prescaler/WDT

postscaler, the External INT Interrupt, TMR0 and the weak pull-ups
on PORTB.

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Instruction Set
Every Instruction is coded in a 14 bit word
Each instruction takes one cycle to execute
Only 35 instructions (RISC)

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Interrupts in PIC 16F877

14 Interrupt sources

RB0/INT External interrupt

PORTB change interrupt
Timer 0 overflow interrupt
Peripheral interrupts

INTCON Register

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INTCON REGISTER (ADDRESS 0Bh, 8Bh,

10Bh, 18Bh)

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bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in
software)
0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state; a mismatch
condition will continue to set the bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared(must be
cleared in software).
0 = None of the RB7:RB4 pins have changed state

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Peripheral Interrupts
PIE1,PIE2 registers
PIR1,PIR2 registers

PIEX Individual Interrupt enable bits

PIRX Individual Interrupt flag bits

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PIE1 REGISTER (ADDRESS 8Ch)

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

bit 6 ADIE: A/D Converter Interrupt Enable bit
bit 5 RCIE: USART Receive Interrupt Enable bit
bit 4 TXIE: USART Transmit Interrupt Enable bit
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
bit 2 CCP1IE: CCP1 Interrupt Enable bit
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1Enables interrupt
0Disables interrupt

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PIR1 REGISTER (ADDRESS 0Ch)

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full

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bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag

1 = The SSP interrupt condition has occurred, and must be cleared in
software before returning from the Interrupt Service Routine
0 = No SSP interrupt condition has occurred.
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in
software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode

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bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

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PIE2 REGISTER (ADDRESS 8Dh)

bit 7 Unimplemented: Read as '0'

bit 6 Reserved: Always maintain this bit clear
bit 5 Unimplemented: Read as '0'
bit 4 EEIE: EEPROM Write Operation Interrupt Enable
bit 3 BCLIE: Bus Collision Interrupt Enable
bit 2-1 Unimplemented: Read as '0'
bit 0 CCP2IE: CCP2 Interrupt Enable bit

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PIR2 REGISTER (ADDRESS 0Dh)

bit 7 Unimplemented: Read as '0'

bit 6 Reserved: Always maintain this bit clear
bit 5 Unimplemented: Read as '0'
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I2C
Master mode
0 = No bus collision has occurred

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bit 2-1 Unimplemented: Read as '0'

bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in
software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused

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Interrupt Logic Diagram

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Reading the EEPROM Data Memory

The steps to reading the EEPROM data memory are:
1. Write the address to EEDATA. Make sure that the address is
not larger than the memory size of the PIC16F87X device.
2. Clear the EEPGD bit to point to EEPROM data memory.
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA register.

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STATUS equ h03

ADDR equ h40
EEADR equ h10D
EECON1 equ h18C
EEDATA equ h10C
RP1 equ 6
RP0 equ 5
EEPGD equ 7
RD equ 0

ORG 0
GOTO START
START

NOP
CALL PGM
GOTO START

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PGM

END

BSF STATUS, RP1

BCF STATUS, RP0
MOVF ADDR, W
MOVWF EEADR
BSF STATUS, RP0
BCF EECON1, EEPGD
BSF EECON1, RD
BCF STATUS, RP0
MOVF EEDATA, W
RETURN

;Bank 2
;Write address
;to read from
;Bank 3
;Point to Data memory
;Start read operation
;Bank 2
;W = EEDATA

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Writing to the EEPROM Data Memory

1.

If step 10 is not implemented, check the WR bit to see if a write

is in progress.

2.

Write the address to EEADR. Make sure that the address is not
larger than the memory size of the PIC16F87X device.

3.

Write the 8-bit data value to be programmed in the EEDATA

register.

4.

Clear the EEPGD bit to point to EEPROM data memory

5.

Set the WREN bit to enable program operations.

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6. Disable interrupts (if enabled).

7. Execute the special five instruction sequence:

Write 55h to EECON2 in two steps (first to W,
then to EECON2)
Write AAh to EECON2 in two steps (first to W,
then to EECON2)
Set the WR bit
8. Enable interrupts (if using interrupts).

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9. Clear the WREN bit to disable program operations.

10. At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by hardware.)
If step 1 is not implemented, then check whether EEIF is
set, or WR to clear, to indicate the end of the program
cycle.

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STATUS equ h03

EEPROM_ADDR equ h40
EEADR equ h10D
EECON1 equ h18C
EEDATA equ h10C
EEPROM_DATA equ h77
RP1 equ 6
RP0 equ 5
EEPGD equ 7
RD equ 0
WR equ 1
WREN equ 2
INTCON equ h18B

GIE equ 7
EECON2 equ h18D
PIE2 equ h8D
PIR2 equ h0D
EEIE equ 4
EEIF equ 4
PEIE equ 6

ORG 0
GOTO START
ORG 4
GOTO INTR

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;Main program

START NOP
BSF STATUS, RP0
BCF STATUS, RP1
BSF PIE2,EEIE
BSF INTCON,PEIE
CALL PGM
GOTO START
;Subroutine for writing a byte in Data EEPROM
PGM BSF STATUS,RP1
BCF STATUS,RP0
MOVF EEPROM_ADDR, W
MOVWF EEADR
MOVF EEPROM_DATA, W
MOVWF EEDATA
BSF STATUS, RP0
BCF EECON1, EEPGD
BSF EECON1, WREN

;Bank 1

;Bank 2
;Address to
;write to
;Data to
;write
;Bank 3
;Point to Data memory

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;Only disable interrupts

BCF INTCON, GIE
;otherwise discard
;Special 5 instruction sequence
MOVLW 0x55
MOVWF EECON2
MOVLW 0xAA
MOVWF EECON2
BSF EECON1, WR
;Only enable interrupts
BSF INTCON, GIE
;otherwise discard
SLEEP

;if already enabled,

;Write 55h to
;EECON2
;Write AAh to
;EECON2
;Start write operation

;if using interrupts,

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NOP

BSF STATUS,RP0
BSF STATUS,RP1
BCF EECON1, WREN
RETURN
;ISR
INTR BCF STATUS,RP0
BCF STATUS,RP1
BCF PIR2,EEIF
RETFIE
END

;Bank 3

;Bank 0

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WDT (Watchdog Timer)

Used to prevent the processor from endless loop.
Resets PIC MC if CLRWDT instruction is not executed periodically.
Resets the timeout bit
If working normally, it will set the timeout bit in the STATUS
register
Normal timeout period is 18ms.
Internal RC oscillator drives WDT.
Once enabled at the time of device programming, cannot be
disabled by any means and vice versa.
Programmable prescaling is possible with the help of PSA,PS0,PS1
& PS2 bits.
With all bits set to 1,max.time out period possible is 2.304sec.
Can wake up the processor from sleep.
If the device is in SLEEP mode, a WDT time-out causes the
device to wake-up and continue with normal operation

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Ports
5 I/O ports

Port A6 bits wide

Port B,C,D8 bits wide
Port E3 bits wide
All ports are bi-directional
Data direction registers
TRISA,TRISB,TRISC,TRISD,TRISE

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PORT A & PORT B

I/O direction TRISA
register
Clearing TRISA Makes Port
A as O/P
Setting TRISA Makes Port A
as I/P
Alternate function of analog
I/P & Vref
Pin RA4T0CKI(TMR0 clk
I/P) pin

I/O direction TRISB

register
Low voltage programming
functions
Weak internal Pull-ups
Port B change interrupt

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PORT C & PORT D

I/O direction TRISC I/O direction TRISD
register
register
Many peripheral functions Used as an 8 bit parallel
slave port(PSP)
are multiplexed
MSSP
CCP
USART

Schmitt trigger I/P buffers

By setting PSPMODE bit in

TRISE register.

Schmitt trigger I/P buffers

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PORT E
Serves as control I/Ps for PSP
As Analog I/P
Schmitt trigger I/P buffers

TRISE Register

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bit 2,1,0Port E data direction bits

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Parallel Slave Port

8 bits wide
In slave mode, the port can be read/written by
external source using control signals RD & WR.
Consist of two 8-bit latches

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CCP Modules
Capture
Transfer the contents of an internal 16 bit timer into a SFR
upon detection of a rising/falling edge

Compare
Generates an interrupt or changes the status of O/P pin
when Timer1 matches a predefined comparison value.

PWM
Generates a rectangular wave with a programmable duty
cycle at user defined frequency

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2 capture/compare modulesCCP1 & CCP2

Similar operations
CCP1CON & CCP2CON registers controls CCP1 & CCP2
modules
Each Capture/Compare/PWM (CCP) module contains a 16-bit
register which can operate as a:

16-bit Capture register

16-bit Compare register
PWM Master/Slave Duty Cycle register
CCPR1CCPR1H & CCPR1L
CCPR2CCPR2H & CCPR2L
RC2/CCP1 & RC1/T1OSI/CCP2 are the pins used for the
purpose

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MSSP
The Master Synchronous Serial Port (MSSP) module is a
serial interface, useful for communicating with other
peripherals or microcontroller devices.
Peripheral devices include serial EEPROMs, shift
registers, display drivers, A/D converters etc.

The MSSP module can operate in one of two modes:

Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)

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SPI
Developed by Motorola and supported by various
controllers.
Supports SPI using master/slave relationships among
devices.
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously.

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I2C
Two wire serial bus developed by Philips for simple
inexpensive communications, usually between ICs on
the same PCB.
Serial data line(SDL) & Serial clock line(SCL).
Each device connected to this bus is software
addressable.
Multi master and multi slave configuration.
Pins 18 & 23 are used for the purpose.

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USART

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The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial I/O
modules.
USART is also known as a Serial Communications Interface or
SCI

The USART can be configured in the following modes:

Asynchronous (full duplex)
CRT terminals and personal computers

Synchronous - Master (half duplex)

Synchronous - Slave (half duplex)
A/D or D/A integrated circuits, serial EEPROMs etc.

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RC6/TX/CK and RC7/RX/DT pins are used.

The USART module also

communication
capability
detection.

has a
using

multi-processor
9-bit
address

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A/D Converter
8 analog inputs
Result is a 10 bit number
Successive approximation

ADRESH,ADRESL
ADCON0,ADCON1
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode.
To operate in SLEEP, the A/D clock must be derived from the
internal RC oscillator.

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Square Wave Generation

WAP to create a square wave of 50% duty cycle on Port C
D1 EQU 0X40
D2 EQU 0X42
D3 EQU 0X44

HERE

BSF STATUS, RP0

BCF STATUS, RP1
MOVLW 0x00
MOVWF TRISC
BCF STATUS, RP0
MOVLW 0xFF
MOVWF PORTC
CALL DELAY
CLRF PORTC
CALL DELAY
GOTO HERE

;Bank 1
;Bank 0

85
Ragam R_DEEE_RSET

DELAY

MOVLW 0X03
MOVWF D1
MOVLW 0X18
MOVWF D2
MOVLW 0X02
MOVWF D3
DELAY_O
DECFSZ D1,1
GOTO DELAY_O
DECFSZ D2,1
GOTO DELAY_O
DECFSZ D3,1
GOTO DELAY_O
RETURN
END

86
Ragam R_DEEE_RSET

References

Ajay V Deshmukh , Microcontrollers- Theory

and
Applications , Tata McGraw Hill
Education, New Delhi

Microchip PIC 16F87X Data Sheet