2/6/2019 ARM7TDMI Technical Reference Manual A.3.

Signal descriptions

ARM7TDMI Technical Reference Manual Revision: r4p1

A.3. Signal descriptions

Table A.3 describes all the signals used for the ARM7TDMI r4p1 processor.

Table A.3. Signal descriptions

Name Type Description

A[31:0] O This is the 32-bit address bus. ALE, ABE, and APE are used to control when
the address bus is valid.
Addresses

ABE IC The address bus drivers are disabled when this is LOW, putting the address
bus into a high impedance state. This also controls the LOCK, MAS[1:0],
Address bus nRW, nOPC, and nTRANS signals in the same way. ABE must be tied HIGH
enable if there is no system requirement to disable the address drivers.

ABORT IC The memory system uses this signal to tell the processor that a requested
access is not allowed.
Memory abort

ALE IC This signal is provided for backwards compatibility with older ARM processors.
For new designs, if address retiming is required, ARM Limited recommends
Address latch the use of APE, and for ALE to be connected HIGH.
enable
The address bus, LOCK, MAS[1:0], nRW, nOPC, and nTRANS signals are
latched when this is held LOW. This enables these address signals to be held
valid for the complete duration of a memory access cycle. For example, when
interfacing to ROM, the address must be valid until after the data has been
read.

APE IC Selects whether the address bus, LOCK, MAS[1:0], nRW, nTRANS, and
nOPC signals operate in pipelined (APE is HIGH) or depipelined mode (APE
Address pipeline is LOW).
enable
Pipelined mode is particularly useful for DRAM systems, where it is desirable
to provide the address to the memory as early as possible, to allow longer
periods for address decoding and the generation of DRAM control signals. In
this mode, the address bus does not remain valid to the end of the memory
cycle.
Depipelined mode can be useful for SRAM and ROM access. Here the address
bus, LOCK, MAS[1:0], nRW, nTRANS, and nOPC signals must be kept
stable throughout the complete memory cycle. However, this does not
provide optimum performance.
See Address timing for details of this timing.

BIGEND IC Selects how the processor treats bytes in memory:

Big endian HIGH for big-endian format

configuration LOW for little-endian format.

BL[3:0] IC The values on the data bus are latched on the falling edge of MCLK when
these signals are HIGH. For most designs these signals must be tied HIGH.
Byte latch
control

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2/6/2019 ARM7TDMI Technical Reference Manual A.3. Signal descriptions

Name Type Description

BREAKPT IC A conditional request for the processor to enter debug state is made by
placing this signal HIGH. If the memory access at that time is an instruction
Breakpoint fetch, the processor enters debug state only if the instruction reaches the
execution stage of the pipeline. If the memory access is for data, the
processor enters debug state after the current instruction completes
execution. This enables extension of the internal breakpoints provided by the
EmbeddedICE-RT logic.

See Behavior of the program counter in debug state for details on the use of
this signal.

BUSDIS O When INTEST is selected on scan chain 0, 4, or 8 this is HIGH. It can be used
to disable external logic driving onto the bidirectional data bus during scan
Bus disable testing. This signal changes after the falling edge of TCK.

BUSEN IC A static configuration signal that selects whether the bidirectional data bus
(D[31:0]) or the unidirectional data busses (DIN[31:0] and DOUT[31:0])
Data bus are used for transfer of data between the processor and memory.
configuration
When BUSEN is LOW, D[31:0] is used; DOUT[31:0] is driven to a value of
zero, and DIN[31:0] is ignored, and must be tied LOW.
When BUSEN is HIGH, DIN[31:0] and DOUT[31:0] are used; D[31:0] is
ignored and must be left unconnected.
See Chapter 3 Memory Interface for details on the use of this signal.

COMMRX O When the communications channel receive buffer is full this is HIGH.

Communications This signal changes after the rising edge of MCLK.

channel receive
See Debug Communications Channel for more information.

COMMTX O When the communications channel transmit buffer is empty this is HIGH. This
signal changes after the rising edge of MCLK.
Communications
channel See Debug Communications Channel for more information.
transmit

CPA IC Placed LOW by the coprocessor if it is capable of performing the operation

requested by the processor.
Coprocessor
absent

CPB IC Placed LOW by the coprocessor when it is ready to start the operation
requested by the processor.
Coprocessor
busy It is sampled by the processor when MCLK goes HIGH in each cycle in which
nCPI is LOW.

D[31:0] IC Used for data transfers between the processor and external memory.

Data bus O During read cycles input data must be valid on the falling edge of MCLK.

During write cycles output data remains valid until after the falling edge of
MCLK.
This bus is always driven except during read cycles, irrespective of the value
of BUSEN. Consequently it must be left unconnected if using the
unidirectional data buses.

See Chapter 3 Memory Interface.

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2/6/2019 ARM7TDMI Technical Reference Manual A.3. Signal descriptions

Name Type Description

DBE IC Must be HIGH for data to appear on either the bidirectional or unidirectional
data output bus.
Data bus enable
When LOW the bidirectional data bus is placed into a high impedance state
and data output is prevented on the unidirectional data output bus.
It can be used for test purposes or in shared bus systems.

DBGACK O When the processor is in a debug state this is HIGH.

Debug
acknowledge

DBGEN IC A static configuration signal that disables the debug features of the processor
when held LOW.
Debug enable
This signal must be HIGH to enable the EmbeddedICE-RT logic to function.

DBGRQ IC This is a level-sensitive input, that when HIGH causes ARM7TDMI core to
enter debug state after executing the current instruction. This enables
Debug request external hardware to force the ARM7TDMI core into debug state, in addition
to the debugging features provided by the EmbeddedICE-RT logic.

See Appendix B Debug in Depth.

DBGRQI O This is the logical OR of DBGRQ and bit [1] of the debug control register.

Internal debug
request

DIN[31:0] IC Unidirectional bus used to transfer instructions and data from the memory to
the processor.
Data input bus
This bus is only used when BUSEN is HIGH. If unused then it must be tied
LOW.
This bus is sampled during read cycles on the falling edge of MCLK.

DOUT[31:0] O Unidirectional bus used to transfer data from the processor to the memory
system.
Data output bus
This bus is only used when BUSEN is HIGH. Otherwise it is driven to a value
of zero.
During write cycles the output data becomes valid while MCLK is LOW, and
remains valid until after the falling edge of MCLK.

DRIVEBS O Controls the multiplexors in the scan cells of an external boundary-scan

chain.
Boundary scan
cell enable This must be left unconnected, if an external boundary-scan chain is not
connected.

ECAPCLK O Only used on the ARM7TDMI test chip, and must otherwise be left
unconnected.
EXTEST capture
clock

ECAPCLKBS O Used to capture the device inputs of an external boundary-scan chain during
EXTEST.
EXTEST capture
clock for When scan chain 3 is selected, the current instruction is EXTEST and the TAP
boundary-scan controller state machine is in the CAPTURE- DR state, then this signal is a
pulse equal in width to TCK2.
This must be left unconnected, if an external boundary-scan chain is not
connected.

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2/6/2019 ARM7TDMI Technical Reference Manual A.3. Signal descriptions

Name Type Description

ECLK O In normal operation, this is simply MCLK, optionally stretched with nWAIT,
exported from the core. When the core is being debugged, this is DCLK,
External clock which is generated internally from TCK.
output

EXTERN0 IC This is connected to the EmbeddedICE-RT logic and enables breakpoints and
watchpoints to be dependent on an external condition.
External input 0

EXTERN1 IC This is connected to the EmbeddedICE-RT logic and enables breakpoints and
watchpoints to be dependent on an external condition.
External input 1

HIGHZ O When the HIGHZ instruction has been loaded into the TAP controller this
signal is HIGH.
High impedance
See Appendix B Debug in Depth for details.

ICAPCLKBS O This is used to capture the device outputs in an external boundary-scan chain
during INTEST.
INTEST capture
clock This must be left unconnected, if an external boundary-scan chain is not
connected.

INSTRVALID O Indicates that the instruction in the Execute stage of the pipeline was valid
and has been executed (unless it failed its conditions codes).
Instruction valid

IR[3:0] O Reflects the current instruction loaded into the TAP controller instruction
register. These bits change on the falling edge of TCK when the state
TAP controller machine is in the UPDATE-IR state.
instruction
register The instruction encoding is described in Public instructions.

ISYNC IC Set this HIGH if nIRQ and nFIQ are synchronous to the processor clock. Set
it LOW for asynchronous interrupts.
Synchronous
interrupts

LOCK O When the processor is performing a locked memory access this is HIGH. This
is used to prevent the memory controller allowing another device to access
Locked the memory.
operation
It is active only during the data swap (SWP) instruction.
This is one of the signals controlled by APE, ALE and ABE.

MAS[1:0] O Used to indicate to the memory system the size of data transfer (byte,
halfword or word) required for both read and write cycles, become valid
Memory access before the falling edge of MCLK and remain valid until the rising edge of
size MCLK during the memory cycle.

The binary values 00, 01, and 10 represent byte, halfword, and word
respectively (11 is reserved).

This is one of the signals controlled by APE, ALE, and ABE.

MCLK IC This is the main clock for all memory accesses and processor operations. The
clock speed can be reduced to enable access to slow peripherals or memory.
Memory clock
input Alternatively, the nWAIT can be used with a free-running MCLK to achieve
the same effect.

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2/6/2019 ARM7TDMI Technical Reference Manual A.3. Signal descriptions

Name Type Description

nCPI O LOW when a coprocessor instruction is processed. The processor then waits
for a response from the coprocessor on the CPA and CPB lines.
Not coprocessor
instruction If CPA is HIGH when MCLK rises after a request has been initiated by the
processor, then the coprocessor handshake is aborted, and the processor
enters the undefined instruction trap.
If CPA is LOW at this time, then the processor enters a busy-wait period until
CPB goes LOW before completing the coprocessor handshake.

nENIN IC This must be LOW for the data bus to be driven during write cycles.

NOT enable Can be used in conjunction with nENOUT to control the data bus during write
input cycles.
See Chapter 3 Memory Interface.

nENOUT O During a write cycle, this signal is driven LOW before the rising edge of
MCLK, and remains LOW for the entire cycle. This can be used to aid
Not enable arbitration in shared bus applications.
output
See Chapter 3 Memory Interface.

nENOUTI O During a coprocessor register transfer C-cycle from the EmbeddedICE-RT

communications channel coprocessor to the ARM core, this signal goes LOW.
Not enable This can be used to aid arbitration in shared bus systems.
output

nEXEC O This is HIGH when the instruction in the execution unit is not being executed
because, for example, it has failed its condition code check.
Not executed

nFIQ IC Taking this LOW causes the processor to be interrupted if the appropriate
enable in the processor is active. The signal is level-sensitive and must be
Not fast held LOW until a suitable response is received from the processor. nFIQ can
interrupt be synchronous or asynchronous to MCLK, depending on the state of ISYNC.
request

nHIGHZ O When the current instruction is HIGHZ this signal is LOW. This is used to
place the scan cells of that scan chain in the high impedance state.
Not HIGHZ
This must be left unconnected, if an external boundary-scan chain is not
connected.

nIRQ IC As nFIQ, but with lower priority. Can be taken LOW to interrupt the processor
when the appropriate enable is active. nIRQ can be synchronous or
Not interrupt asynchronous, depending on the state of ISYNC.
request

nM[4:0] O These are the inverse of the internal status bits indicating the current
processor mode.
Not processor
mode

nMREQ O When the processor requires memory access during the following cycle this is
LOW.
Not memory
request

nOPC O When the processor is fetching an instruction from memory this is LOW.

Not op-code This is one of the signals controlled by APE, ALE, and ABE.
fetch

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2/6/2019 ARM7TDMI Technical Reference Manual A.3. Signal descriptions

Name Type Description

nRESET IC Used to start the processor from a known address.

Not reset A LOW level causes the instruction being executed to terminate abnormally.

This signal must be held LOW for at least two clock cycles, with nWAIT held
HIGH.
When LOW the processor performs internal cycles with the address
incrementing from the point where reset was activated. The address
overflows to zero if nRESET is held beyond the maximum address limit.

When HIGH for at least one clock cycle, the processor restarts from address
0.

nRW O When the processor is performing a read cycle, this is LOW.

Not read, write This is one of the signals controlled by APE, ALE, and ABE.

nTDOEN O When serial data is being driven out on TDO this is LOW.

Not TDO enable Usually used as an output enable for a TDO pin in a packaged part.

nTRANS O When the processor is in User mode, this is LOW.

Not memory It can be used either to tell the memory management system when address
translate translation is turned on, or as an indicator of non-User mode activity.
This is one of the signals controlled by APE, ALE, and ABE.

nTRST IC Reset signal for the boundary-scan logic. This pin must be pulsed or driven
LOW to achieve normal device operation, in addition to the normal device
Not test reset reset, nRESET.

See Chapter 5 Debug Interface.

nWAIT IC When LOW the processor extends an access over a number of cycles of
MCLK, which is useful for accessing slow memory or peripherals.
Not wait
Internally, nWAIT is logically ANDed with MCLK and must only change when
MCLK is LOW.
If nWAIT is not used it must be tied HIGH.

PCLKBS O This is used by an external boundary-scan chain as the update clock.

Boundary scan This must be left unconnected, if an external boundary-scan chain is not
connected.
update clock

RANGEOUT0 O When the EmbeddedICE-RT watchpoint unit 0 has matched the conditions
currently present on the address, data, and control buses, then this is HIGH.
EmbeddedICE-
RT RANGEOUT0 This signal is independent of the state of the watchpoint enable control bit.
RANGEOUT0 changes when ECLK is LOW.

RANGEOUT1 O As RANGEOUT0 but corresponds to the EmbeddedICE-RT watchpoint unit 1.

EmbeddedICE-
RT RANGEOUT1

RSTCLKBS O When either the TAP controller state machine is in the RESET state or when
nTRST is LOW, then this is HIGH. This can be used to reset external
Boundary scan boundary-scan cells.
Reset Clock

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2/6/2019 ARM7TDMI Technical Reference Manual A.3. Signal descriptions

Name Type Description

SCREG[3:0] O These reflect the ID number of the scan chain currently selected by the TAP
controller. These change on the falling edge of TCK when the TAP state
Scan chain machine is in the UPDATE-DR state.
register

SDINBS O This provides the serial data for an external boundary-scan chain input. It
changes from the rising edge of TCK and is valid at the falling edge of TCK.
Boundary scan
serial input data

SDOUTBS IC Accepts serial data from an external boundary-scan chain output,

synchronized to the rising edge of TCK.
Boundary scan
serial output This must be tied LOW, if an external boundary-scan chain is not connected.
data

SEQ O When the address of the next memory cycle is closely related to that of the
last memory access, this is HIGH.
Sequential
address In ARM state the new address can be for the same word or the next. In
THUMB state, the same halfword or the next.
It can be used, in combination with the low-order address lines, to indicate
that the next cycle can use a fast memory mode (for example DRAM page
mode) or to bypass the address translation system.

SHCLKBS O Used to clock the master half of the external scan cells and follows TCK1
when in the SHIFT-DR state of the state machine and scan chain 3 is
Boundary scan selected. When not in the SHIFT-DR state or when scan chain 3 is not
shift clock, selected, this clock is LOW.
phase one

SHCLK2BS O As SHCLKBS but follows TCK2 instead of TCK1.

Boundary scan This must be left unconnected, if an external boundary-scan chain is not
shift clock, connected.
phase two

TAPSM[3:0] O These reflect the current state of the TAP controller state machine. These bits
change on the rising edge of TCK.
TAP controller
See Figure B.2.
state machine

TBE IC When LOW, D[31:0], A[31:0], LOCK, MAS[1:0], nRW, nTRANS, and
nOPC are set to high impedance.
Test bus enable
Similar in effect as if both ABE and DBE had been driven LOW. However, TBE
does not have an associated scan cell and so enables external signals to be
driven high impedance during scan testing.

Under normal operating conditions TBE must be HIGH.

TBIT O When the processor is executing the THUMB instruction set, this is HIGH. It is
LOW when executing the ARM instruction set.

This signal changes in phase two in the first execute cycle of a BX instruction.

TCK IC Clock signal for all test circuitry. When in debug state, this is used to
generate DCLK, TCK1, and TCK2.

TCK1 O HIGH when TCK is HIGH (slight phase lag because of the internal clock non-
overlap).
TCK, phase one

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2/6/2019 ARM7TDMI Technical Reference Manual A.3. Signal descriptions

Name Type Description

TCK2 O HIGH when TCK is LOW (slight phase lag because of the internal clock non-
overlap).
TCK, phase two
It is the non-overlapping complement of TCK1.

TDI IC Serial data for the scan chains.

TDO O Serial data from the scan chains.

Test data output

TMS IC Mode select for scan chains.

VDD P Provide power to the device.

Power supply

VSS P These connections are the ground reference for all signals.

Ground

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