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II Semester M.TECH - IA3Test Course: High Speed VLSI Design

This document contains a test for a high-speed VLSI design course. It has two sections with multiple choice questions in each section. Section 1 asks about domino CMOS logic, set up and hold times, clock skew, pass gate logic, and asynchronous latches. Section 2 covers static CMOS NAND structures, differential domino structures, cross coupled domino structures, storage elements, static and dynamic latches, and latching differential logic. Students must choose one full question from each section and answer it in 90 minutes.

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35 views1 page

II Semester M.TECH - IA3Test Course: High Speed VLSI Design

This document contains a test for a high-speed VLSI design course. It has two sections with multiple choice questions in each section. Section 1 asks about domino CMOS logic, set up and hold times, clock skew, pass gate logic, and asynchronous latches. Section 2 covers static CMOS NAND structures, differential domino structures, cross coupled domino structures, storage elements, static and dynamic latches, and latching differential logic. Students must choose one full question from each section and answer it in 90 minutes.

Uploaded by

srija
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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II Semester M.

TECH– IA3Test
Course: High Speed VLSI Design

Max Marks: 30 Duration: 90 minutes


Date:31/05/2018
Note: Answer one full question from each section

Section- 1
1. a. Explain Domino CMOS logic with diagram and discuss its function and 08 marks
characteristics

b. What do you understand by set up and hold time. What are the effects of 07 marks
clock skew on circuit design.

OR

2. a. Explain CMOS Pass gate and transmission gate logic with suitable 08 marks
diagrams. Also, explain its strength and weakness.

b. Write a short note on asynchronous latch technique (SRCMOS latch) with 07 marks
suitable diagram and also explain its characteristics.

Section-2

3. a. Explain static CMOS NAND structure with the help of diagrams. 05 Marks

b. Explain differential domino structures and cross coupled domino structures 10 marks
with suitable diagram and their characteristics.

OR

4. a. Write a short note on: i) Storage elements ii) Static and dynamic latches. 10 marks

b. Explain latching differential logic (DCVS latch) with suitable diagram. 05 marks

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