Thanks to visit codestin.com
Credit goes to www.scribd.com

Scribd
Upload
171 views3 pages

Scan Insertion Lab Observations

This document summarizes observations from a scan insertion lab. It notes that the original design had 3 S2 violations that were resolved by using the "set test logic" command to add muxes and inverters. The design has 1 scan chain, a single clock domain, 1 reset, 37 scannable flops and 3 non-scan elements, and a chain length of 40. It also provides responses to questions about the design details, block diagrams of issues and solutions, and observations from the log file.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
171 views3 pages

Scan Insertion Lab Observations

This document summarizes observations from a scan insertion lab. It notes that the original design had 3 S2 violations that were resolved by using the "set test logic" command to add muxes and inverters. The design has 1 scan chain, a single clock domain, 1 reset, 37 scannable flops and 3 non-scan elements, and a chain length of 40. It also provides responses to questions about the design details, block diagrams of issues and solutions, and observations from the log file.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 2: -
Problem Definition: - Design has S2 violations, fix using command
Inputs: -

  Synthesis Netlist
  Library Model
 Dofile commands
Outputs: -

  Scan inserted Netlist


  ATPG Dofile
  ATPG Testproc
 Scan Def

What is issue?
Ans. Design has 3 S2 violations
How resolved?

Ans.Set test logic –set on –reset on –clock on =>dofile command adds required mux
and inverter gates to clear DRC violations
Observations: -
1) Write block diagram with all DFT inputs?

FastClk

Reset

Input Scan Channel Top Design: DmaWr


Output Scan channel
Scan_En
Testen

2) How many clock domains?


Ans. FastClk
3) How many resets?
Ans. Reset

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

4) Number of scan chains


Ans. 1 scan chain

5) Clock mixing or not clock mixing?


Ans.Not clock mixing

6) How many Lockup-latches are added during scan insertion?


Ans.No lockup latches are added during scan insertion.
7) Is it top-down or bottom up approach?
Ans. Top-down approach

8) How many terminal lockup latches are added?


Ans. zero

9) Number of scan flops and non-scan flops in the


design? Ans. 37scannable flops and 3 non-scan elements
10) Chain length?
Ans. 40.

11) Number of DRC


violations? Ans. 3 S2violations
12) Write diagram with issues? (2 out of total 4)

Vlsiguru Confidential 2
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

13) Write diagram with solution?

14) Log file: - please note your observations from the log file
Ans.Top module is DmaWr
Number of shift registers =2
Number of MUX inserted =3
Number of new Pins inserted= 4 (1 scan inputs, 1 scan outputs, scan_en, test_en )

Vlsiguru Confidential 3

You might also like