LTC6803-2/LTC6803-4

Multicell Battery Stack

Monitor
FEATURES DESCRIPTION
n Measures Up to 12 Battery Cells in Series The LTC®6803 is a 2nd generation, complete battery moni-
n Stackable Architecture toring IC that includes a 12-bit ADC, a precision voltage
n Supports Multiple Battery Chemistries reference, a high voltage input multiplexer and a serial
and Supercapacitors interface. Each LTC6803 can measure up to 12 series
n Individually Addressable Serial Interface connected battery cells or supercapacitors. Many LTC6803
n 0.25% Maximum Total Measurement Error devices can be stacked to measure the voltage of each cell
n Engineered for ISO26262 Compliant Systems in a long battery string. Each LTC6803-2/LTC6803-4 has
n 13ms to Measure All Cells in a System an individually addressable serial interface, allowing up
n Passive Cell Balancing: to 16 LTC6803-2/LTC6803-4 devices to interface to one
– Integrated Cell Balancing MOSFETs control processor and operate simultaneously. Each cell
– Ability to Drive External Balancing MOSFETs input has an associated MOSFET switch for discharging
n Onboard Temperature Sensor and Thermistor Inputs overcharged cells. The LTC6803-2 connects the bottom
n 1MHz Serial Interface with Packet Error Checking of the stack to V– internally. It is pin compatible with the
n Safe with Random Connection of Cells LTC6802-2, providing a drop-in upgrade. The LTC6803-4
n Built-In Self Tests separates the bottom of the stack from V–, improving
n Delta-Sigma Converter With Built-In Noise Filter cell 1 measurement accuracy.
n Open-Wire Connection Fault Detection
n 12µA Standby Mode Supply Current
The LTC6803 provides a standby mode to reduce supply
n High EMI Immunity
current to 12µA. Furthermore, the LTC6803 can be powered
n 44-Lead SSOP Package
from an isolated supply, providing a technique to reduce
battery stack current draw to zero.
APPLICATIONS The related LTC6803-1 and LTC6803-3 offer a serial in-
terface that allows the serial ports of multiple LTC6803-1
n Electric and Hybrid Electric Vehicles
or LTC6803-3 devices to be daisy chained without opto-
n High Power Portable Equipment
n
couplers or isolators.
Backup Battery Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n Electric Bicycles, Motorcycles, Scooters Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION
NEXT 12-CELL
PACK ABOVE V+ LTC6803-4 Supply Current vs Modes of Operation
DIE TEMP 1mA
+ SERIAL
REGISTERS DATA
AND 100µA
4-BIT
MUX CONTROL ADDRESS 50V
12-CELL ISOLATED 12V 10µA
SUPPLY CURRENT

BATTERY OR + DC/DC
CAPACITOR CONVERTER
12-BIT
STRING 1µA
∆Σ ADC
+
100nA
VOLTAGE
REFERENCE
10nA
V– EXTERNAL
NEXT 12-CELL TEMP
PACK BELOW
100k NTC 1nA
100k HW STANDBY MEASURE
SHUTDOWN 680324 TA01b

680324 TA01a

680324fa

1
LTC6803-2/LTC6803-4
ABSOLUTE MAXIMUM RATINGS (Note 1)

Total Supply Voltage (V+ to V–)..................................75V Operating Temperature Range

Input Voltage (Relative to V–) LTC6803I..............................................–40°C to 85°C
C0............................................................. –0.3V to 8V LTC6803H........................................... –40°C to 125°C
C12......................................................... –0.3V to 75V Specified Temperature Range
Cn (Note 5).......................... –0.3V to Min (8 • n, 75V) LTC6803I..............................................–40°C to 85°C
Sn (Note 5).......................... –0.3V to Min (8 • n, 75V) LTC6803H........................................... –40°C to 125°C
All Other Pins............................................ –0.3V to 7V Junction Temperature............................................ 150°C
Voltage Between Inputs Storage Temperature Range................... –65°C to 150°C
Cn to Cn – 1.............................................. –0.3V to 8V Note: n = 1 to 12
Sn to Cn – 1.............................................. –0.3V to 8V
C12 to C8................................................ –0.3V to 25V
C8 to C4.................................................. –0.3V to 25V
C4 to C0.................................................. –0.3V to 25V

PIN CONFIGURATION
LTC6803-2 LTC6803-4
TOP VIEW TOP VIEW

V+ 1 44 CSBI V+ 1 44 CSBI
C12 2 43 SDO C12 2 43 SDO
S12 3 42 SDI S12 3 42 SDI
C11 4 41 SCKI C11 4 41 SCKI
S11 5 40 A3 S11 5 40 A3
C10 6 39 A2 C10 6 39 A2
S10 7 38 A1 S10 7 38 A1
C9 8 37 A0 C9 8 37 A0
S9 9 36 GPIO2 S9 9 36 GPIO2
C8 10 35 GPIO1 C8 10 35 GPIO1
S8 11 34 WDTB S8 11 34 WDTB
C7 12 33 NC C7 12 33 TOS
S7 13 32 TOS S7 13 32 VREG
C6 14 31 VREG C6 14 31 VREF
S6 15 30 VREF S6 15 30 VTEMP2
C5 16 29 VTEMP2 C5 16 29 VTEMP1
S5 17 28 VTEMP1 S5 17 28 NC
C4 18 27 NC C4 18 27 V –
S4 19 26 V – S4 19 26 C0
C3 20 25 S1 C3 20 25 S1
S3 21 24 C1 S3 21 24 C1
C2 22 23 S2 C2 22 23 S2

G PACKAGE G PACKAGE
44-LEAD PLASTIC SSOP 44-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 70°C/W TJMAX = 150°C, θJA = 70°C/W

680324fa

2
 LTC6803-2/LTC6803-4
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6803IG-2#PBF LTC6803IG-2#TRPBF LTC6803G-2 44-Lead Plastic SSOP –40°C to 85°C
LTC6803IG-4#PBF LTC6803IG-4#TRPBF LTC6803G-4 44-Lead Plastic SSOP –40°C to 85°C
LTC6803HG-2#PBF LTC6803HG-2#TRPBF LTC6803G-2 44-Lead Plastic SSOP –40°C to 125°C
LTC6803HG-4#PBF LTC6803HG-4#TRPBF LTC6803G-4 44-Lead Plastic SSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
+ –
temperature range, otherwise specifications are at TA = 25°C. V = 43.2V, V = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Specifications
VS Supply Voltage, V+ Relative to V– VERR Specification Met l 10 55 V
Timing Specification Met l 4 55 V
VLSB Measurement Resolution Quantization of the ADC l 1.5 mV/Bit
ADC Offset (Note 2) l –0.5 0.5 mV
ADC Gain Error (Note 2) –0.12 0.12 %
l –0.22 0.22 %
VERR Total Measurement Error (Note4)
VCELL = –0.3V ±2.5 mV
VCELL = 2.3V –2.8 2.8 mV
VCELL = 2.3V l –5.1 5.1 mV
VCELL = 3.6V –4.3 4.3 mV
VCELL = 3.6V, LTC6803IG l –7.9 7.9 mV
VCELL = 3.6V, LTC6803HG l –9 9 mV
VCELL = 4.2V –5 5 mV
VCELL = 4.2V, LTC6803IG l –9.2 9.2 mV
VCELL = 4.2V, LTC6803HG l –10 10 mV
VCELL = 5V ±3 mV
2.3V < VTEMP < 4.2V, LTC6803IG l –9.2 9.2 mV
2.3V < VTEMP < 4.2V, LTC6803HG l –10 10 mV
VCELL Cell Voltage Range Full-Scale Voltage Range –0.3 5 V
VCM Common Mode Voltage Range Range of Inputs Cn < 0.25% Gain Error, l 1.8 5•n V
Measured Relative to V– n = 2 to 11, LTC6803IG
Range of Inputs C0, C1 < 0.25% Gain Error, l 0 5 V
LTC6803IG
Range of Inputs Cn < 0.5% Gain Error, l 1.8 5•n V
n = 2 to 11, LTC6803HG
Range of Inputs C0, C1 < 0.5% Gain Error, l 0 5 V
LTC6803HG
Die Temperature Measurement Error Error in Measurement of 125°C 5 °C

680324fa

3
LTC6803-2/LTC6803-4
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
+ –
temperature range, otherwise specifications are at TA = 25°C. V = 43.2V, V = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Reference Pin Voltage RLOAD = 100k to V– 3.020 3.065 3.110 V
l 3.015 3.065 3.115 V
Reference Voltage Temperature 8 ppm/°C
Coefficient
Reference Voltage Thermal Hysteresis 25°C to 85°C and 25°C to –40°C 100 ppm
Reference Voltage Long-Term Drift 60 ppm/√kHr
VREF2 2nd Reference Voltage 2.25 2.5 2.75 V
l 2.1 2.5 2.9 V
VREG Regulator Pin Voltage 10V < V+ < 50V, No Load l 4.5 5.0 5.5 V
ILOAD = 4mA l 4.5 5.0 V
Regulator Pin Short-Circuit Limit l 8 mA
IB Input Bias Current In/Out of Pins C1 Through C12
When Measuring Cell –10 10 µA
When Not Measuring Cell 1 nA
IS Supply Current, Measure Mode Current Into the V+ Pin When Measuring
(Note 7) Continuous Measuring (CDC = 2) 620 780 1000 µA
Continuous Measuring (CDC = 2) l 600 780 1150 µA
Measure Every 130ms (CDC = 5) l 190 250 360 µA
Measure Every 500ms (CDC = 6) l 140 175 250 µA
Measure Every 2 Seconds (CDC = 7) l 55 70 105 µA
IQS Supply Current, Standby Current Into V+ Pin When In Standby, All Serial 8 12 16.5 µA
Port Pin at Logic “1”
LTC6803IG l 6 12 18 µA
LTC6803HG l 6 12 19 µA
ISD Supply Current, Hardware Shutdown Current Out of V–, VC12 = 43.2V, V+ Floating l 0.001 1 µA
(Note 8)
Discharge Switch-On Resistance VCELL > 3V (Note 3) l 10 20 Ω
IOW Current Used for Open-Wire Detection l 70 110 140 µA
Thermal Shutdown Temperature 145 °C
Thermal Shutdown Hysteresis 5 °C
Voltage Mode Timing Specifications
tCYCLE Measurement Cycling Time Required to Measure 12 Cells l 11 13 15 ms
Time Required to Measure 10 Cells l 9 11 13 ms
Time Required to Measure 3 Temperatures l 2.8 3.4 4.1 ms
Time Required to Measure 1 Cell or Temperature l 1.0 1.2 1.4 ms
t1 SDI Valid to SCKI Rising Setup l 10 ns
t2 SDI Valid to SCKI Rising Hold l 250 ns
t3 SCKI Low l 400 ns
t4 SCKI High l 400 ns
t5 CSBI Pulse Width l 400 ns
t6 CSBI Falling to SCKI Rising l 100 ns
t7 CSBI Falling to SDO Valid l 100 ns
t8 SCKI Falling to SDO Valid l 250 ns
Clock Frequency l 1 MHz
Watchdog Timer Timeout Period l 1 2.5 Seconds

680324fa

4
 LTC6803-2/LTC6803-4
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
+ –
temperature range, otherwise specifications are at TA = 25°C. V = 43.2V, V = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Voltage Mode Digital I/O
VIH Digital Input Voltage High Pins SCKI, SDI and CSBI l 2 V
VIL Digital Input Voltage Low Pins SCKI, SDI and CSBI l 0.8 V
VOL Digital Output Voltage Low Pin SDO, Sinking 500µA l 0.3 V
IIN Digital Input Current VMODE, TOS, SCKI, SDI, CSBI l 10 µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: These absolute maximum ratings apply provided that the voltage
may cause permanent damage to the device. Exposure to any Absolute between inputs do not exceed the absolute maximum ratings.
Maximum Rating condition for extended periods may affect device Note 6: Supply current is tested during continuous measuring. The supply
reliability and lifetime. current during periodic measuring (130ms, 500ms, 2s) is guaranteed by
Note 2: The ADC specifications are guaranteed by the Total Measurement design.
Error (VERR) specification. Note 7: The CDC = 5, 6 and 7 supply currents are not measured. They are
Note 3: Due to the contact resistance of the production tester, this guaranteed by the CDC = 2 supply current measurement.
specification is tested to relaxed limits. The 20Ω limit is guaranteed by Note 8: Limit is determined by high speed automated test capability.
design.
Note 4: VCELL refers to the voltage applied across Cn to Cn – 1 for
n = 1 to 12. VTEMP refers to the voltage applied from VTEMP1 or VTEMP2
to V–.

TYPICAL PERFORMANCE CHARACTERISTICS

Cell Measurement Error Cell Measurement Error Cell Measurement Error
vs Cell Input Voltage vs Input RC Values vs Input RC Values
4.5 5 0
TA = 125°C
TA = 85°C 0 CELLS 2 TO 12, 13ms CELL
TOTAL UNADJUSTED ERROR (mV)

3.0 TA = 25°C –5 MEASUREMENT REPETITION

CELL VOLTAGE ERROR (mV)

CELL VOLTAGE ERROR (mV)

TA = –40°C VCELL = 3.3V

–5
1.5 –10
–10
0 –15
–15 C = 0µF
C = 0.1µF
–1.5 C = 1µF –20
–20
C = 3.3µF
C = 0µF
–3.0 CELL 1, 13ms CELL MEASUREMENT –25 C = 0.1µF
–25 REPETITION C = 1µF
VCELL = 3.3V C = 3.3µF
–4.5 –30 –30
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
CELL INPUT VOLTAGE (V) INPUT RESISTANCE (kΩ) INPUT RESISTANCE (kΩ)
680324 G01 680324 G02 680324 G03

680324fa

5
LTC6803-2/LTC6803-4
TYPICAL PERFORMANCE CHARACTERISTICS
Cell Voltage Measurement Error Cell Measurement Error
Cell 12 Measurement Error vs V+ vs Common Mode Voltage vs Cell Voltage
100 2 1000
TA = 25°C ALL OTHER CELLS = 3V

CELL VOLTAGE MEASUREMENT ERROR (mV)

VCELL = 3.3V
CELL 12 MEASUREMENT ERROR (mV)

CELL MEASUREMENT ERROR (mV)

–2 100
10
–4
CELL6
–6 10

–8 VCELL = 3.6V
1
TA = 25°C
–10 CELL2 ERROR vs VC1 1
CELL3 ERROR vs VC2
–12 CELLn ERROR VS VCn–1,
n = 4 TO 12
0.1 –14 0.1
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
V+ – VC12 (V) COMMON MODE VOLTAGE (V) VIN CELL6 (V)
680324 G04 680324 G05 680324 G06

Cell 1 Voltage Measurement Error Cell 2 Voltage Measurement Error Cell 3 to Cell 12 Voltage
vs Temperature vs Temperature Measurement Error vs Temperature
1.75 2.50 1.75
VCELL = 0.8V VCELL = 0.8V
V+ = 9.6V V+ = 9.6V
CELL MEASUREMENT ERROR (mV)

4 SAMPLES
CELL MEASUREMENT ERROR (mV)

CELL MEASUREMENT ERROR (mV)

4 SAMPLES 1.75
1.00 1.00

1.00
0.25 0.25
0.25

–0.50 –0.50
–0.50

–1.25 –1.25 VCELL = 0.8V

–1.25
V+ = 9.6V
4 SAMPLES
–2.00 –2.00 –2.00
–50 –30 –10 10 30 50 70 90 110 130 –50 –30 –10 10 30 50 70 90 110 130 –50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
680324 G07 680324 G08 680324 G09

Measurement Gain Error Measurement Gain Error Cell Measurement Common Mode
Hysteresis Hysteresis Rejection
25 20 0
TA = 85°C TO 25°C TA = –45°C TO 25°C VCM(IN) = 5VP-P
18 72dB REJECTION
–10 CORRESPONDS TO
20 16 LESS THAN 1 BIT
14 –20 AT ADC OUTPUT
NUMBER OF UNITS
NUMBER OF UNITS

REJECTION (dB)

15 12
–30
10
–40
10 8
6 –50
5 4
–60
2
0 0 –70
–250 –200 –150 –100 –50 0 50 100 150 200 –250 –200 –150 –100 –50 0 50 100 150 200 10 100 1k 10k 100k 1M 10M
CHANGE IN GAIN ERROR (ppm) CHANGE IN GAIN ERROR (ppm) FREQUENCY (Hz)
680324 G10 680324 G11 680324 G12

680324fa

6
 LTC6803-2/LTC6803-4
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Normal Mode Rejection
vs Frequency ADC INL ADC DNL
0 2.0 1.0

1.5 0.8
–10
0.6
1.0
–20 0.4
REJECTION (dB)

0.5 0.2

DNL (BITS)
INL (BITS)
–30
0 0
–40
–0.5 –0.2

–50 –0.4
–1.0
–0.6
–60 –1.5 –0.8
–70 –2.0 –1.0
10 100 1k 10k 100k 0 1 2 3 4 5 0 1 2 3 4 5
FREQUENCY (Hz) INPUT (V) INPUT (V)
680324 G13 680324 G14 680324 G15

Cell Input Bias Current During Standby Supply Current Supply Current vs Supply Voltage
Standby and Hardware Shutdown vs Supply Voltage During Continuous Conversions
50 16 850
CELL INPUT = 3.6V CDC = 2
45 CONTINUOUS CONVERSION
14
CELL INPUT BIAS CURRENT (nA)

40 800
12
SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

35
30 10
750
25 8
20 6 7000
15
C12 4 125°C 125°C
10 85°C 650 85°C
C6 2
5 25°C 25°C
C1 –40°C –40°C
0 0 600
–40 –20 0 20 40 60 80 100 120 0 10 20 30 40 50 60 0 10 20 30 40 50 60
TEMPERATURE (°C) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
680324 G16 680324 G17 680324 G18

Internal Die Temperature External Temperature

Measurement Error Using an Measurement Total Unadjusted
8mV/°K Scale Factor Error vs Input
15 4.5
10 SAMPLES TA = 125°C
TA = 85°C
TOTAL UNADJUSTED ERROR (mV)

3.0 TA = 25°C
E = (AMBIENT TEMP-INTERNAL

10
TA = –40°C
DIE TEMP READING) (°C)

1.5
5
0

0
–1.5

–5 –3.0

–10 –4.5
0 25 50 75 100 125 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE (°C) TEMPERATURE INPUT VOLTAGE (V)
680324 G19 680324 G20

680324fa

7
LTC6803-2/LTC6803-4
TYPICAL PERFORMANCE CHARACTERISTICS
VREF Output Voltage
vs Temperature VREF Load Regulation VREF Line Regulation
3.070 3.09 3.074
NO EXTERNAL LOAD ON VREF, CDC = 2
(CONTINUOUS CELL CONVERSIONS)
3.068 3.072
3.08
3.066 3.070
TA = 25°C
3.064 3.07
3.068
VREF (V)

TA = 85°C

VREF (V)

VREF (V)
TA = 25°C TA = 85°C
3.062 3.066
3.06
TA = –40°C
3.060 TA = –40°C 3.064
3.05
3.058 3.062
5 REPRESENTATIVE UNITS
3.056 3.04 3.060
–50 –25 0 25 50 75 100 125 0 10 100 1000 0 10 20 30 40 50 60
TEMPERATURE (°C) SOURCING CURRENT (µA) SUPPLY VOLTAGE (V)
680324 G21 680324 G22 680324 G23

Internal Discharge Resistance

VREG Load Regulation VREG Line Regulation vs Cell Voltage
5.2 5.5 50
V+ = 43.2V CDC = 2 TA = 105°C
CONTINUOUS CONVERSIONS 45 TA = 85°C
5.0 TA = 25°C
40

DISCHARGE RESISTANCE (Ω)

TA = –45°C
35
4.8 5.0
30
VREG (V)

VREG (V)

4.6 25
20
4.4 4.5
15
TA = 125°C TA = 125°C
TA = 85°C TA = 85°C 10
4.2
TA = 25°C TA = 25°C 5
TA = –40°C TA = –40°C
4.0 4.0 0
0 2 4 6 8 10 12 0 10 20 30 40 50 60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY CURRENT (mA) SUPPLY VOLTAGE (V) CELL VOLTAGE (V)
680324 G26
680324 G24 680324 G25

Die Temperature Increase vs

Discharge Current in Internal FET Cell Conversion Time
50 13.20
ALL 12 CELLS AT 3.6V
45 VS = 43.2V 13.15
INCREASE IN DIE TEMPERATURE (°C)

TA = 25°C
40
13.10
CONVERSION TIME (ms)

35
30 13.05
12 CELLS
25 DISCHARGING 13.00
6 CELLS
20 DISCHARGING
12.95
15 1 CELL
12.90
10 DISCHARGING

5 12.85

0 12.80
0 10 20 30 40 50 60 70 80 –40 –20 0 20 40 60 80 100 120
DISCHARGE CURRENT PER CELL (mA) TEMPERATURE (°C)
680324 G27 680324 G28

680324fa

8
 LTC6803-2/LTC6803-4
PIN FUNCTIONS
To ensure pin compatibility with LTC6802-2, the LTC6803‑2 should be connected in series with the NMOS to dissipate
is configured such that the bottom cell input (C0) is con- heat outside of the LTC6803 package. When using the
nected internally to the negative supply voltage (V–). The internal MOSFETs to discharge cells, the die temperature
LTC6803-4 offers a unique pinout with an input for the should be monitored. See Power Dissipation and Thermal
bottom cell (C0). This simple functional difference offers Shutdown in the Applications Information section. The S
the possibility for enhanced cell 1 measurement accuracy, pins also feature an internal pull-up PMOS. This allows the
enhanced SPI noise tolerance and simplified wiring. More S pins to be used to drive the gates of external MOSFETs
information is provided in the Applications Information for higher discharge capability.
section entitled Advantages of Kelvin Connection for C0.
V– (Pin 26 on LTC6803-2/Pin 27 on LTC6803-4): Connect
V+ (Pin 1): Positive Power Supply. Pin 1 can be tied to the V– to the most negative potential in the series of cells.
most positive potential in the battery stack or an isolated NC (Pin 27 on LTC6803-2/Pin 28 on LTC6803-4): This pin
power supply. V+ must be greater than the most positive is not used and is internally connected to V– through 10Ω.
potential in the battery stack under normal operation. With It can be left unconnected or connected to V– on the PCB.
an isolated power supply, LTC6803 can be turned off by
simply shutting down V+. VTEMP1, VTEMP2 (Pins 28, 29 on LTC6803-2/Pins 29, 30,
on LTC6803-4): Temperature Sensor Inputs. The ADC will
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1
measure the voltage on VTEMPn with respect to V– and store
(Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1 the result in the TMP register. The ADC measurements
through C12 are the inputs for monitoring battery cell are relative to the VREF pin voltage. Therefore a simple
voltages. The negative terminal of the bottom cell should thermistor and resistor combination connected to the
be tied to the V– pin for the LTC6803-2, and the C0 pin for VREF pin can be used to monitor temperature. The VTEMP
the LTC6803-4. The next lowest potential is tied to C1 and inputs can also be general purpose ADC inputs.
so forth. See the figures in the Applications Information
section for more details on connecting batteries to the VREF (Pin 30 on LTC6803-2/Pin 31 on LTC6803-4): 3.065V
LTC6803-2 and LTC6803-4. The LTC6803 can monitor a Voltage Reference Output. This pin should be bypassed
series connection of up to 12 cells. Each cell in a series with a 1µF capacitor. The VREF pin can drive a 100k resis-
connection must have a common mode voltage that is tive load connected to V–. Larger loads should be buffered
greater than or equal to the cells below it. 100mV negative with an LT6003 op amp, or a similar device.
voltages are permitted. VREG (Pin 31 on LTC6803-2/Pin 32 on LTC6803-4): Linear
C0 (Pin 26 on LTC6803-4): Negative Terminal of the Bot- Voltage Regulator Output. This pin should be bypassed with
tom Battery Cell. C0 and V– form a Kelvin connection to a 1µF capacitor. The VREG is capable of sourcing up to 4mA
eliminate effect of voltage drop at the V– trace. to an external load. The VREG pin does not sink current.
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins TOS (Pin 32 on LTC6803-2/Pin 33 on LTC6803-4): Top
3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though of Stack Input. The TOS pin can be tied to VREG or V– for
S12 pins are used to balance battery cells. If one cell in a the LTC6803. The state of the TOS pin alters the operation
series becomes overcharged, an S output can be used to of the SDO pin in the toggle polling mode. See the Serial
discharge the cell. Each S output has an internal N-channel Port description.
MOSFET for discharging. See the Block Diagram. The NMOS NC (Pin 33 on LTC6803-2): No Connection.
has a maximum on-resistance of 20Ω. An external resistor

680324fa

9
LTC6803-2/LTC6803-4
PIN FUNCTIONS
WDTB (Pin 34): Watchdog Timer Output (Active Low). If A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs.
there is no valid command received in 1 to 2.5 seconds, the These pins are tied to VREG or V–. The state of the address
WDTB output is asserted. The WDTB pin is an open-drain pins (VREG = 1, V– = 0) determines the LTC6803 address.
NMOS output. When asserted it pulls the output down to See Address Commands in the Serial Port subsection of
V– and resets the configuration register to its default state. the Applications Information section.
GPIO1, GPIO2 (Pins 35, 36): General Purpose Input/ SCKI (Pin 41): Serial Clock Input. The SCKI pin inter-
Output. By writing a “0” to a GPIO configuration register faces to any logic gate (TTL levels). See Serial Port in the
bit, the open-drain output is activated and the pin is pulled Applications Information section.
to V–. By writing a logic “1” to the configuration register
SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
bit, the corresponding GPIO pin is high impedance. An
any logic gate (TTL levels). See Serial Port in the Applica-
external resistor is required to pull the pin up to VREG.
tions Information section.
By reading the configuration register locations GPIO1
and GPIO2, the state of the pins can be determined. For SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS
example, if a “0” is written to register bit GPIO1, a “0” is open-drain output. A pull-up resistor is needed on SDO.
always read back because the output N-channel MOSFET See Serial Port in the Applications Information section.
pulls Pin 35 to V–. If a “1” is written to register bit GPIO1, CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI
the pin becomes high impedance. Either a “1” or a “0” is pin interfaces to any logic gate (TTL levels). See Serial
read back, depending on the voltage present at Pin 35. Port in the Applications Information section.
The GPIOs makes it possible to turn-on/off circuitry around
the LTC6803-4, or read logic values from a circuit around
the LTC6803-4. The GPIO pins should be connected to
V– if not used.

680324fa

10
 LTC6803-2/LTC6803-4
BLOCK DIAGRAMS
1
LTC6803-2 V+
2nd REFERENCE VREG
VREF2 REGULATOR 31
C12
2

S12 WATCHDOG WDTB

3 34
TIMER

C11
4
A3
40
A2
39
S3 A1
21 38
RESULTS A0
12 37
∆Σ A/D REGISTER
C2 MUX
22 CONVERTER AND CSBI
COMMUNICATIONS 44
SDO
S2 43
23 SDI
42
C1 SCKI
24 41
REFERENCE
S1 GPIO2
25 39

V–
26 GPIO1
CONTROL 38
EXTERNAL
DIE TEMP TOS
32
TEMP
NC VTEMP1 VTEMP2 VREF
27 28 29 30
68032 BD

680324fa

11
LTC6803-2/LTC6803-4
BLOCK DIAGRAMS
1
LTC6803-4 V+
2nd REFERENCE
VREG
VREF2 REGULATOR 32
C12
2

S12 WATCHDOG WDTB

3 34
TIMER

C11
4
A3
40
A2
39
S3 A1
21 38
RESULTS A0
12
∆Σ A/D REGISTER 37
C2 MUX
22 CONVERTER AND CSBI
COMMUNICATIONS 44
SDO
S2 43
23
SDI
42
C1 SCKI
24 41
REFERENCE
GPIO2
S1 36
25

C0
26 GPIO1
CONTROL 35
–
V EXTERNAL
27 TEMP
DIE TOS
TEMP 33
NC VTEMP1 VTEMP2 VREF
28 29 30 31
68033 BD

TIMING DIAGRAM
Timing Diagram of the Serial Interface

t1 t4 t6
t2 t3 t7

SCKI

SDI D3 D2 D1 D0 D7···D4 D3

t5

CSBI

t8

SDO D4 D3 D2 D1 D0 D7···D4 D3
68034 TD
PREVIOUS CURRENT
COMMAND COMMAND

680324fa

12
 LTC6803-2/LTC6803-4
OPERATION
THEORY OF OPERATION The LTC6803 has three modes of operation: hardware
The LTC6803 is a data acquisition IC capable of mea- shutdown, standby and measure. Hardware shutdown is
suring the voltage of 12 series connected battery cells. a true zero power mode. Standby mode is a power saving
An input multiplexer connects the batteries to a 12-bit state where all circuits except the serial interface are turned
delta-sigma analog-to-digital converter (ADC). An internal off. In measure mode, the LTC6803 is used to measure
8ppm/°C voltage reference combined with the ADC give cell voltages and store the results in memory. Measure
the LTC6803 its outstanding measurement accuracy. The mode will also monitor each cell voltage for overvoltage
inherent benefits of the delta-sigma ADC versus other types (OV) and undervoltage (UV) conditions.
of ADCs (e.g., successive approximation) are explained
in Advantages of Delta-Sigma ADCs in the Applications HARDWARE SHUTDOWN MODE
Information section. The V+ pin can be disconnected from the C pins and the
Communication between the LTC6803 and a host processor battery pack. If the V+ supply pin is 0V, the LTC6803 will
is handled by a SPI compatible serial interface. Multiple typically draw less than 1nA from the battery cells. All
LTC6803s can be connected to a single serial interface. circuits inside the IC are off. It is not possible to com-
As shown in Figure 1, the LTC6803-2s or LTC6803-4s municate with the IC when V+ = 0V. See the Applications
are isolated from one another using digital isolators. A Information section for hardware shutdown circuits.
unique addressing scheme allows all the LTC6803-2s or
LTC6803‑4s to connect to the same serial port of the host STANDBY MODE
processor. Further explanation of the LTC6803-2/LTC6803-
4 can be found in the Serial Port section of the data sheet. The LTC6803 defaults (powers up) to standby mode.
Standby mode is the lowest supply current state with a
The LTC6803 also contains circuitry to balance cell voltages. supply connected. Standby current is typically 12µA when
Internal MOSFETs can be used to discharge cells. These V+ = 44V. All circuits are turned off except the serial interface
internal MOSFETs can also be used to control external and the voltage regulator. For the lowest possible standby
balancing circuits. Figure 1 illustrates cell balancing by current consumption, all SPI logic inputs should be set to
internal discharge. Figure 3 shows the S pin controlling logic 1 level. The LTC6803 can be programmed for standby
an external balancing circuit. It is important to note that mode by setting the comparator duty cycle configuration
the LTC6803 makes no decisions about turning on/off bits, CDC[2:0], to 0. If the part is put into standby mode
the internal MOSFETs. This is completely controlled by while ADC measurements are in progress, the measure-
the host processor. The host processor writes values to ments will be interrupted and the cell voltage registers will
a configuration register inside the LTC6803 to control the be in an indeterminate state. To exit standby mode, the CDC
switches. The watchdog timer on the LTC6803 can be used bits must be written to a value other than 0.
to turn off the discharge switches if communication with
the host processor is interrupted. MEASURE MODE
Since the LTC6803-4 separates C0 and V–, C0 can have The LTC6803 is in measure mode when the CDC bits are
higher potential than V–. This feature is very useful for
programmed with a value from 1 to 7. When CDC = 1 the
super capacitors and fuel cells whose voltages can go to
LTC6803 is on and waiting for a start ADC conversion
zero or slightly negative. In such a case, the stacked cells
command. When CDC is 2 through 7 the IC monitors each
can’t power the LTC6803-4. In Figure 1, an isolated 36V
cell voltage and produces an interrupt signal on the SDO
and –3.6V provides power to each LTC6803-4. This allows
pin indicating all cell voltages are within the UV and OV
the C1 to C12 pins to go up to 3.6V below C0.
limits. The value of the CDC bits determines how often
the cells are monitored, and, how much average supply
current is consumed.
680324fa

13
LTC6803-2/LTC6803-4
OPERATION

LTC6803-4 V2 – V1– LTC6803-4 V2 – V1–

IC #1 OE2 OE1 IC #7 OE2 OE1
+ CSBI + CSBI
V V
C12 SDO C12 SDO
+ S12 SDI
+ S12 SDI
C11 SCKI C11 SCKI
+ S11 A3
+ S11 A3
ADDRESS1 V2 – V1– ADDRESS7 V2 – V1–
C10 A2 C10 A2
+ S10 A1 V2 + V1+ 3V + S10 A1 V2 + V1+ 3V
DIGITAL DIGITAL
C9 A0 C9 A0
+ S9 GPIO2
ISOLATOR + S9 GPIO2
ISOLATOR
C8 GPIO1 C8 GPIO1
+ S8 WDTB
+ S8 WDTB
C7 TOS C7 TOS
+ S7 VREG
+ S7 VREG
C6 VREF C6 VREF
+ S6 VTEMP2
+ S6 VTEMP2
C5 VTEMP1 C5 VTEMP1

+ S5 NC
+ S5 NC
C4 V– C4 V–
+ S4 C0
+ S4 C0
ISOLATED 12V ISOLATED 12V
C3 S1 C3 S1
+ S3 C1
DC/DC + S3 C1
DC/DC
CONVERTER CONVERTER
C2 S2 C2 S2
+ 680324 F01

+ +
3V
LTC6803-4 V2 – V1–
IC #0 OE2 OE1 MPU MODULE
V+ CSBI MISO
IO
C12 SDO CS
+ S12 SDI M0SI
C11 SCKI
+ S11 A3 CLK
– –
ADDRESS0 V2 V1
C10 A2
+ S10 A1 V2 + V1+ 3V
DIGITAL
C9 A0
+ S9 GPIO2
ISOLATOR
C8 GPIO1
+ S8 WDTB
C7 TOS
+ S7 VREG
C6 VREF
+ S6 VTEMP2
C5 VTEMP1

+ S5 NC
C4 V–
+ S4 C0
ISOLATED 12V
C3 S1
+ S3 C1
DC/DC
CONVERTER
C2 S2
+
+

Figure 1. Simplified 96-Cell Battery or Supercapacitor, Isolated Interface. In this Diagram the Battery
Negative is Isolated from the Module Ground. Isolated Power Supplies Each LTC6803-4. Opto-Couplers
or Digital Isolators Allow Each IC to Be Addressed Individually

680324fa

14
 LTC6803-2/LTC6803-4
OPERATION
There are two methods for indicating the UV/OV inter- ADC RANGE AND OUTPUT FORMAT
rupt status: toggle polling (using a 1kHz output signal)
The ADC outputs a 12-bit code with an offset of 0x200
and level polling (using a high or low output signal). The
(512 decimal). The input voltage can be calculated as:
polling methods are described in the Serial Port section.
The UV/OV limits are set by the VUV and VOV values in the VIN = (DOUT – 512) • VLSB; VLSB = 1.5mV
configuration registers. When a cell voltage exceeds the where DOUT is a decimal integer.
UV/OV limits a bit is set in the flag register. The UV and
OV flag status for each cell can be determined using the For example, a 0V input will have an output reading of 0x200.
Read Flag Register Group. An ADC reading of 0x000 means the input was –0.768V. The
absolute ADC measurement range is –0.768V to 5.376V.
An ADC measurement can be requested at any time when The resolution is VLSB = 1.5mV = (5.376 + 0.768)/212. The
the IC is in measure mode. To initiate cell voltage measure- useful range is –0.3V to 5V. This range allows monitoring
ments while in measure mode, a Start A/D Conversion supercapacitors which could have small negative voltage.
command is sent. After the command has been sent, the Inputs below –0.3V exceed the absolute maximum rating
LTC6803 will indicate the A/D converter status via toggle of the C pins. If all inputs are negative, the ADC range is
polling or level polling (as described in the Serial Port reduced to –0.1V. Inputs above 5V will have noisy ADC
section). During cell voltage measurement commands, readings (see Typical Performance Characteristics).
the UV and OV flags (within the flag register group) are
also updated. When the measurements are complete, the
ADC MEASUREMENTS DURING CELL BALANCING
part will continue monitoring UV and OV conditions at
the rate designated by the CDC bits. Note that there is a The primary cell voltage ADC measurement commands
5µs window during each UV/OV comparison cycle where (STCVAD and STOWAD) automatically turn off a cell’s
an ADC measurement request may be missed. This is discharge switch while its voltage is being measured. The
an unlikely event. For example, the comparison cycle is discharge switches for the cell above and the cell below will
2 seconds when CDC = 7. Use the CLEAR command to also be turned off during the measurement. For example,
detect missing ADC commands. discharge switches S4, S5 and S6 will be off while cell 5
is being measured. The UV/OV comparison conversions in
Operating with Less than 12 Cells CDC modes 2 through 7 also cause a momentary turn-off
If fewer than 12 cells are connected to the LTC6803, the of the discharge switch. For example, switches S4, S5 and
unused input channels must be masked. The MCxI bits in S6 will be off while cell 5 is checked for a UV/OV condition.
the configuration registers are used to mask channels. In In some systems it may be desirable to allow discharging to
addition, the LTC6803 can be configured to automatically continue during cell voltage measurements. The cell voltage
bypass the measurements of the top 2 cells, reducing power ADC conversion commands STCVDC and STOWDC allow
consumption and measurement time. If the CELL10 bit is the discharge switches to remain on during cell voltage
high, the inputs for cell 11 and cell 12 are masked and only measurements. This feature allows the system to perform
the bottom 10-cell voltages will be measured. By default, a self test to verify the discharge functionality.
the CELL10 bit is low, enabling measurement of all 12-cell
voltages. Additional information regarding operation with
less than 12 cells is provided in the applications section.

680324fa

15
LTC6803-2/LTC6803-4
OPERATION
ADC REGISTER CLEAR COMMAND USING THE GENERAL PURPOSE INPUTS/OUTPUTS
The clear command can be used to clear the cell voltage (GPIO1, GPIO2)
registers and temperature registers. The clear command The LTC6803 has two general purpose digital input/output
will set all registers to 0xFFF. This command is used to pins. By writing a GPIO configuration register bit to a logic
make sure conversions are being made. When cell volt- low, the open-drain output can be activated. The GPIOs
ages are stable, ADC results could stay the same. If a start give the user the ability to turn on/off circuitry around
ADC conversion command is sent to the LTC6803 but the the LTC6803. One example might be a circuit to verify the
PEC fails to match then the command is ignored and the operation of the system.
voltage register contents also will not change. Sending a
When a GPIO configuration bit is written to a logic high,
clear command then reading back register contents is a
the corresponding GPIO pin may be used as an input.
way to make sure LTC6803 is accepting commands and
The read back value of that bit will be the logic level that
performing new measurements. The clear command takes
appears at the GPIO pins.
1ms to execute.

WATCHDOG TIMER CIRCUIT

ADC CONVERTER SELF TEST
The LTC6803 includes a watchdog timer circuit. The
Two self-test commands can be used to verify the func-
watchdog timer is on for all modes except CDC = 0. The
tionality of the digital portions of the ADC. The self tests
watchdog timer times out if no valid command is received
also verify the cell voltage registers and temperature
for 1 to 2.5 seconds. When the watchdog timer circuit
monitoring registers. During these self tests a test signal
times out, the WDTB open-drain output is asserted low
is applied to the ADC. If the circuitry is working properly all
and the configuration register bits are reset to their default
cell voltage and temperature registers will contain 0x555
(power-up) state. In the power-up state, CDC is 0, the S
or 0xAAA. The time required for the self-test function is
outputs are off and the IC is in the low power standby
the same as required to measure all cell voltages or all
mode. The WDTB pin remains low until a valid command
temperature sensors.
is received. The watchdog timer provides a means to turn
off cell discharging should communications to the MPU
MULTIPLEXER AND REFERENCE SELF TEST be interrupted. There is no need for the watchdog timer
The LTC6803 uses a multiplexer to measure the 12 bat- at CDC = 0 since discharging is off. The open-drain WDTB
tery cell inputs as well as the temperature signals. A output can be wire ORd with other external open-drain
diagnostic command is used to validate the function of signals. Pulling the WDTB signal low will not initiate a
the multiplexer, the temperature sensor, and the precision watchdog event, but the CNFGO bit 7 will reflect the state
reference circuit. Diagnostic registers will be updated after of this signal. Therefore, the WDTB pin can be used to
each diagnostic test. The muxfail bit of the registers will monitor external digital events if desired.
be 1 if the multiplexer self test fails.
A constant voltage generated by the 2nd reference circuit SERIAL PORT
will be measured by the ADC and the results written to the
Overview
diagnostic register. The voltage reading should be 2.5V
±16%. Readings outside this range indicate a failure of The LTC6803-2/LTC6803-4 has an SPI bus compatible
the temperature sensor circuit, the precision reference serial port. Devices can be connected in parallel, using
circuit, or the analog portion of the ADC. The DAGN com- digital isolators. Multiple devices are uniquely identified by
mand executes in 16.4ms, which is the sum of the 12-cell a part address determined by the A0 to A3 pins. Physical
tCYCLE and the 3 temperature tCYCLE. The diagnostic read Layer on the LTC6803-2/LTC6803-4, four pins comprise
command can be used to read the registers. the serial interface: CSBI, SCKI, SDI and SDO. The SDO
680324fa

16
 LTC6803-2/LTC6803-4
OPERATION
and SDI may be tied together, if desired, to form a single, Network Layer
bi-directional port. Four address pins (A0 to A3) set the
PEC Byte: The packet error code (PEC) byte is a cyclic
part address for address commands. The TOS pin desig-
redundancy check (CRC) value calculated for all of the
nates the top device (logic high) for polling commands.
bits in a register group in the order they are passed, us-
All interface pins are voltage mode, with voltage levels
ing the initial PEC value of 01000001 and the following
sensed with respect to the V– supply. See Figure 1.
characteristic polynomial:
Data Link Layer x8 + x2 + x + 1
Clock Phase And Polarity: The LTC6803 SPI compat- To calculate the 8-bit PEC value, a simple procedure can
ible interface is configured to operate in a system using be established:
CPHA = 1 and CPOL = 1. Consequently, data on SDI must 1. Initialize the PEC to 0100 0001.
be stable during the rising edge of SCKI.
2. For each bit DIN coming into the register group, set IN0
Data Transfers: Every byte consists of 8 bits. Bytes are = DIN XOR PEC[7], then IN1 = PEC[0] XOR IN0, IN2 =
transferred with the most significant bit (MSB) first. On a PEC[1] XOR IN0.
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 2). Similarly, on a read, the 3. Update the 8-bit PEC as PEC[7] = PEC[6], PEC[6] =
data value output on SDO is valid during the rising edge of PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2, PEC[1]
SCKI and transitions on the falling edge of SCKI (Figure 3). = IN1, PEC[0] = IN0.
CSBI must remain low for the entire duration of a com- 4. Go back to step 2 until all data are shifted. The 8-bit
mand sequence, including between a command byte and result is the final PEC byte.
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.

CSBI

SCKI

SDI MSB (CMD) BIT 6 (CMD) LSB (CMD) MSB (DATA) LSB (DATA)
68034 F02

Figure 2. Transmission Format (Write)

CSBI

SCKI

SDI MSB (CMD) BIT 6 (CMD) LSB (CMD)

SDO MSB (DATA) LSB (DATA)

68034 F03

Figure 3. Transmission Format (Read)

680324fa

17
LTC6803-2/LTC6803-4
OPERATION
An example to calculate the PEC is listed in Table 1 and value of 1000 and 4 address bits. Following the address
Figure 4. The PEC of the 1 byte data 0x01 is computed as command is its PEC byte. The third and fourth bytes are
0xC7 after the last bit of the byte streamed in. For multiple the command byte and its PEC byte respectively. See the
byte data, PEC is valid at the end (LSB) of the last byte. Bus Protocols and Commands section.
LTC6803 calculates PEC byte for any command or data Polling Methods: For ADC conversions, three methods can
received and compares it with the PEC byte following the be used to determine ADC completion. First, a controller
command or data. The command or data is regarded as can start an ADC conversion and wait for the specified
valid only if the PEC bytes match. LTC6803 also attaches conversion time to pass before reading the results. The
the calculated PEC byte at the end of the data it shifts out. second method is to hold CSBI low after an ADC start
command has been sent. The ADC conversion status will
Broadcast Commands: A broadcast command is one to
be output on SDO (Figure 5). A problem with the second
which all devices on the bus will respond, regardless of
method is that the controller is not free to do other serial
device address. See the Bus Protocols and Commands
communication while waiting for ADC conversions to
sections. With broadcast commands all devices can be
complete. The third method overcomes this limitation.
sent commands simultaneously. This is useful for ADC
The controller can send an ADC start command, perform
conversion and polling commands. It can also be used
other tasks, and then send a poll ADC converter status
with write commands when all parts are being written with
(PLADC) command to determine the status of the ADC
the same data. Broadcast read commands should not be
conversions (Figure 6). For OV/UV interrupt status, the poll
used in the parallel configuration.
interrupt status (PLINT) command can be used to quickly
Address Commands: An address command is one in which determine whether any cell in a stack is in an overvoltage
only the addressed device on the bus responds. The first or undervoltage condition (Figure 6).
byte of an address command consists of 4 bits with a

Table 1. Procedure to Calculate PEC Byte

CLOCK
CYCLE DIN IN0 IN1 IN2 PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0]
0 0 0 1 0 0 1 0 0 0 0 0 1
1 0 1 1 0 1 0 0 0 0 0 1 0
2 0 0 1 1 0 0 0 0 0 0 1 1
3 0 0 0 1 0 0 0 0 0 1 1 0
4 0 0 0 0 0 0 0 0 1 1 0 0
5 0 0 0 0 0 0 0 1 1 0 0 0
6 0 0 0 0 0 0 1 1 0 0 0 0
7 1 1 1 1 0 1 1 0 0 0 0 0
8 1 1 0 0 0 1 1 1

680324fa

18
 OPERATION

XOR 2 PEC1 = PEC[0] XOR IN0; 3 PEC2 = PEC[1] XOR IN0; 4 PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
PEC[7] IN0 PEC[7]
END
DATAIN XOR
XOR IN0 PEC[2] PEC[3] PEC[4] PEC[5] PEC[6] PEC[7]
INO PEC[1] PEC2 PEC[2] PEC[3] PEC[4] PEC[5] PEC[6]
PEC[0] PEC1 D Q D Q D Q D Q D Q D Q
D Q
1 INO = DATAIN XOR PEC[7]; D Q
PEC[1] CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q
PEC[0] CLK Q
BEGIN PEC[7:0] = 0x41 CLK Q DTFF DTFF DTFF DTFF DTFF DTFF
DTFF
DTFF
680324 F04
CLOCK

PEC Hardware and Software Example

BEGIN PEC[7:0] = 0x41

1 INO = DATAIN XOR PEC[7];

2 PEC1 = PEC[0] XOR IN0;

3 PEC2 = PEC[1] XOR IN0;

4 PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};

END

Figure 4

19
680324fa
LTC6803-2/LTC6803-4
LTC6803-2/LTC6803-4
OPERATION
tCYCLE
CSBI

SCKI

SDI MSB (CMD) BIT6 (CMD) LSB (PEC)

680324 F05
SDO TOGGLE OR LEVEL POLL

Figure 5. Transmission Format (ADC Conversion and Poll)

CSBI

SCKI

SDI MSB (CMD) BIT6 (CMD) LSB (PEC)

680324 F06
SDO TOGGLE OR LEVEL POLL

Figure 6. Transmission Format (PLADC Conversion or PLINT)

Toggle Polling: Toggle polling allows a robust determina- Level Polling: Level polling is enabled when the LVLPL
tion both of device states and of the integrity of the con- bit is high. After entering a polling command, the data
nections between the devices in a stack. Toggle polling is out line will be driven by the slave devices based on their
enabled when the LVLPL bit is low. After entering a polling status. When polling for the ADC converter status, data
command, the data out line will be driven by the slave out will be low when any device is busy performing an
devices based on their status. When polling for the ADC ADC conversion and will be high when no device is busy.
converter status, data out will be low when any device is Similarly, when polling for interrupt status, the output will
busy performing an ADC conversion and will toggle at be low when any device has an interrupt condition and will
1kHz when no device is busy. Similarly, when polling for be high when none has an interrupt condition.
interrupt status, the output will be low when any device Level Polling—Address Polling: The addressed device
has an interrupt condition and will toggle at 1kHz when drives the SDO line based on its state alone—pulled low
none has an interrupt condition. for busy/in interrupt, released for not busy/not in interrupt.
Toggle Polling—Address Polling: The addressed device Level polling—Parallel Broadcast Polling: No part address
drives the SDO line based on its state alone—low for busy/ is sent, so all devices respond simultaneously. If a device
in interrupt, toggling at 1kHz for not busy/not in interrupt. is busy/in interrupt, it will pull SDO low. If a device is not
Toggle Polling—Parallel Broadcast Polling: No part ad- busy/not in interrupt, then it will release the SDO line. If
dress is sent, so all devices respond simultaneously. If a any device is busy or in interrupt the SDO signal will be
device is busy/in interrupt, it will pull SDO low. If a device low. If all devices are not busy/not in interrupt, the SDO
is not busy/not in interrupt, then it will release the SDO line signal will be high. The master controller pulls CSBI high
(TOS = 0) or attempt to toggle the SDO line at 1kHz (TOS to exit polling.
= 1).The master controller pulls CSBI high to exit polling.
680324fa

20
 LTC6803-2/LTC6803-4
OPERATION
Revision Code Bus Protocols
The diagnostic register group contains a 2-bit revision There are 6 different protocol formats, depicted in Table 3
code. If software detection of device revision is neces- through Table 8. Table 2 is the key for reading the protocol
sary, then contact the factory for details. Otherwise, the diagrams.
code can be ignored. In all cases, however, the values of
all bits must be used when calculating the packet error
code (PEC) byte on data reads.

Table 2. Protocol Key

PEC Packet Error Code Master-to-Slave

N Number of Bits Slave-to-Master

... Continuation of Protocol Complete Byte of

Data

Table 3. Broadcast Poll Command

8 8
Command PEC Poll Data

Table 4. Broadcast Read

8 8 8 … 8 8
Command PEC Data Byte Low … Data Byte High PEC
A bus collision will occur if multiple devices are on the same serial bus.

Table 5. Broadcast Write

8 8 8 … 8 8
Command PEC Data Byte Low … Data Byte High PEC

Table 6. Address Poll Command

4 4 8 8 8
1000 Address PEC Command PEC Poll Data

Table 7. Address Read

4 4 8 8 8 8 … 8 8
1000 Address PEC Command PEC Data Byte Low … Data Byte High PEC
See Serial Command examples

Table 8. Address Write

4 4 8 8 8 8 … 8 8
1000 Address PEC Command PEC Data Byte Low … Data Byte High PEC

680324fa

21
LTC6803-2/LTC6803-4
OPERATION
Commands
Table 9. Command Codes and PEC Bytes
COMMAND DESCRIPTION NAME CODE PEC
Write Configuration Register Group WRCFG 01 C7
Read Configuration Register Group RDCFG 02 CE
Read All Cell Voltage Group RDCV 04 DC
Read Cell Voltages 1-4 RDCVA 06 D2
Read Cell Voltages 5-8 RDCVB 08 F8
Read Cell Voltages 9-12 RDCVC 0A F6
Read Flag Register Group RDFLG 0C E4
Read Temperature Register Group RDTMP 0E EA
Start Cell Voltage ADC Conversions and Poll Status STCVAD All 10 B0
Cell 1 11 B7
Cell 2 12 BE
Cell 3 13 B9
Cell 4 14 AC
Cell 5 15 AB
Cell 6 16 A2
Cell 7 17 A5
Cell 8 18 88
Cell 9 19 8F
Cell 10 1A 86
Cell 11 1B 81
Cell 12 1C 94
Clear (FF) 1D 93
Self Test1 1E 9A
Self Test2 1F 9D
Start Open-Wire ADC Conversions and Poll Status STOWAD All 20 20
Cell 1 21 27
Cell 2 22 2E
Cell 3 23 29
Cell 4 24 3C
Cell 5 25 3B
Cell 6 26 32
Cell 7 27 35
Cell 8 28 18
Cell 9 29 1F
Cell 10 2A 16
Cell 11 2B 11
Cell 12 2C 4
Start Temperature ADC Conversions and Poll Status STTMPAD All 30 50
External1 31 57
External2 32 5E
Internal 33 59
Self Test 1 3E 7A
Self Test 2 3F 7D
Poll ADC Converter Status PLADC 40 07
Poll Interrupt Status PLINT 50 77
Start Diagnose and Poll Status DAGN 52 79
Read Diagnostic Register RDDGNR 54 6B

680324fa

22
 LTC6803-2/LTC6803-4
OPERATION
Table 9. Command Codes and PEC Bytes (continued)
COMMAND DESCRIPTION NAME CODE PEC
Start Cell Voltage ADC Conversions and Poll Status, STCVDC All 60 E7
with Discharge Permitted Cell 1 61 E0
Cell 2 62 E9
Cell 3 63 EE
Cell 4 64 FB
Cell 5 65 FC
Cell 6 66 F5
Cell 7 67 F2
Cell 8 68 DF
Cell 9 69 D8
Cell 10 6A D1
Cell 11 6B D6
Cell 12 6C C3
Start Open-Wire ADC Conversions and Poll Status, STOWDC All 70 97
with Discharge Permitted Cell 1 71 90
Cell 2 72 99
Cell 3 73 9E
Cell 4 74 8B
Cell 5 75 8C
Cell 6 76 85
Cell 7 77 82
Cell 8 78 AF
Cell 9 79 A8
Cell 10 7A A1
Cell 11 7B A6
Cell 12 7C B3

Table 10. Configuration (CFG) Register Group

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CFGR0 RD/WR WDT GPIO2 GPIO1 LVLPL CELL10 CDC[2] CDC[1] CDC[0]
CFGR1 RD/WR DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1
CFGR2 RD/WR MC4I MC3I MC2I MC1I DCC12 DCC11 DCC10 DCC9
CFGR3 RD/WR MC12I MC11I MC10I MC9I MC8I MC7I MC6I MC5I
CFGR4 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[0]
CFGR5 RD/WR VOV[7] VOV[6] VOV[5] VOV[4] VOV[3] VOV[2] VOV[1] VOV[0]

680324fa

23
LTC6803-2/LTC6803-4
OPERATION
Table 11. Cell Voltage (CV) Register Group
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVR00 RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0]
CVR01 RD C2V[3] C2V[2] C2V[1] C2V[0] C1V[11] C1V[10] C1V[9] C1V[8]
CVR02 RD C2V[11] C2V[10] C2V[9] C2V[8] C2V[7] C2V[6] C2V[5] C2V[4]
CVR03 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[0]
CVR04 RD C4V[3] C4V[2] C4V[1] C4V[0] C3V[11] C3V[10] C3V[9] C3V[8]
CVR05 RD C4V[11] C4V[10] C4V[9] C4V[8] C4V[7] C4V[6] C4V[5] C4V[4]
CVR06 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[0]
CVR07 RD C6V[3] C6V[2] C6V[1] C6V[0] C5V[11] C5V[10] C5V[9] C5V[8]
CVR08 RD C6V[11] C6V[10] C6V[9] C6V[8] C6V[7] C6V[6] C6V[5] C6V[4]
CVR09 RD C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[0]
CVR10 RD C8V[3] C8V[2] C8V[1] C8V[0] C7V[11] C7V[10] C7V[9] C7V[8]
CVR11 RD C8V[11] C8V[10] C8V[9] C8V[8] C8V[7] C8V[6] C8V[5] C8V[4]
CVR12 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[0]
CVR13 RD C10V[3] C10V[2] C10V[1] C10V[0] C9V[11] C9V[10] C9V[9] C9V[8]
CVR14 RD C10V[11] C10V[10] C10V[9] C10V[8] C10V[7] C10V[6] C10V[5] C10V[4]
CVR15* RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[0]
CVR16* RD C12V[3] C12V[2] C12V[1] C12V[0] C11V[11] C11V[10] C11V[9] C11V[8]
CVR17* RD C12V[11] C12V[10] C12V[9] C12V[8] C12V[7] C12V[6] C12V[5] C12V[4]
*Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low

Table 12. Flag (FLG) Register Group

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FLGR0 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV
FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV
FLGR2 RD C12OV* C12UV* C11OV* C11UV* C10OV C10UV C9OV C9UV
* Bits C11UV, C12UV, C11OV and C12OV are always low if the CELL10 bit in register CFGR0 is high

Table 13. Temperature (TMP) Register Group

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TMPR0 RD ETMP1[7] ETMP1[6] ETMP1[5] ETMP1[4] ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[0]
TMPR1 RD ETMP2[3] ETMP2[2] ETMP2[1] ETMP2[0] ETMP1[11] ETMP1[10] ETMP1[9] ETMP1[8]
TMPR2 RD ETMP2[11] ETMP2[10] ETMP2[9] ETMP2[8] ETMP2[7] ETMP2[6] ETMP2[5] ETMP2[4]
TMPR3 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[0]
TMPR4 RD NA NA NA THSD ITMP[11] ITMP[10] ITMP[9] ITMP[8]

Table 14. Packet Error Code (PEC)

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PEC RD PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0]

Table 15. Diagnostic Register Group

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DGNR0 RD REF[7] REF[6] REF[5] REF[4] REF[3] REF[2] REF[1] REF[0]
DGNR1 RD REV[1] REV[0] MUXFAIL NA REF[11] REF[10] REF[9] REF[8]
680324fa

24
 LTC6803-2/LTC6803-4
OPERATION
Table 16. Memory Bit Descriptions
NAME DESCRIPTION VALUES
UV/OV COMPARATOR VREF POWERED DOWN CELL VOLTAGE
CDC PERIOD BETWEEN MEASUREMENTS MEASUREMENT TIME
0 N/A (Comparator Off)
Yes N/A
(Default) Standby Mode
1 N/A (Comparator Off) No 13ms

CDC Comparator Duty Cycle 2 13ms No 13ms

3 130ms No 13ms
4 500ms No 13ms
5 130ms Yes 21ms
6 500ms Yes 21ms
7 2000ms Yes 21ms
CELL10 10-Cell Mode 0 = 12-cell mode (default); 1 = 10-cell mode
LVLPL Level Polling Mode 0 = toggle polling (default); 1 = level polling
Write: 0 = GPIO1 pin pull-down on; 1 = GPIO1 pin pull-down off (default)
GPIO1 GPIO1 Pin Control
Read: 0 = GPIO1 pin at logic ‘0’; 1 = GPIO1 pin at logic ‘1’
Write: 0 = GPIO2 pin pull-down on; 1 = GPIO2 pin pull-down off (default)
GPIO2 GPIO2 Pin Control
Read: 0 = GPIO2 pin at logic ‘0’; 1 = GPIO2 pin at logic ‘1’
WDT Watchdog Timer Read: 0 = WDTB pin at logic ‘0’; 1 = WDTB pin at logic ‘1’
DCCx Discharge Cell x x = 1..12 0 = turn off shorting switch for cell ‘x’ (default); 1 = turn on shorting switch
VUV Undervoltage Comparison Voltage* Comparison voltage = (VUV –31) • 16 • 1.5mV (Default VUV = 0)
VOV Overvoltage Comparison Voltage* Comparison voltage = (VOV –32) • 16 • 1.5mV (Default VOV = 0)
x = 1..12 0 = enable interrupts for cell ‘x’ (default)
MCxI Mask Cell x Interrupts
1 = turn off interrupts and clear flags for cell ‘x’
x = 1..12 12-bit ADC measurement value for cell ‘x’
CxV Cell x Voltage* cell voltage for cell ‘x’ = (CxV –512) • 1.5mV
reads as 0xFFF while A/D conversion in progress
x = 1..12 cell voltage compared to VUV comparison voltage
CxUV Cell x Undervoltage Flag
0 = cell ‘x’ not flagged for undervoltage condition; 1 = cell ‘x’ flagged
x = 1..12 cell voltage compared to VOV comparison voltage
CxOV Cell x Overvoltage Flag
0 = cell ‘x’ not flagged for overvoltage condition; 1 = cell ‘x’ flagged
ETMPx External Temperature Measurement* Temperature measurement voltage = (ETMPx –512) • 1.5mV
0 = thermal shutdown has not occurred; 1 = thermal shutdown has occurred
THSD Thermal Shutdown Status
Status cleared to ‘0’ on read of Thermal Register Group
REV Revision Code Device revision code
ITMP Internal Temperature Measurement* Temperature measurement voltage = (ITMP –512) • 1.5mV = 8mV • T(°K)
PEC Packet Error Code Cyclic redundancy check (CRC) value
REF Reference Voltage for Diagnostics This reference voltage = (REF –512) • 1.5mV. Normal range is within 2.1V to 2.9V
*Voltage equations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers

680324fa

25
LTC6803-2/LTC6803-4
OPERATION
SERIAL COMMAND EXAMPLES
LTC6803-2/LTC6803-4 (Addressable Configuration)
Examples below use a configuration of three stacked devices: bottom (B), middle (M), and top (T)
Write Configuration Registers (Figure 7) (Broadcast Write)
1. Pull CSBI low
2. Send WRCFG command and its PEC byte
3. Send CFGR0 byte, then CFGR1, …CFGR5, PEC byte (All devices on the bus receive the same data)
4. Pull CSBI high; data latched into all devices on rising edge of CSBI. S pins respond as data latched
Calculation of serial interface time for sequence above:
Number of devices in stack = N
Number of bytes in sequence = B = 2 command byte and 7 data bytes = 2 + 7
Serial port frequency per bit = F
Time = (1/F) * B * 8 bits/byte = (1/F) * (2 + 7) * 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) * (2 + 7)*8 = 72µs
Read Cell Voltage Registers (12 battery cells, addressable read)
1. Pull CSBI low
2. Send Address and PEC byte for bottom device
3. Send RDCV command and its PEC byte
4. Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B)
5. Pull CSBI high
6. Repeat steps 1-5 for middle device and top device
Calculation of serial interface time for sequence above:
Number of devices in stack = N
Number of bytes in sequence = B = 2 address bytes, 2 command bytes, and 18 data bytes plus 1 PEC byte = 23 * N
Serial port frequency per bit = F
Time = (1/F) * B * 8 bits/byte = (1/F) * (23 * N) * 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) * (23 * N) * 8 = 552µs

680324fa

26
 LTC6803-2/LTC6803-4
OPERATION
Start Cell Voltage ADC Conversions and Poll Status (Broadcast Command with Toggle Polling)
1. Pull CSBI low
2. Send STCVAD command and its PEC byte (all devices in stack start ADC conversions simultaneously)
3. SDO output of all devices in parallel pulled low for approximately 12ms
4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices
5. Pull CSBI high to exit polling
Poll Interrupt Status (Level Polling)
1. Pull CSBI low
2. Send Address and PEC bytes for bottom device
3. Send PLINT command and PEC bytes
4. SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high
5. Pull CSBI high to exit polling
6. Repeat steps 1-5 for middle device and top device

CSBI

SCKI

SDI WRCFG + CFGR + PEC

td td < 2µs IF Sn IS UNLOADED

Sn Sn, DISCHARGE PIN STATE

(n = 1 TO 12)
680324 F07

Figure 7. S Pin Action and SPI Transmission

680324fa

27
LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
DIFFERENCE BETWEEN THE LTC6803-2 AND LTC6803‑4 Larger series resistors and shunt capacitors can be used
The only difference between the LTC6803-2 and the to lower the filter bandwidth. The measurement error due
LTC6803-4 is the bonding of the V–­ and C0 pins. The to the larger component values is a complex function of
V– and C0 are separate signals on every LTC6803 die. the component values. The error also depends on how
In the LTC6803-2 package, the V– and C0 signals are often measurements are made. Table 17 is an example. In
shorted together by bonding these signals to the same each example a 3.6V cell is being measured and the error
pin. In the LTC6803‑4 package, V– and C0 are separate is displayed in millivolts. There is a RC filter in series with
pins. Therefore, the LTC6803-2 is pin compatible with the inputs C1 through C12. There is no filter in series with
LTC6802-2. For new designs the LTC6803-4 pinout allows C0. There is an interaction between cells. This is why the
a Kelvin connection to C0 (Figure 22). errors for C1 and C12 differ from C2 through C11.
Table 17. Cell Measurement Errors vs Input RC Values
CELL VOLTAGE FILTERING R = 100Ω, R = 1k, R = 1k, R = 10k,
C = 0.1µF C = 0.1µF C = 1µF C = 3.3µF
The LTC6803 employs a sampling system to perform its Cell 1 Error 0.1 4.5 1.5 1.5
analog-to-digital conversions and provides a conversion (mV, LTC6803-2)
result that is essentially an average over the 0.5ms con- Cell 2 to Cell 12 (mV) 1 9 3 0.5
version window, provided there isn’t noise aliasing with For the LTC6803-2, no resistor should be placed in series
respect to the delta-sigma modulator rate of 512kHz. This with the V– pin. Because the supply current flows from
indicates that a lowpass filter with 30dB attenuation at the V– pin, any resistance on this pin could generate a
500kHz may be beneficial. Since the delta-sigma integra- significant conversion error for cell 1, and the error of
tion bandwidth is about 1kHz, the filter corner need not cell 1 caused by the RC filter differs from errors of cell 2
be lower than this to assure accurate conversions. to cell 2.
Series resistors of 100Ω may be inserted in the input OPEN-CONNECTION DETECTION
paths without introducing meaningful measurement er-
ror. Shunt capacitors may be added from the cell inputs When a cell input (C pin) is open, it affects two cell mea-
to V–, creating RC filtering as shown in Figure 8. The cell surements. Figure 9 shows an open connection to C3,
balancing MOSFET in Figure 11 can cause a small transient in an application without external filtering between the C
when it switches on and off. Keeping the cutoff frequency pins and the cells. During normal ADC conversions (that
of the RC filter relatively high will allow adequate settling is, using the STCVAD command), the LTC6803 will give
prior to the actual conversion. A delay of about 500µs is near zero readings for B3 and B4 when C3 is open. The
provided in the ADC timing, so a 16kHz LPF is optimal zero reading for B3 occurs because during the measure-
(100Ω, 0.1µF) and offers about 30dB of noise rejection. ment of B3, the ADC input resistance will pull C3 to the
C2 potential. Similarly, during the measurement of B4, the
ADC input resistance pulls C3 to the C4 potential.
100Ω
Cn
100nF
Figure 10 shows an open connection at the same point in
+
7.5V the cell stack as Figure 9, but this time there is an external
100Ω
C(n – 1)
filtering network still connected to C3. Depending on the
100nF
680324 F08
value of the capacitor remaining on C3, a normal measure-
ment of B3 and B4 may not give near-zero readings, since
the C3 pin is not truly open. In fact, with a large external
Figure 8. Adding RC Filtering to the Cell Inputs capacitance on C3, the C3 voltage will be charged midway
(One Cell Connection Shown)

680324fa

28
 LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
increase the B4 measurement result relative to the normal
+ STCVAD command. The biggest change is observed in the
LTC6803-4
+ 18
C4 B4 measurement when C3 is open. So, the best method to
B4
C3 detect an open wire at input C3 is to look for an increase
+ 20
B3 in the value of battery connected between inputs C3 and
C2
+ 22 MUX C4 (battery B4).
C1
+ 24 The following algorithm can be used to detect an open
1
V–
100µA
connection to cell pin Cn:
1. Issue a STOWAD command (with 100µA sources
connected).
680324 F09

2. Issue a RDCV command and store all cell measurements

Figure 9. Open Connection
into array CELLA(n).
3. Issue the 2nd STOWAD command (with 100µA sources
+ connected).
C4 LTC6803-4
+ 18
4. Issue the 2nd RDCV command and store all cell mea-
B4 CF4
20
C3 surements into array CELLB(n).
+
5. For battery cells, if CELLA(1) < 0 or CELLB(1) < 0, V–
B3 CF3
C2
22 MUX
+ must be open.
C1
+ 24
If CELLA(12) < 0 or CELLB(12) < 0, C12 must be open.
V–
1 100µA For n = 2 to 11, if CELLB(n+1) – CELLA(n+1) > 200mV,
or CELLB(n+1) reaches the full scale of 5.375V, then
Cn is open.
680324 F10

Figure 10. Open Connection with RC Filtering

The 200mV threshold is chosen to provide tolerance for
measurement errors. For a system with the capacitor con-
between C2 and C4 after several cycles of measuring cells nected to Cn larger than 0.5µF, repeating step 3 several
B3 and B4. Thus the measurements for B3 and B4 may times will discharge the external capacitor enough to meet
indicate a valid cell voltage when in fact the exact state of the criteria.
B3 and B4 is unknown. If the top C pin is open yet V+ is still connected, then the
To reliably detect an open connection, the command best way to detect an open connection to the top C pin
STOWAD is provided. With this command, two 100µA is by comparing the sum of all cell measurements using
current sources are connected to the ADC inputs and the STCVAD command to an auxiliary measurement of
turned on during all cell conversions. Referring again to the sum of all the cells, using a method similar to that
Figure 10, with the STOWAD command, the C3 pin will be shown in Figure 19. A significantly lower result for the
pulled down by the 100µA current source during the B3 sum of all 12 cells suggests an open connection to the
cell measurement AND during the B4 cell measurement. top C pin, provided it was already determined that no
This will tend to decrease the B3 measurement result and other C pin is open.

680324fa

29
LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
USING THE S PINS AS DIGITAL OUTPUTS OR GATE detected on the device goes above approximately 145°C,
DRIVERS the configuration registers will be reset to default states,
The S outputs include an internal pull-up PMOS. Therefore turning off all discharge switches and disabling ADC
the S pins will behave as a digital output when loaded with conversions. When a thermal shutdown has occurred, the
a high impedance, e.g. the gate of an external MOSFET. THSD bit in the temperature register group will go high.
For applications requiring high battery discharge currents, The bit is cleared by performing a read of the temperature
connect a discrete PMOS switch device and suitable dis- registers (RDTMP command).
charge resistor to the cell, and the gate terminal to the S Since thermal shutdown interrupts normal operation, the
output pin, as illustrated in Figure 11. internal temperature monitor should be used to determine
when the device temperature is approaching unacceptable
Cn levels.
Si2351DS

+ 3.3k
Sn
USING THE LTC6803 WITH LESS THAN 12 CELLS
33Ω
1W If the LTC6803 is powered by the stacked cells, the minimum
680324 F11
Cn – 1 number of cells is governed by the supply voltage require-
ments of the LTC6803. The sum of the cell voltages must be
Figure 11. External Discharge FET Connection (One Cell Shown) 10V to guarantee that all electrical specifications are met.
Figure 12 shows an example of the LTC6803-4 when used
POWER DISSIPATION AND THERMAL SHUTDOWN to monitor seven cells. The lowest C inputs connect to the
The MOSFETs connected to the Pins S1 through S12 can be seven cells and the upper C inputs connect to C12. Other
used to discharge battery cells. An external resistor should configurations, e.g., 9 cells, would be configured in the
be used to limit the power dissipated by the MOSFETs. The same way: the lowest C inputs connected to the battery
maximum power dissipation in the MOSFETs is limited by cells and the unused C inputs connected to C12. The unused
the amount of heat that can be tolerated by the LTC6803. inputs will result in a reading of 0V for those channels.
Excessive heat results in elevated die temperatures. The The ADC can also be commanded to measure a stack of
electrical characteristics for the LTC6803 I-grade are 10 or 12 cells, depending on the state of the CELL10 bit
guaranteed for die temperatures up to 85°C. Little or no in the control register. The ADC can also be commanded
degradation will be observed in the measurement accuracy to measure any individual cell voltage.
for die temperatures up to 105°C. Damage may occur
above 150°C, therefore the recommended maximum die FAULT PROTECTION
temperature is 125°C.
Care should always be taken when using high energy
To protect the LTC6803 from damage due to overheating, sources such as batteries. There are numerous ways
a thermal shutdown circuit is included. Overheating of the that systems can be (mis)configured when considering
device can occur when dissipating significant power in the assembly and service procedures that might affect a
the cell discharge switches. The problem is exacerbated battery system during its useful lifespan. Table 18 shows
when operating with a large voltage between V+ and V–. the various situations that should be considered when plan-
The thermal shutdown circuit is enabled whenever the ning protection circuitry. The first five scenarios are to be
device is not in standby mode (see Modes of Operation). anticipated during production and appropriate protection
It will also be enabled when any current mode input or is included within the LTC6803 device itself.
output is sinking or sourcing current. If the temperature

680324fa

30
 LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
NEXT HIGHER GROUP
Internal Protection Diodes
OF 7 CELLS
Each pin of the LTC6803 has protection diodes to help
100
V+ prevent damage to the internal device structures caused
C12
S12 by external application of voltages beyond the supply rails
C11 as shown in Figure 13. The diodes shown are conventional
S11
C10 silicon diodes with a forward breakdown voltage of 0.5V.
S10
C9
The unlabeled Zener diode structures have a reverse
S9 breakdown characteristic which initially breaks down at
C8
S8
12V then snaps back to a 7V clamping potential. The Zener
+ C7 diodes labeled ZCLAMP are higher voltage devices with an
S7 LTC6803-4
C6 initial reverse breakdown of 30V snapping back to 25V.
+
S6 The forward voltage drop of all Zeners is 0.5V. Refer to
+ C5
S5 this diagram in the event of unpredictable voltage clamp-
+ C4 ing or current flow. Limiting the current flow at any pin to
S4
+ C3 ±10mA will prevent damage to the IC.
S3
C2
+
S2
C1
READING EXTERNAL TEMPERATURE PROBES
+ S1
C0 The LTC6803 includes two channels of ADC input, VTEMP1
V– and VTEMP2, that are intended to monitor thermistors
(tempco about –4%/°C generally) or diodes (–2.2mV/°C
680324 F12
NEXT LOWER GROUP
OF 7 CELLS
typical) located within the cell array. Sensors can be
Figure 12. Monitoring 7 Cells with the LTC6803-4 powered directly from VREF as shown in Figure 14 (up to
60µA total).

Table 18. LTC6803 Failure Mechanism Effect Analysis

SCENARIO EFFECT DESIGN MITIGATION
Cell input open-circuit (random) Power-up sequence at IC inputs Clamp diodes at each pin to V+ and V– (within IC) provide
alternate power path
Cell input open-circuit (random) Differential input voltage overstress Zener diodes across each cell voltage input pair (within IC) limits
stress
Disconnection of a harness between Loss of supply connection to the IC Separate power may be provided by a local supply
a group of battery cells and the IC
(in a system of stacked groups)
Data link disconnection between Loss of serial communication (no stress to ICs) The device will enter standby mode within 2 seconds of
LTC6803 and the master disconnect. Discharge switches are disabled in standby mode
Cell-pack integrity, break between No effect during charge or discharge Use digital isolators to isolate the LTC6803-2/LTC6803-4 serial
stacked units port from other LTC6803-2/LTC6803-4 serial ports
Cell-pack integrity, break within Cell input reverse overstress during discharge Add parallel Schottky diodes across each cell for load-path
stacked unit redundancy. Diode and connections must handle full operating
current of stack, will limit stress on IC
Cell-pack integrity, break within Cell input positive overstress during charge Add SCR across each cell for charge-path redundancy. SCR and
stacked unit connections must handle full charging current of stack, will limit
stress on IC by selection of trigger Zener

680324fa

31
LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
V+ LTC6803-4
LTC6803-4
1 VREG
100k 100k
C12 VREF
2
VTEMP2
S12
3 VTEMP1
C11 NC 100k 100k
4 1µF 1µF
V– NTC NTC
S11 ZCLAMP
5
680324 F14
C10
6 ZCLAMP ZCLAMP
S10 Figure 14. Driving Thermistors Directly from VREF
7 ZCLAMP
C9
8
S9 A3
9 40
C8 A2 +
10 39
A1 LT6000
S8
11 38
C7 A0
–
12 37
S7 LTC6803-4
13 VREG VREG
C6 32 10k 10k
14 ZCLAMP VREF
VREF VTEMP2
S6 31
15 VTEMP2 VTEMP1
C5 30 NC 10k 10k
16
V– NTC NTC
S5 VTEMP1
17 29
680324 F15
C4
18

19
S4 CSBI
44 Figure 15. Buffering VREF for Higher Current Sensors
C3 SDO
20 43

21
S3 SDI
42
Expanding Probe Count
C2 SCKI
22 41 As shown Figure 16, a dual 4:1 multiplexer is used to ex-
GPIO2
23
S2
ZCLAMP 36 pand the general purpose VTEMP1 and VTEMP2 ADC inputs
24
C1 GPIO1
35 to accept 8 different probe signals. The channel is selected
25
S1 WDTB
34 by setting the general purpose digital outputs GPIO1 and
26
C0 TOS
33 GPIO2 and the resultant signals are buffered by sections
of the LT6004 micropower dual operational amplifier. The
probe excitation circuitry will vary with probe type and is
V–
27
not shown here.
680324 F13
NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 27
Another method of multiple sensor support is possible
Figure 13. Internal Protection Diodes without the use of any GPIO pins. If the sensors are PN
diodes and several used in parallel, then the hottest diode
For sensors that require higher drive currents, a buffer will produce the lowest forward voltage and effectively
op amp may be used as shown in Figure 15. Power for establish the input signal to the VTEMP input(s). The hottest
the sensor is actually sourced indirectly from the VREG diode will therefore dominate the readout from the VTEMP
pin in this case. Probe loads up to about 1mA maximum inputs that the diodes are connected to. In this scenario,
are supported in this configuration. Since VREF is shut the specific location or distribution of heat is not known,
down during the LTC6803 idle and shutdown modes, the but such information may not be important in practice.
thermistor drive is also shut off and thus power dissipa- Figure 17 shows the basic concept. In any of the sensor
tion minimized. Since VREG remains always on, the buffer configurations shown, a full-scale cold readout would be
op amp (LT6000 shown) is selected for its ultralow power an indication of a failed-open sensor connection to the
consumption (12µA). LTC6803.
680324fa

32
 LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
PROBE8 ADDING CALIBRATION AND FULL-STACK
PROBE7
PROBE6
MEASUREMENTS
PROBE5
The general purpose VTEMP ADC inputs may be used to digi-
1 16
2
Y0 VCC
15
PROBE4 tize any signals from 0V to 4V with accuracy corresponding
3
Y2
Y
X2
X1
14
PROBE3
PROBE2
closely with that of the cell 1 ADC input. One useful signal
6
+ – 5 4
Y3
74HC4052
X
13
PROBE1 to provide is a high accuracy voltage reference, such as
4 8 5 12
6
Y1 X0
11 3.300V from an LTC6655-3.3. From periodic readings of
1/2 LT6004 INH X3
7 7
VEE A
10 this signal, the host software can provide correction of
8 9
GND B the LTC6803 readings to improve the accuracy over that
CPO2 of the internal LTC6803 reference and/or validate ADC
GPO1
operation. Figure 18 shows a means of selectively pow-
VREG
VTEMP2 ering an LTC6655-3.3 from the battery stack, under the
1/2 LT6004 8
1 + 3 680324 F16 control of the GPIO1 output of the LTC6803-2. Since the
VTEMP1 2
– operational power of the reference IC would add significant
1µF
4 thermal loading to the LTC6803 if powered from VREG, an
V– external high voltage NPN pass transistor is used to form
a local 4.4V (Vbe below VREG) from the battery stack. The
Figure 16. Expanding Sensor Count with Multiplexing GPIO1 signal controls a PMOS FET switch to activate the
reference when calibration is to be performed. Since GPIO
signals default to logic high in shutdown, the reference
200k
will automatically turn off during idle periods.
LTC6803-4
VREG 200k Another useful signal is a measure of the total stack poten-
VREF
VTEMP2
tial. This provides a redundant operational measurement
VTEMP1 of the cells in the event of a malfunction in the normal
NC
V–
acquisition process, or as a faster means of monitoring
680324 F17 the entire stack potential. Figure 19 shows how a resis-
tive divider is used to derive a scaled representation of a
Figure 17. Using Diode Sensors as Hot Spot Detectors full cell group potential. A MOSFET is used to disconnect

TOP CELL POTENTIAL

CZT5551
1M
LTC6803-2
35
GPIO1 Si2351DS 100nF
LTC6655-3.3
31 1 8
VREG SHDN GND
2 7
28 VIN VOUT_F
VTEMP1 3 6
GND VOUT_S
26 4 5
V– 1µF 10µF
GND GND

680324 F18

Figure 18. Providing Measurement of Calibration Reference

680324fa

33
LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
CELLGROUP+
499k PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA
1M 1
PORT
2N7002K
WDTB
2 Isolation techniques that are capable of supporting the
VREG 3
1Mbps data rate of the LTC6803-2/LTC6803-4 require more
8 1µF
+
3 power on the isolated (battery) side than can be furnished
VTEMP1
1
1/2 LT6004
by the VREG output of the LTC6803-2/LTC6803-4. To keep
–
2 10nF battery drain minimal, this means that a DC/DC function
4 31.6k
must be implemented along with a suitable data isolation
V– circuit, such as shown in Figure 20. A quad (3 + 1) data
CELLGROUP–
680324 F19
isolator Si8441AB-C-IS is used to provide non-galvanic
SPI signal connections between a host microprocessor
Figure 19. Using a VTEMP Input for Full-Stack Readings and an LTC6803-2/LTC6803-4. An inexpensive isolated DC/
DC converter provides powering of the isolator function
the resistive loading on the cell group when the IC enters completely from the host 5V power supply. A quad three-
standby mode (i.e., when WDTB goes low). An LT6004 state buffer is used to allow SPI inputs at the LTC6803-2/
micropower operational amplifier section is shown for LTC6803-4 to rise to a logic high level when the isolator
buffering the divider signal to preserve accuracy. This circuitry powers down, assuring the lowest power con-
circuit has the virtue that it can be converted about four sumption in the standby condition. The pull-ups to VREG
times more frequently than the entire battery array, thus are selected to match the internal loading on VREG by ICs
offering a higher sample rate option at the expense of operating with a current mode SPI interface, thus balanc-
some precision/accuracy, reserving the high resolution ing the current in all cells during operation. The additional
cell readings for calibration and balancing data. pull-up on the SDO line (1k resistor and Schottky diode)
is to improve rise time, in lower data rate applications this
may not be needed.

Si8441AB-C-IS
QUAD ISOLATOR CMDSH2-3
1 16 1k
5V_HOST VDD1 VDD2
2 15 13
GND1 GND2 4.22k
100Ω VREG
3 14 12 11
SPI_CLOCK A1 B1 SCKI
100Ω 4 13 1/4 74ABT126
SPI_CHIPSELECT A2 B2 1 4.22k
100Ω 5 12 2 3
SPI_MASTEROUT A3 B3 CSB1
100Ω 6 11 4 4.22k
SPI_MASTERIN A4 B4 1/4 74ABT126
7 10 5 6
1µF EN1 EN2 1µF SCI
8 9 4.22k
GND_HOST GND1 GND2 1/4 74ABT126 10
1µF SDO
8 9
1/4 74ABT126
V–
1 LTC1693-2 8 74ABT126 SUPPLY SHARED WITH
680324 F20

IN1 VCC1 33nF BAT54S ISOLATOR VDD2 and GND2

470pF 2 7 PE-68386
GND1 OUT1
3 6 1• •6
IN2 VCC2
20.0k 4 5 3 4
GND2 OUT2
10.0k

Figure 20. Providing an Isolated High Speed Data Interface

680324fa

34
 LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
SUPPLY DECOUPLING IF BATTERY-STACK POWERED ADVANTAGES OF KELVIN CONNECTION ON C0
As shown in Figure 21, the LTC6803-4 can have filtering The V– trace resistance can cause an observable voltage
on both V+ and V–, so differential bypassing to the cell drop between the negative end of the bottom battery
group potentials is recommended. The Zener suppresses cell and V– pin of LTC6803. This voltage drop will add to
overvoltages from reaching the IC supply pins. A small the measurement error of the bottom cell voltage. The
ferrite-bead inductor provides protection for the Zener, par- LTC6803‑4 separates C0 from V–, allowing Kelvin con-
ticularly from energetic ESD strikes. Since the LTC6803-2 nection on C0 as shown in Figure 22. Voltage drop on the
cannot have a series resistance to V–, additional Schottky V– trace will not affect the bottom cell voltage measure-
diodes are needed to prevent ESD-induced reverse-supply ment. The Kelvin connection will also allow RC filtering
(substrate) currents to flow. on V– as shown in Figure 21.

BLM31PG330SN1L 100Ω
CELLGROUP+ V+

CMHZ5265B BAT46W 100nF

CELLGROUP– V–
680324 F21

LTC6803-2 Configuration

BLM31PG330SN1L 100Ω
CELLGROUP+ V+

CMHZ5265B 100nF
100Ω
CELLGROUP– V–

LTC6803-4 Configuration

Figure 21. Supply Decoupling

+
BATTERY
+ STACK

+ LTC6803-4

C1
+
C0
R
V–
68034 F20
ISUPPLY

Figure 22. Kelvin Connection on C0 Improving

Bottom Cell Voltage Measurement Accuracy

680324fa

35
LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
HARDWARE SHUTDOWN separation of traces at different potentials. The pinout
To completely shut down the LTC6803 a PMOS switch can of the LTC6803 was chosen to facilitate this physical
be connected to V+, or, V+ can be driven from an isolated separation. There is no more than 5.5V between any two
power supply. Figure 23 shows an example of a switched adjacent pins. The package body is used to separate the
V+. The breakdown voltage of DZ4 is about 1.8V. If SHDN < highest voltage (e.g., 43.2V) from the lowest voltage (0V).
1.8V, no current will flow through the stacked MMBTA42s As an example, Figure 24 shows the DC voltage on each
and the 1M resistors. TP0610Ks will be completely shut pin with respect to V– when twelve 3.6V battery cells are
off. If SHDN > 2.5V, M7 will be turned on and then all connected to the LTC6803.
TP0610Ks will be turned on.
43.2V V+ CSBI 0V TO 5.5V
43.2V C12 SDO 0V TO 5.5V
TP0610K
V+ 43.2V S12 SDI 0V TO 5.5V
39.6V C11 SCKI 0V TO 5.5V
C12
+ 39.6V S11 A3 0V TO 5.5V

LTC6803-4
DZ1
1M + 36V C10 A2 0V TO 5.5V
15V 36V S10 A1 0V TO 5.5V
IC #3 LTC6803-4
32.4V C9 A0 0V TO 5.5V
C0 + 32.4V S9 GPIO2 0V TO 5.5V
D1
28.8V C8 GPIO1 0V TO 5.5V
V– 28.8V WDTB 0V TO 5.5V
S8
25.2V C7 TOS 0V TO 5.5V
TP0610K 25.2V S7 VREG 5V
V+ 21.6 C6 VREF 3.1V
21.6 VTEMP2 1.5V
C12
+ S6
DZ2 18V C5 VTEMP1 1.5V
1M
LTC6803-4 15V + 18V S5 NC 0V
IC #2 14.4V V– 0V
C4
D2 14.4V S4 C0 0V
C0 + 10.8 C3 S1 3.6V
V– 10.8 S3 C1 3.6V
7.2 C2 S2 7.2V
680324 F24
TP0610K
V+
Figure 24. Typical Pin Voltages for Twelve 3.6V Cells
C12 DZ3
15V 1M
+
LTC6803-4 SHDN ADVANTAGES OF DELTA-SIGMA ADCS
IC #1 +
DZ4 The LTC6803 employs a delta-sigma analog-to-digital
1.8V DZ1, DZ2, DZ3: MMSZ5245B
C0 + DZ4: MMSZ4678T1 converter for voltage measurement. The architecture of
50k ALL NPN: MMBTA42
V– ALL PN: RS07J delta-sigma converters can vary considerably, but the
680324 F23
common characteristic is that the input is sampled many
times over the course of a conversion and then filtered or
Figure 23. Hardware Shutdown Circuit Reduces Total Supply averaged to produce the digital output code. In contrast,
Current of LTC6803-4 to About 0µA
a SAR converter takes a single snapshot of the input
voltage and then performs the conversion on this single
PCB LAYOUT CONSIDERATIONS sample. For measurements in a noisy environment, a
delta-sigma converter provides distinct advantages over
The VREG and VREF pins should be bypassed with a 1µF
capacitor for best performance. The LTC6803 is capable of a SAR converter.
operation with as much as 55V between V+ and V–. Care While SAR converters can have high sample rates, the full-
should be taken on the PCB layout to maintain physical power bandwidth of a SAR converter is often greater than
680324fa

36
 LTC6803-2/LTC6803-4
APPLICATIONS INFORMATION
1MHz, which means the converter is sensitive to noise out (187µs time constant) which has the same integrated
to this frequency. And many SAR converters have much response to wideband noise as the LTC6803 ADC, which
higher bandwidths—up to 50MHz and beyond. It is pos- is about 1350Hz. This means that if wideband noise is
sible to filter the input, but if the converter is multiplexed applied to the LTC6803 input, the increase in noise seen
to measure several input channels a separate filter will be at the digital output will be the same as an ADC with a
required for each channel. A low frequency filter cannot wide bandwidth (such as a SAR) preceded by a perfect
reside between a multiplexer and an ADC and achieve a 1350Hz brick wall lowpass filter.
high scan rate across multiple channels. Another conse-
Thus if an analog filter is placed in front of a SAR converter
quence of filtering a SAR ADC is that any noise reduction
to achieve the same noise rejection as the LTC6803 ADC,
gained by filtering the input cancels the benefit of having
the SAR will have a slower response to input signals. For
a high sample rate in the first place, since the filter will
example, a step input applied to the input of the 850Hz
take many conversion cycles to settle.
filter will take 1.55ms to settle to 12 bits of precision, while
For a given sample rate, a delta-sigma converter can the LTC6803 ADC settles in a single 1ms conversion cycle.
achieve excellent noise rejection while settling completely This also means that very high sample rates do not provide
in a single conversion—something that a filtered SAR con- any additional information because the analog filter limits
verter cannot do. Noise rejection is particularly important the frequency response.
in high voltage switching controllers, where switching
While higher order active filters may provide some im-
noise will invariably be present in the measured voltage.
provement, their complexity makes them impractical for
Other advantages of delta-sigma converters are that they
high channel count measurements as a single filter would
are inherently monotonic, meaning they have no missing
be required for each input.
codes, and they have excellent DC specifications.
Also note that the SINC2 response has a 2nd order roll-
Converter Details off envelope, providing an additional benefit over a single
The LTC6803 ADC has a 2nd order delta-sigma modulator pole analog filter.
followed by a SINC2, finite impulse response (FIR) digital
filter. The front-end sample rate is 512ksps, which greatly 10

reduces input filtering requirements. A simple 16kHz, 0

1-pole filter composed of a 100Ω resistor and a 0.1≤F
–10
capacitor at each input will provide adequate filtering
FILTER GAIN (dB)

for most applications. These component values will not –20

degrade the DC accuracy of the ADC. –30

Each conversion consists of two phases—an autozero –40

phase and a measurement phase. The ADC is autozeroed
–50
at each conversion, greatly improving CMRR. The second
half of the conversion is the actual measurement. –60
10 100 1k 10k 100k
FREQUENCY (Hz)
Noise Rejection 680324 F25

Figure 25 shows the frequency response of the ADC. The Figure 25. Noise Filtering of the LTC6803-4 ADC
roll-off follows a SINC2 response, with the first notch at
4kHz. Also shown is the response of a 1 pole, 850Hz filter

680324fa

37
LTC6803-2/LTC6803-4
PACKAGE DESCRIPTION
G Package
44-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1754 Rev Ø)

12.50 – 13.10*
(.492 – .516)
1.25 ±0.12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

7.8 – 8.2 5.3 – 5.7

7.40 – 8.20
(.291 – .323)

0.50
0.25 ±0.05
BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

5.00 – 5.60* 2.0

(.197 – .221) 1.65 – 1.85 (.079)
(.065 – .073) MAX

PARTING 0° – 8°
LINE
SEATING
0.50 PLANE
0.10 – 0.25 0.55 – 0.95**
(.01968)
(.004 – .010) (.022 – .037)
BSC 0.05
1.25 0.20 – 0.30† (.002)
(.0492) (.008 – .012) MIN
REF TYP G44 SSOP 0607 REV Ø

NOTE:
1.DRAWING IS NOT A JEDEC OUTLINE *DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS,
2. CONTROLLING DIMENSION: MILLIMETERS BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT
THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE
MILLIMETERS
3. DIMENSIONS ARE IN **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE
(INCHES)
†THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS.
4. DRAWING NOT TO SCALE
DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE

680324fa

38
 LTC6803-2/LTC6803-4
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/12 Clarification to UV/OV Operation 15

680324fa

39
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6803-2/LTC6803-4
TYPICAL APPLICATION
Typical 12-Cell Measurement Block
CELL 12

IMC1210ER100K
MMSZ5267B

BAT46W

BAT46W

100Ω 1M 1M 1M
1 LTC6803-2 44
V+ CSBI CSBI
2 43 SPI PORT
100nF C12FILTER C12 SDO SDO*
3 42 TO HOST µP
DC12 S12 SDI SDI
4 41 OR DATA ISOLATOR
C11FILTER C11 SCKI SCKI
5 40
DC11 S11 A3
6 39 *REQUIRES 1K PULL-UP
C10FILTER C10 A2
7 38 RESISTOR AT HOST DEVICE
DC10 S10 A1
8 37
C9FILTER C9 A0 1M
9 36
DC9 S9 GPIO2
10 35 1M
C8FILTER C8 GPIO1
11 34
DC8 S8 WDTB
REPEAT INPUT CIRCUITS 12 33 1M
C7FILTER C7 NC
FOR CELL3 TO CELL12 13 32
DC7 S7 TOS
14 31
C6FILTER C6 VREG 10.0k
15 30
DC6 S6 VREF NTC2
16 29 3
C5FILTER C5 VTEMP2 1µF 1µF 1k
17 28 8
DC5
18
S5 VTEMP1
27
+
C4FILTER C4 NC 1
19 26 1/2 LT6004 10nF
DC4 S4 V– 2
20 25 –
C3FILTER C3 S1 4
21 24
DC3 S3 C1
22 23
C2 S2
5 8
C2FILTER +
CELL2 7 10.0k
RQJ0303PGDQALT 100Ω 100nF 1/2 LT6004 NTC1
PDZ7.5B 6
3.3k – 4
1k
33Ω
475Ω 10nF
C1FILTER
CELL1 680324 TA02
RQJ0303PGDQALT 100Ω 100nF
PDZ7.5B
3.3k
33Ω
475Ω

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC6801 Independent Multicell Battery Stack Fault Monitor Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or
Overvoltage. Companion to the LTC6802 and LTC6803 family
LTC6802-1 Multicell Battery Stack Monitor with Parallel Addressed Functionally Equivalent to the LTC6803-1 and the LTC6803-3
Serial Interface
LTC6802-2 Multicell Battery Stack Monitor with an Individually Functionally Equivalent to LTC6803-2/LTC6803-4. Pin Compatible with the
Addressable Serial Interface LTC6803-2
LTC6803-1/ Multicell Battery Stack Monitor with Daisy-Chained Functionality Equivalent to LTC6803-2/LTC6803-4, Allows for Multiple Devices
LTC6803-3 Serial Interface to Be Daisy Chained

680324fa

40 Linear Technology Corporation

LT 0812 REV A • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2011