LTC6804-1/LTC6804-2

Multicell Battery Monitors

Features Description
nn Measures Up to 12 Battery Cells in Series The LTC®6804 is a 3rd generation multicell battery stack
nn Stackable Architecture Supports 100s of Cells monitor that measures up to 12 series connected battery
nn Built-In isoSPI™ Interface: cells with a total measurement error of less than 1.2mV. The
1Mbps Isolated Serial Communications cell measurement range of 0V to 5V makes the LTC6804
Uses a Single Twisted Pair, Up to 100 Meters suitable for most battery chemistries. All 12 cell voltages
Low EMI Susceptibility and Emissions can be captured in 290µs, and lower data acquisition rates
nn 1.2mV Maximum Total Measurement Error can be selected for high noise reduction.
nn 290µs to Measure All Cells in a System
nn Synchronized Voltage and Current Measurement
Multiple LTC6804 devices can be connected in series,
nn 16-Bit Delta-Sigma ADC with Frequency Program-
permitting simultaneous cell monitoring of long, high volt-
age battery strings. Each LTC6804 has an isoSPI interface
mable 3rd Order Noise Filter
nn Engineered for ISO26262 Compliant Systems
for high speed, RF-immune, local area communications.
nn Passive Cell Balancing with Programmable Timer
Using the LTC6804-1, multiple devices are connected in
nn 5 General Purpose Digital I/O or Analog Inputs:
a daisy-chain with one host processor connection for all
devices. Using the LTC6804-2, multiple devices are con-
Temperature or other Sensor Inputs
nected in parallel to the host processor, with each device
Configurable as an I2C or SPI Master
nn 4μA Sleep Mode Supply Current
individually addressed.
nn 48-Lead SSOP Package Additional features include passive balancing for each cell,
an onboard 5V regulator, and 5 general purpose I/O lines.
Applications In sleep mode, current consumption is reduced to 4µA.
The LTC6804 can be powered directly from the battery,
nn Electric and Hybrid Electric Vehicles
or from an isolated supply.
nn Backup Battery Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered and isoSPI is a
nn Grid Energy Storage trademark of Linear Technology Corporation. All other trademarks are the property of their
nn High Power Portable Equipment respective owners. Protected by U.S. patents, including 8908799, 9182428, 9270133.

Typical Application
+
IPB Total Measurement Error
LTC6804-1 vs Temperature of 5 Typical Units
12S1P IMB
2.0
ILP
IPA
+ CELL VOLTAGE = 3.3V
1.5 5 TYPICAL UNITS
MEASUREMENT ERROR (mV)

IMA 1.0
•
• 0.5
IPB
+ 0
LTC6804-1
IMB –0.5
IPA
+ –1.0

IMA –1.5
•
–2.0
IPB
• MPU –50 –25 0 25 50 75 100 125
+ TEMPERATURE (°C)
LTC6804-1 680412 TA01b
SPI
IMB
IPA IP
+
•
•

•
•

LTC6820
IMA IM

680412 TA01a
680412fc

For more information www.linear.com/LTC6804-1 1

LTC6804-1/LTC6804-2
Table of Contents
Features...................................................... 1 Data Link Layer........................................................44
Applications................................................. 1 Network Layer.........................................................44
Typical Application ......................................... 1 Programming Examples..........................................54
Description.................................................. 1 Simple Linear Regulator..........................................58
Absolute Maximum Ratings............................... 3 Improved Regulator Power Efficiency......................58
Pin Configuration........................................... 3 Fully Isolated Power................................................. 59
Order Information........................................... 4 Reading External Temperature Probes..................... 59
Electrical Characteristics.................................. 4 Expanding the Number of Auxiliary
Pin Functions............................................... 17 Measurements.........................................................60
Block Diagram.............................................. 18 Internal Protection Features.....................................60
Operation................................................... 20 Filtering of Cell and GPIO Inputs..............................60
State Diagram..........................................................20 Cell Balancing with Internal Mosfets........................62
LTC6804 Core State Descriptions............................20 Cell Balancing with External MOSFETS................... 62
isoSPI State Descriptions........................................ 21 Discharge Control During Cell Measurements.........62
Power Consumption................................................ 21 Power Dissipation and Thermal Shutdown..............63
ADC Operation......................................................... 21 Method to Verify Balancing Circuitry.......................63
Data Acquisition System Diagnostics......................26 Current Measurement with a Hall Effect Sensor......66
Watchdog and Software Discharge Timer...............30 Current Measurement with a Shunt Resistor...........66
I2C/SPI Master on LTC6804 Using GPIOS............... 31 Using the LTC6804 with Less Than 12 Cells............ 67
Serial Interface Overview.........................................35 Package Description...................................... 76
4-Wire Serial Peripheral Interface (SPI) Revision History........................................... 77
Physical Layer.........................................................36 Typical Application........................................ 78
2-Wire Isolated Interface (isoSPI) Physical Layer....36 Related Parts............................................... 78

680412fc

2 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Absolute Maximum Ratings (Note 1)
Total Supply Voltage V+ to V–.....................................75V C8 to C4.................................................. –0.3V to 25V
Input Voltage (Relative to V–) C4 to C0.................................................. –0.3V to 25V
C0.......................................................... –0.3V to 0.3V Current In/Out of Pins
C12......................................................... –0.3V to 75V All Pins Except VREG, IPA, IMA, IPB, IMB, S(n)...10mA
C(n)......................................–0.3V to MIN (8 • n, 75V) IPA, IMA, IPB, IMB..............................................30mA
S(n)......................................–0.3V to MIN (8 • n, 75V) Operating Temperature Range
IPA, IMA, IPB, IMB .....................–0.3V to VREG + 0.3V LTC6804I..............................................–40°C to 85°C
DRIVE Pin................................................. –0.3V to 7V LTC6804H........................................... –40°C to 125°C
All Other Pins............................................ –0.3V to 6V Specified Temperature Range
Voltage Between Inputs LTC6804I..............................................–40°C to 85°C
V+ to C12.............................................................–5.5V LTC6804H........................................... –40°C to 125°C
C(n) to C(n – 1)......................................... –0.3V to 8V Junction Temperature............................................ 150°C
S(n) to C(n – 1)......................................... –0.3V to 8V Storage Temperature.............................. –65°C to 150°C
C12 to C8................................................ –0.3V to 25V Lead Temperature (Soldering, 10sec).................... 300°C

Pin Configuration
LTC6804-1 LTC6804-2
TOP VIEW TOP VIEW

V+ 1 48 IPB V+ 1 48 A3
C12 2 47 IMB C12 2 47 A2
S12 3 46 ICMP S12 3 46 A1
C11 4 45 IBIAS C11 4 45 A0
S11 5 44 SDO (NC)* S11 5 44 SDO (IBIAS)*
C10 6 43 SDI (NC)* C10 6 43 SDI (ICMP)*
S10 7 42 SCK (IPA)* S10 7 42 SCK (IPA)*
C9 8 41 CSB (IMA)* C9 8 41 CSB (IMA)*
S9 9 40 ISOMD S9 9 40 ISOMD
C8 10 39 WDT C8 10 39 WDT
S8 11 38 DRIVE S8 11 38 DRIVE
C7 12 37 VREG C7 12 37 VREG
S7 13 36 SWTEN S7 13 36 SWTEN
C6 14 35 VREF1 C6 14 35 VREF1
S6 15 34 VREF2 S6 15 34 VREF2
C5 16 33 GPIO5 C5 16 33 GPIO5
S5 17 32 GPIO4 S5 17 32 GPIO4
C4 18 31 V– C4 18 31 V–
S4 19 30 V–** S4 19 30 V–**
C3 20 29 GPIO3 C3 20 29 GPIO3
S3 21 28 GPIO2 S3 21 28 GPIO2
C2 22 27 GPIO1 C2 22 27 GPIO1
S2 23 26 C0 S2 23 26 C0
C1 24 25 S1 C1 24 25 S1

G PACKAGE G PACKAGE
48-LEAD PLASTIC SSOP 48-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 55°C/W TJMAX = 150°C, θJA = 55°C/W
*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD *THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD
ISOMD TIED TO V–: CSB, SCK, SDI, SDO ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IMA, IPA, NC, NC ISOMD TIED TO VREG: IMA, IPA, ICMP, IBIAS
**THIS PIN MUST BE CONNECTED TO V– **THIS PIN MUST BE CONNECTED TO V–

680412fc

For more information www.linear.com/LTC6804-1 3

LTC6804-1/LTC6804-2
Order Information http://www.linear.com/product/LTC6804-1#orderinfo

TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6804IG-1#PBF LTC6804IG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 85°C
LTC6804HG-1#PBF LTC6804HG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 125°C
LTC6804IG-2#PBF LTC6804IG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP –40°C to 85°C
LTC6804HG-2#PBF LTC6804HG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Parts ending with PBF are RoHS and WEEE compliant.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ADC DC Specifications
Measurement Resolution l 0.1 mV/bit
ADC Offset Voltage (Note 2) l 0.1 mV
ADC Gain Error (Note 2) 0.01 %
l 0.02 %
Total Measurement Error (TME) in C(n) to C(n – 1), GPIO(n) to V– = 0 ±0.2 mV
Normal Mode C(n) to C(n – 1) = 2.0 ±0.1 ±0.8 mV
C(n) to C(n – 1), GPIO(n) to V– = 2.0 l ±1.4 mV
C(n) to C(n – 1) = 3.3 ±0.2 ±1.2 mV
C(n) to C(n – 1), GPIO(n) to V– = 3.3 l ±2.2 mV
C(n) to C(n – 1) = 4.2 ±0.3 ±1.6 mV
C(n) to C(n – 1), GPIO(n) to V– = 4.2 l ±2.8 mV
C(n) to C(n – 1), GPIO(n) to V– = 5.0 ±1 mV
Sum of Cells, V(CO) = V– l ±0.2 ±0.75 %
Internal Temperature, T = Maximum ±5 °C
Specified Temperature
VREG Pin l ±0.1 ±0.25 %
VREF2 Pin l ±0.02 ±0.1 %
Digital Supply Voltage VREGD l ±0.1 ±1 %

680412fc

4 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Total Measurement Error (TME) in C(n) to C(n – 1), GPIO(n) to V– = 0 ±0.1 mV
Filtered Mode C(n) to C(n – 1) = 2.0 ±0.1 ±0.8 mV
C(n) to C(n – 1), GPIO(n) to V– = 2.0 l ±1.4 mV
C(n) to C(n – 1) = 3.3 ±0.2 ±1.2 mV
C(n) to C(n – 1), GPIO(n) to V– = 3.3 l ±2.2 mV
C(n) to C(n – 1) = 4.2 ±0.3 ±1.6 mV
C(n) to C(n – 1), GPIO(n) to V– = 4.2 l ±2.8 mV
C(n) to C(n – 1), GPIO(n) to V– = 5.0 ±1 mV
Sum of Cells, V(CO) = V– l ±0.2 ±0.75 %
Internal Temperature, T = Maximum ±5 °C
Specified Temperature
VREG Pin l ±0.1 ±0.25 %
VREF2 Pin l ±0.02 ±0.1 %
Digital Supply Voltage VREGD l ±0.1 ±1 %
Total Measurement Error (TME) in C(n) to C(n – 1), GPIO(n) to V– = 0 ±2 mV
Fast Mode C(n) to C(n – 1), GPIO(n) to V– = 2.0 l ±4 mV
C(n) to C(n – 1), GPIO(n) to V– = 3.3 l ±4.7 mV
C(n) to C(n – 1), GPIO(n) to V– = 4.2 l ±8.3 mV
C(n) to C(n – 1), GPIO(n) to V– = 5.0 ±10 mV
Sum of Cells, V(CO) = V– l ±0.3 ±1 %
Internal Temperature, T = Maximum ±5 °C
Specified Temperature
VREG Pin l ±0.3 ±1 %
VREF2 Pin l ±0.1 ±0.25 %
Digital Supply Voltage VREGD l ±0.2 ±2 %
Input Range C(n), n = 1 to 12 l C(n – 1) C(n – 1) + 5 V
C0 l 0
GPIO(n), n = 1 to 5 l 0 5 V
IL Input Leakage Current When Inputs C(n), n = 0 to 12 l 10 ±250 nA
Are Not Being Measured
GPIO(n), n = 1 to 5 l 10 ±250 nA

Input Current When Inputs Are C(n), n = 0 to 12 ±2 µA

Being Measured GPIO(n), n = 1 to 5 ±2 µA
Input Current During Open Wire l 70 100 130 µA
Detection

680412fc

For more information www.linear.com/LTC6804-1 5

LTC6804-1/LTC6804-2
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Voltage Reference Specifications
VREF1 1st Reference Voltage VREF1 Pin, No Load l 3.1 3.2 3.3 V
1st Reference Voltage TC VREF1 Pin, No Load 3 ppm/°C
1st Reference Voltage Hysteresis VREF1 Pin, No Load 20 ppm
1st Reference Long Term Drift VREF1 Pin, No Load 20 ppm/√kHr
VREF2 2nd Reference Voltage VREF2 Pin, No Load l 2.990 3 3.010 V
VREF2 Pin, 5k Load to V– l 2.988 3 3.012 V
2nd Reference Voltage TC VREF2 Pin, No Load 10 ppm/°C
2nd Reference Voltage Hysteresis VREF2 Pin, No Load 100 ppm
2nd Reference Long Term Drift VREF2 Pin, No Load 60 ppm/√kHr
General DC Specifications
IVP V+ Supply Current State: Core = SLEEP, isoSPI = IDLE VREG = 0V 3.8 6 µA
(See Figure 1: LTC6804 Operation VREG = 0V l 3.8 10 µA
State Diagram)
VREG = 5V 1.6 3 µA
VREG = 5V l 1.6 5 µA
State: Core = STANDBY 18 32 50 µA
l 10 32 60 µA
State: Core = REFUP or MEASURE 0.4 0.55 0.7 mA
l 0.375 0.55 0.725 mA
IREG(CORE) VREG Supply Current State: Core = SLEEP, isoSPI = IDLE VREG = 5V 2.2 4 µA
(See Figure 1: LTC6804 Operation VREG = 5V l 2.2 6 µA
State diagram)
State: Core = STANDBY 10 35 60 µA
l 6 35 65 µA
State: Core = REFUP 0.2 0.45 0.7 mA
l 0.15 0.45 0.75 mA
State: Core = MEASURE 10.8 11.5 12.2 mA
l 10.7 11.5 12.3 mA
IREG(isoSPI) Additional VREG Supply Current if LTC6804-2: ISOMD = 1, READY l 3.9 4.8 5.8 mA
isoSPI in READY/ACTIVE States RB1 + RB2 = 2k ACTIVE l 5.1 6.1 7.3 mA
Note: ACTIVE State Current
LTC6804-1: ISOMD = 0, READY l 3.7 4.6 5.6 mA
Assumes tCLK = 1µs, (Note 3)
RB1 + RB2 = 2k ACTIVE l 5.7 6.8 8.1 mA
LTC6804-1: ISOMD = 1, READY l 6.5 7.8 9.5 mA
RB1 + RB2 = 2k ACTIVE l 10.2 11.3 13.3 mA
LTC6804-2: ISOMD = 1, READY l 1.3 2.1 3 mA
RB1 + RB2 = 20k ACTIVE l 1.6 2.5 3.5 mA
LTC6804-1: ISOMD = 0, READY l 1.1 1.9 2.8 mA
RB1 + RB2 = 20k ACTIVE l 1.5 2.3 3.3 mA
LTC6804-1: ISOMD = 1, READY l 2.1 3.3 4.9 mA
RB1 + RB2 = 20k ACTIVE l 2.7 4.1 5.8 mA

680412fc

6 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V+ Supply Voltage TME Specifications Met (Note 6) l 11 40 55 V
VREG VREG Supply Voltage TME Supply Rejection < 1mV/V l 4.5 5 5.5 V
DRIVE output voltage Sourcing 1µA 5.4 5.6 5.8 V
l 5.2 5.6 6.0 V
Sourcing 500µA l 5.1 5.6 6.1 V
VREGD Digital Supply Voltage l 2.7 3.0 3.6 V
Discharge Switch ON Resistance VCELL = 3.6V l 10 25 Ω
Thermal Shutdown Temperature 150 °C
VOL(WDT) Watchdog Timer Pin Low WDT Pin Sinking 4mA l 0.4 V
VOL(GPIO) General Purpose I/O Pin Low GPIO Pin Sinking 4mA (Used as Digital Output) l 0.4 V
ADC Timing Specifications
tCYCLE Measurement + Calibration Cycle Measure 12 Cells l 2120 2335 2480 µs
(Figure 3) Time When Starting from the Measure 2 Cells l 365 405 430 µs
REFUP State in Normal Mode
Measure 12 Cells and 2 GPIO Inputs l 2845 3133 3325 µs
Measurement + Calibration Cycle Measure 12 Cells l 183 201.3 213.5 ms
Time When Starting from the Measure 2 Cells l 30.54 33.6 35.64 ms
REFUP State in Filtered Mode
Measure 12 Cells and 2 GPIO Inputs l 244 268.4 284.7 ms
Measurement + Calibration Cycle Measure 12 Cells l 1010 1113 1185 µs
Time When Starting from the
REFUP State in Fast Mode Measure 2 Cells l 180 201 215 µs
Measure 12 Cells and 2 GPIO Inputs l 1420 1564 1660 µs
tSKEW1 Skew Time. The Time Difference Fast Mode l 189 208 221 µs
(Figure 6) between C12 and GPIO2
Measurements, Command =
ADCVAX Normal Mode l 493 543 576 µs

tSKEW2 Skew Time. The Time Fast Mode l 211 233 248 µs
(Figure 3) Difference between C12 and C0
Measurements, Command = ADCV
Normal Mode l 609 670 711 µs

tWAKE Regulator Start-Up Time VREG Generated from Drive Pin (Figure 28) l 100 300 µs
tSLEEP Watchdog or Software Discharge SWTEN Pin = 0 or DCTO[3:0] = 0000 l 1.8 2 2.2 sec
Timer SWTEN Pin = 1 and DCTO[3:0] ≠ 0000 0.5 120 min
tREFUP Reference Wake-Up Time State: Core = STANDBY l 2.7 3.5 4.4 ms
(Figure 1, State: Core = REFUP l 0 ms
Figures 3 to 7)
fS ADC Clock Frequency l 3.0 3.3 3.5 MHz
SPI Interface DC Specifications
VIH(SPI) SPI Pin Digital Input Voltage High Pins CSB, SCK, SDI l 2.3 V
VIL(SPI) SPI Pin Digital Input Voltage Low Pins CSB, SCK, SDI l 0.8 V
VIH(CFG) Configuration Pin Digital Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l 2.7 V
Input Voltage High
VIL(CFG) Configuration Pin Digital Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l 1.2 V
Input Voltage Low

680412fc

For more information www.linear.com/LTC6804-1 7

LTC6804-1/LTC6804-2
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ILEAK(DIG) Digital Input Current Pins CSB, SCK, SDI, ISOMD, SWTEN, l ±1 µA
A0 to A3
VOL(SDO) Digital Output Low Pin SDO Sinking 1mA l 0.3 V
isoSPI DC Specifications (See Figure 16)
VBIAS Voltage on IBIAS Pin READY/ACTIVE State l 1.9 2.0 2.1 V
IDLE State 0 V
IB Isolated Interface Bias Current RBIAS = 2k to 20k l 0.1 1.0 mA
AIB Isolated Interface Current Gain VA ≤ 1.6V IB = 1mA l 18 20 22 mA/mA
IB = 0.1mA l 18 20 24.5 mA/mA
VA Transmitter Pulse Amplitude VA = |VIP – VIM| l 1.6 V
VICMP Threshold-Setting Voltage on ICMP VTCMP = ATCMP • VICMP l 0.2 1.5 V
Pin
ILEAK(ICMP) Input Leakage Current on ICMP Pin VICMP = 0V to VREG l ±1 µA
ILEAK(IP/IM) Leakage Current on IP and IM Pins IDLE State, VIP or VIM = 0V to VREG l ±1 µA
ATCMP Receiver Comparator Threshold VCM = VREG/2 to VREG – 0.2V, VICMP = 0.2V to 1.5V l 0.4 0.5 0.6 V/V
Voltage Gain
VCM Receiver Common Mode Bias IP/IM Not Driving (VREG – VICMP/3 – 167mV) V
RIN Receiver Input Resistance Single-Ended to IPA, IMA, IPB, IMB l 27 35 43 kΩ
isoSPI Idle/Wakeup Specifications (See Figure 21)
VWAKE Differential Wake-Up Voltage tDWELL = 240ns l 200 mV
tDWELL Dwell Time at VWAKE Before Wake VWAKE = 200mV l 240 ns
Detection
tREADY Startup Time After Wake Detection l 10 µs
tIDLE Idle Timeout Duration l 4.3 5.5 6.7 ms
isoSPI Pulse Timing Specifications (See Figure 19)
t1/2PW(CS) Chip-Select Half-Pulse Width l 120 150 180 ns
tINV(CS) Chip-Select Pulse Inversion Delay l 200 ns
t1/2PW(D) Data Half-Pulse Width l 40 50 60 ns
tINV(D) Data Pulse Inversion Delay l 70 ns
SPI Timing Requirements (See Figure 15 and Figure 20)
tCLK SCK Period (Note 4) l 1 µs
t1 SDI Setup Time before SCK Rising l 25 ns
Edge
t2 SDI Hold Time after SCK Rising l 25 ns
Edge
t3 SCK Low tCLK = t3 + t4 ≥ 1µs l 200 ns
t4 SCK High tCLK = t3 + t4 ≥ 1µs l 200 ns
t5 CSB Rising Edge to CSB Falling l 0.65 µs
Edge
t6 SCK Rising Edge to CSB Rising (Note 4) l 0.8 µs
Edge
t7 CSB Falling Edge to SCK Rising (Note 4) l 1 µs
Edge

680412fc

8 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

isoSPI Timing Specifications (See Figure 19)
t8 SCK Falling Edge to SDO Valid (Note 5) l 60 ns
t9 SCK Rising Edge to Short ±1 l 50 ns
Transmit
t10 CSB Transition to Long ±1 Transmit l 60 ns
t11 CSB Rising Edge to SDO Rising (Note 5) l 200 ns
tRTN Data Return Delay l 430 525 ns
tDSY(CS) Chip-Select Daisy-Chain Delay l 150 200 ns
tDSY(D) Data Daisy-Chain Delay l 300 360 ns
tLAG Data Daisy-Chain Lag (vs Chip- l 0 35 70 ns
Select)
t6(GOV) Data to Chip-Select Pulse Governor l 0.8 1.05 µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: These timing specifications are dependent on the delay through
may cause permanent damage to the device. Exposure to any Absolute the cable, and include allowances for 50ns of delay each direction. 50ns
Maximum Rating condition for extended periods may affect device corresponds to 10m of CAT-5 cable (which has a velocity of propagation of
reliability and lifetime. 66% the speed of light). Use of longer cables would require derating these
Note 2: The ADC specifications are guaranteed by the Total Measurement specs by the amount of additional delay.
Error specification. Note 5: These specifications do not include rise or fall time of SDO. While
Note 3: The ACTIVE state current is calculated from DC measurements. fall time (typically 5ns due to the internal pull-down transistor) is not a
The ACTIVE state current is the additional average supply current into concern, rising-edge transition time tRISE is dependent on the pull-up
VREG when there is continuous 1MHz communications on the isoSPI ports resistance and load capacitance on the SDO pin. The time constant must
with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply be chosen such that SDO meets the setup time requirements of the MCU.
current. See Applications Information section for additional details. Note 6: V+ needs to be greater than or equal to the highest C(n) voltage for
accurate measurements. See the graph Top Cell Measurement Error vs V+.

680412fc

For more information www.linear.com/LTC6804-1 9

LTC6804-1/LTC6804-2
Typical Performance Characteristics TA = 25°C, unless otherwise noted.

Measurement Error Measurement Error Due to IR Measurement Error Long-

vs Temperature Reflow Term Drift
2.0 35 30
CELL VOLTAGE = 3.3V 260°C, 1 CYCLE CELL VOLTAGE = 3.3V
5 TYPICAL UNITS 8 TYPICAL PARTS
1.5 30 25

MEASUREMENT ERROR (ppm)

MEASUREMENT ERROR (mV)

1.0
25

NUMBER OF PARTS
20
0.5
20
0 15
15
–0.5
10
10
–1.0
5 5
–1.5

–2.0 0 0
–50 –25 0 25 50 75 100 125 –125 –100 –75 –50 –25 0 25 50 75 0 500 1000 1500 2000 2500 3000
TEMPERATURE (°C) CHANGE IN GAIN ERROR (ppm) TIME (HOURS)
680412 G03
680412 G01 680412 G02

Measurement Error vs Input, Measurement Error vs Input, Measurement Error vs Input,

Normal Mode Filtered Mode Fast Mode
2.0 2.0 10
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT 8
1.5 1.5
6

MEASUREMENT ERROR (mV)

MEASUREMENT ERROR (mV)

MEASUREMENT ERROR (mV)

1.0 1.0
4
0.5 0.5
2
0 0 0

–0.5 –0.5 –2
–4
–1.0 –1.0
–6
–1.5 –1.5 –8 10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
–2.0 –2.0 –10
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
INPUT (V) INPUT (V) INPUT (V)
680412 G04 680412 G05 680412 G06

Measurement Noise vs Input, Measurement Noise vs Input, Measurement Noise vs Input,

Normal Mode Filtered Mode Fast Mode
1.0 1.0 10
0.9 0.9 9
0.8 0.8 8
0.7 0.7 7
PEAK NOISE (mV)

PEAK NOISE (mV)

PEAK NOISE (mV)

0.6 0.6 6
0.5 0.5 5
0.4 0.4 4
0.3 0.3 3
0.2 0.2 2
0.1 0.1 1
0 0 0
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4
INPUT (V) INPUT (V) INPUT (V)
680412 G07 680412 G08 680412 G09

680412fc

10 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Typical Performance Characteristics TA = 25°C, unless otherwise noted.

Measurement Gain Error Measurement Gain Error

Hysteresis, Hot Hysteresis, Cold Noise Filter Response
25 30 0
TA = 85°C TO 25°C TA = –45°C TO 25°C

25 –10
20

NOISE REJECTION (dB)

–20
NUMBER OF PARTS

NUMBER OF PARTS
20
15
–30
15
–40
10
10
–50
5
5
–60

0 0 –70
–50 –40 –30 –20 –10 0 10 20 30 –40 –30 –20 –10 0 10 20 30 40 10 100 1k 10k 100k 1M
CHANGE IN GAIN ERROR (ppm) CHANGE IN GAIN ERROR (ppm) INPUT FREQUENCY (Hz)
680412 G10 680412 G11
ADC MODE:
FILTERED NORMAL
2kHz 15kHz
3kHz FAST 680412 G12

Measurement Error V+ PSRR Measurement Error VREG PSRR

Measurement Error vs VREG vs Frequency vs Frequency
2.0 –40 0
V+DC = 39.6V VREG(DC) = 5V
1.5
–45 V+AC = 5VP-P VREG(AC) = 500mVP-P
–10
–50 1 BIT CHANGE < –90dB 1 BIT CHANGE < –70dB
MEASUREMENT ERROR (mV)

1.0 VREG GENERATED FROM

–55 DRIVE PIN, FIGURE 28 –20
0.5 –60
PSRR (dB)

PSRR (dB)

–30
0 –65
–40
–70
–0.5
–75 –50
–1.0
VIN = 2V –80
VIN = 3.3V –60
–1.5 –85
VIN = 4.2V
–2.0 –90 –70
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
VREG (V) FREQUENCY (Hz) FREQUENCY (Hz)
680412 G13 680412 G14 68412 G15

Cell Measurement Error GPIO Measurement Error

vs Input RC Values vs Input RC Values Top Cell Measurement Error vs V+
20 10 1.0
NORMAL MODE CONVERSIONS TIME BETWEEN MEASUREMENTS > 3RC C12-C11 = 3.3V
DIFFERENTIAL RC FILTER ON EVERY C PIN. 8 0.8 C12 = 39.6V
CELL 12 MEASUREMENT ERROR (mV)

15
CELL MEASUREMENT ERROR (mV)

EXPECT CELL-TO-CELL AND 6 0.6

MEASUREMENT ERROR (mV)

10 PART-TO-PART VARIATIONS
IN ERROR IF R > 100Ω AND/OR C > 10nF 4 0.4
5 2 0.2

0 0 0
–2 –0.2
–5
–4 –0.4
–10 C=0 C=0
C = 10nF –6 C = 100nF –0.6
–15 C = 100nF –8 C = 1µF –0.8
C = 1µF C = 10µF
–20 –10 –1.0
1 10 100 1000 10000 1 10 100 1000 10000 100000 36 38 40 42 44
INPUT RESISTOR, R (Ω) INPUT RESISTANCE, R (Ω) V+ (V)
680412 G16 680412 G17 680412 G18

680412fc

For more information www.linear.com/LTC6804-1 11

 LTC6804-1/LTC6804-2
Typical Performance Characteristics TA = 25°C, unless otherwise noted.

Cell Measurement Error Cell Measurement CMRR

vs Common Mode Voltage vs Frequency Measurement Error vs V+
1.0 0 2.0
C12-C11 = 3.3V VCM(IN) = 5VP-P MEASUREMENT ERROR OF
0.8 V+ = 39.6V –10 NORMAL MODE CONVERSIONS CELL 1 WITH 3.3V INPUT.
CELL 12 MEASUREMENT ERROR (mV)

1.5
0.6 VREG GENERATED FROM

MEASUREMENT ERROR (mV)

–20 1.0 DRIVE PIN, FIGURE 28
0.4
–30

REJECTION (dB)
0.2 0.5
–40
0 0
–50
–0.2
–0.5
–60
–0.4
–70 –1.0
–0.6
–0.8 –80 –1.5

–1.0 –90 –2.0

0 10 20 30 100 1k 10k 100k 1M 10M 5 10 15 20 25 30 35 40
C11 VOLTAGE (V) FREQUENCY (Hz) V+ (V)
680412 G19 680412 G20 680412 G21

Sleep Supply Current vs V+ Standby Supply Current vs V+ REFUP Supply Current vs V+

7 80 1000
125°C 125°C
85°C 85°C
STANDBY SUPPLY CURRENT (µA)

6 25°C 25°C

REFUP SUPPLY CURRENT (µA)

SLEEP SUPPLY CURRENT (µA)

–45°C 70 –45°C
950
5
60
4
125°C
900 85°C
50 25°C
3 –45°C
SLEEP SUPPLY CURRENT = STANDBY SUPPLY CURRENT = REFUP SUPPLY CURRENT =
V+ CURRENT + VREG CURRENT V+ CURRENT + VREG CURRENT V+ CURRENT + VREG CURRENT
2 40 850
5 15 25 35 45 55 65 75 5 15 25 35 45 55 65 75 5 15 25 35 45 55 65 75
V+ (V) V+ (V) V+ (V)
680412 G22 680412 G23 680412 G24

Measure Mode Supply Current Internal Die Temperature

vs V+ Measurement Time vs Temperature Measurement Error vs Temperature
12.50 2440 10
TEMPERATURE MEASUREMENT ERROR (DEG)

12 CELL NORMAL MODE TIME 5 TYPICAL UNITS

MEASURE MODE SUPPLY CURRENT (mA)

SHOWN. ALL ADC MEASURE 8

2420
12.25 TIMES SCALE PROPORTIONALLY
6
2400
MEASUREMENT TIME (µs)

4
12.00
2380 2

11.75 2360 0

2340 –2
125°C
11.50 85°C –4
25°C 2320
–45°C VREG = 5V –6
11.25
MEASURE MODE SUPPLY CURRENT = 2300 VREG = 4.5V
+ CURRENT + V
–8
V REG CURRENT VREG = 5.5V
11.00 2280 –10
5 15 25 35 45 55 65 75 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
V+ (V) TEMPERATURE (°C) TEMPERATURE (°C)
680412 G25 680412 G26 680412 G27

680412fc

12 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Typical Performance Characteristics TA = 25°C, unless otherwise noted.

VREF2 vs Temperature VREF2 Load Regulation VREF2 V+ Line Regulation

3.003 0 200
V+ = 39.6V VREG GENERATED FROM
5 TYPICAL PARTS 150 DRIVE PIN, FIGURE 28
3.002
–200
100

CHANGE IN VREF2 (ppm)

CHANGE IN VREF2 (ppm)
3.001
50
–400
VREF2 (V)

3.000 0
–600 V+ = 39.6V –50
2.999 VREG = 5V
125°C –100 125°C
–800 85°C 85°C
2.998
25°C –150 25°C
–45°C –45°C
2.997 –1000 –200
–50 –25 0 25 50 75 100 125 0.01 0.1 1 10 5 15 25 35 45 55 65 75
TEMPERATURE (°C) IOUT (mA) V+ (V)
680412 G28 680412 G29 580412 G30

VREF2 VREG Line Regulation VREF2 Power-Up VREF2 Long-Term Drift

150 3.5 100
RL = 5k RL = 5k 8 TYPICAL PARTS
3.0 CL = 1µF
75
100
2.5
VREF2 (V)

VREF2 50
CHANGE IN VREF2 (ppm)

CHANGE IN VREF2 (ppm)

2.0
50
1.5 25

0 1.0 0
0.5
–25
–50
0
125°C CSB –50
85°C 5
–100
25°C –75
CSB

0
–45°C
–150 –5 680412 G32
–100
4.5 4.75 5 5.25 5.5 1ms/DIV 0 500 1000 1500 2000 2500 3000
VREG (V) TIME (HOURS)
680412 G31 680412 G33

VREF2 Hysteresis, Hot VREF2 Hysteresis, Cold VREF2 Change Due to IR Reflow
25 16 30
TA = 85°C TO 25°C TA = –45°C TO 25°C 260°C, 1 CYCLE
14
25
20
12
NUMBER OF PARTS
NUMBER OF PARTS

NUMBER OF PARTS

20
15 10

8 15
10 6
10
4
5
5
2

0 0 0
–125 –75 –25 25 75 125 175 –250 –200 –150 –100 –50 0 50 100 –700 –500 –300 –100 100 300
CHANGE IN REF2 (ppm) CHANGE IN REF2 (ppm) CHANGE IN REF2 (ppm)
680412 G34 680412 G35 680412 G36

680412fc

For more information www.linear.com/LTC6804-1 13

LTC6804-1/LTC6804-2
Typical Performance Characteristics TA = 25°C, unless otherwise noted.

Discharge Switch On-Resistance

vs Cell Voltage Drive Pin Load Regulation Drive Pin Line Regulation
50 0 10
ON-RESISTANCE OF INTERNAL V+ = 39.6V
DISCHARGE SWITCH ON-RESISTANCE (Ω)

45 DISCHARGE SWITCH MEASURED

CHANGE IN DRIVE PIN VOLTAGE (mV)

CHANGE IN DRIVE PIN VOLTAGE (mV)
40 WITH 100Ω. EXTERNAL DISCHARGE
–20 5
RESISTOR BETWEEN S(n) and C(n)
35
30 –40 0
25
20 –60 –5
15
125°C 125°C 125°C
10 85°C –80 –10 85°C
85°C
5 25°C 25°C 25°C
–45°C –45°C –45°C
0 –100 –15
1 2 3 4 5 0.01 0.1 1 5 15 25 35 45 55 65 75
CELL VOLTAGE (V) ILOAD (mA) V+ (V)
680412 G37 680412 G38 680412 G39

Drive and VREG Pin Power-Up VREF1 Power-Up VREF1 vs Temperature

6 3.5 3.155
CL = 1µF 5 TYPICAL
3.0 3.154
5
2.5 3.153
VREF1 (V)

4 2.0 3.152
VDRIVE AND VREG (V)

VDRIVE VREG VREF1

1.5 3.151
VREF1 (V)
3
1.0 3.150
2 3.149
0.5

1 3.148
CSB
VREG: CL = 1µF 5 3.147
0
VREG GENERATED FROM
CSB

0 3.146
DRIVE PIN, FIGURE 28
–1 –5 3.145
680412 G40
100µs/DIV 1ms/DIV 680412 G41
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
680412 G42

Internal Die Temperature isoSPI Current (READY) isoSPI Current (READY/ACTIVE)

Increase vs Discharge Current vs Temperature vs isoSPI Clock Frequency
50 9 14
IB = 1mA ISOMD = VREG
45 IB = 1mA
LT6804-1
INCREASE IN DIE TEMPERATURE (°C)

12
40 8 ISOMD = VREG
LTC6804-1
isoSPI CURRENT (mA)
isoSPI CURRENT (mA)

35 10
12 CELLS DISCHARGING
30 7
6 CELLS DISCHARGING 8
25
6 LTC6804-2
20 6
15 LT6804-2 4
10 1 CELL 5 ISOMD = VREG
DISCHARGING 2
5 WRITE
LT6804-1, ISOMD = 0 READ
0 4 0
0 20 40 60 80 –50 –25 0 25 50 75 100 125 0 200 400 600 800 1000
INTERNAL DISCHARGE CURRENT (mA PER CELL) TEMPERATURE (°C) isoSPI CLOCK FREQUENCY (kHz)
680412 G43 680412 G44 680412 G45

680412fc

14 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Typical Performance Characteristics TA = 25°C, unless otherwise noted.

isoSPI Driver Current Gain

IBIAS Voltage vs Temperature IBIAS Voltage Load Regulation (Port A/PortB) vs Bias Current
2.02 2.010 23
IB = 1mA
3 PARTS
22
2.01 2.005

CURRENT GAIN (mA/mA)

IBIAS PIN VOLTAGE (V)
IBIAS PIN VOLTAGE (V)

21
2.00 2.000
20

1.99 1.995
19 VA = 0.5V
VA = 1.0V
VA = 1.6V
1.98 1.990 18
–50 –25 0 25 50 75 100 125 0 200 400 600 800 1000 0 200 400 600 800 1000
TEMPERATURE (°C) BIAS CURRENT (µA) BIAS CURRENT (µA)
680412 G46 408912 G47 680412 G48

isoSPI Driver Common Mode isoSPI Comparator Threshold

isoSPI Driver Current Gain Voltage (Port A/Port B) vs Pulse Gain (Port A/Port B) vs Common
(Port A/PortB) vs Temperature Amplitude Mode
23 5.5 0.56

COMPARATOR THRESHOLD GAIN (V/V)

5.0 0.54
22
DRIVER COMMON MODE (V)

IB = 100µA IB = 100µA
CURRENT GAIN (mA/mA)

4.5 0.52
21 IB = 1mA VICMP = 1V
4.0 0.50
IB = 1mA
20
3.5 0.48 VICMP = 0.2V

19
3.0 0.46

18 2.5 0.44
–50 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TEMPERATURE (°C) PULSE AMPLITUDE (V) COMMON MODE VOLTAGE (V)
680412 G49 680412 G50 680412 G51

isoSPI Comparator Threshold

Gain (Port A/Port B) vs ICMP Typical Wake-Up Pulse Amplitude
Voltage (Port A) vs Dwell Time
0.56 300
3 PARTS
WAKE-UP PULSE AMPLITUDE, VWAKE (mV)
COMPARATOR THRESHOLD GAIN (V/V)

0.54 GUARANTEED
250
WAKE-UP REGION
0.52
200
0.50
150
0.48

100
0.46

0.44 50
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 150 300 450 600
ICMP VOLTAGE (V) WAKE-UP DWELL TIME, tDWELL (ns)
680412 G52 680412 G53

680412fc

For more information www.linear.com/LTC6804-1 15

LTC6804-1/LTC6804-2
Typical Performance Characteristics TA = 25°C, unless otherwise noted.

Write Command to a Daisy-Chained Write Command to a Daisy-Chained

Device (ISOMD = 0) Device (ISOMD = 1)
CSB
5V/DIV
IPA-IMA
SDI
1V/DIV
5V/DIV
PORT A (PORT A)
SCK
5V/DIV
SDO
5V/DIV IPB-IMB
1V/DIV
IPB-IMB (PORT B)
2V/DIV
(PORT B) 680412 G54
1µs/DIV 1µs/DIV
680412 G55

ISOMD = V– ISOMD = VREG

BEGINNING OF A COMMAND BEGINNING OF A COMMAND

Data Read-Back from a Daisy-Chained Data Read-Back from a Daisy-Chained

Device (ISOMD = 0) Device (ISOMD = 1)
CSB
5V/DIV IPA-IMA
SDI 1V/DIV
5V/DIV (PORT A)
PORT A SCK
5V/DIV
SDO IPB-IMB
5V/DIV 1V/DIV
IPB-IMB (PORT B)
2V/DIV
(PORT B) 680412 G57
1µs/DIV
680412 G56
1µs/DIV
ISOMD = V– ISOMD = VREG
END OF A READ COMMAND END OF A READ COMMAND

680412fc

16 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Pin Functions
C0 to C12: Cell Inputs. Serial Port Pins
S1 to S12: Balance Inputs/Outputs. 12 N-MOSFETs are LTC6804-1 LTC6804-2
(DAISY-CHAINABLE) (ADDRESSABLE)
connected between S(n) and C(n – 1) for discharging cells.
ISOMD = VREG ISOMD = V– ISOMD = VREG ISOMD = V–
V+: Positive Supply Pin. PORT B IPB IPB A3 A3
(Pins 45
V–: Negative Supply Pins. The V– pins must be shorted to 48)
IMB IMB A2 A2
together, external to the IC. ICMP ICMP A1 A1
IBIAS IBIAS A0 A0
VREF2: Buffered 2nd reference voltage for driving multiple PORT A (NC) SDO IBIAS SDO
10k thermistors. Bypass with an external 1µF capacitor. (Pins 41 (NC) SDI ICMP SDI
to 44)
VREF1: ADC Reference Voltage. Bypass with an external IPA SCK IPA SCK
1µF capacitor. No DC loads allowed. IMA CSB IMA CSB

GPIO[1:5]: General Purpose I/O. Can be used as digital

CSB, SCK, SDI, SDO: 4-Wire Serial Peripheral Interface
inputs or digital outputs, or as analog inputs with a mea-
(SPI). Active low chip select (CSB), serial clock (SCK),
surement range from V– to 5V. GPIO [3:5] can be used
and serial data in (SDI) are digital inputs. Serial data out
as an I2C or SPI port.
(SDO) is an open drain NMOS output pin. SDO requires
SWTEN: Software Timer Enable. Connect this pin to VREG a 5k pull-up resistor.
to enable the software timer.
A0 to A3: Address Pins. These digital inputs are connected
DRIVE: Connect the base of an NPN to this pin. Connect to VREG or V– to set the chip address for addressable se-
the collector to V+ and the emitter to VREG. rial commands.
VREG: 5V Regulator Input. Bypass with an external 1µF IPA, IMA: Isolated 2-Wire Serial Interface Port A. IPA
capacitor. (plus) and IMA (minus) are a differential input/output pair.
ISOMD: Serial Interface Mode. Connecting ISOMD to IPB, IMB: Isolated 2-Wire Serial Interface Port B. IPB
VREG configures Pins 41 to 44 of the LTC6804 for 2-wire (plus) and IMB (minus) are a differential input/output pair.
isolated interface (isoSPI) mode. Connecting ISOMD to
IBIAS: Isolated Interface Current Bias. Tie IBIAS to
V– configures the LTC6804 for 4-wire SPI mode.
V– through a resistor divider to set the interface output
WDT: Watchdog Timer Output Pin. This is an open drain current level. When the isoSPI interface is enabled, the
NMOS digital output. It can be left unconnected or con- IBIAS pin voltage is 2V. The IPA/IMA or IPB/IMB output
nected with a 1M resistor to VREG. If the LTC6804 does not current drive is set to 20 times the current, IB, sourced
receive a wake-up signal (see Figure 21) within 2 seconds, from the IBIAS pin.
the watchdog timer circuit will reset the LTC6804 and the
ICMP: Isolated Interface Comparator Voltage Threshold
WDT pin will go high impedance.
Set. Tie this pin to the resistor divider between IBIAS
and V– to set the voltage threshold of the isoSPI receiver
comparators. The comparator thresholds are set to 1/2
the voltage on the ICMP pin.

680412fc

For more information www.linear.com/LTC6804-1 17

LTC6804-1/LTC6804-2
Block Diagram
LTC6804-1

V+ IPB
1 48
C12 IMB
2 47
S12 VREGD POR VREG ICMP
3 46
C12
C11 IBIAS
C11
4 C10
P + 45
6-CELL
S11 C9 ADC2 SERIAL I/O SDO/(NC)
MUX
C8 16 PORT B
5
C7
M – 44
C10 LOGIC SDI/(NC)
DIGITAL
6 C6 AND 43
FILTERS
MEMORY
S10 SCK/(IPA)
C5
7 C4
P + SERIAL I/O 42
6-CELL PORT A
C9 C3 ADC1 CSB/(IMA)
MUX
C2 16
8
C1
M – 41
S9 C0 ISOMD
9 40
C8 WDT
10 39
S8 DRIVE
11 12 BALANCE FETs 38
C7 S(n) VREG
12 VREGD 37
SOC
S7 C(n – 1) VREG SWTEN
13 SOFTWARE 36
P TIMER
C6 VREF1
AUX
14 MUX 35
S6 M VREF2
15 34
REGULATORS
C5 GPIO5
16 V+ 33
LDO2
S5 GPIO4
DRIVE
17 32
V+ DIE
C4 TEMPERATURE V–
LDO1 VREGD
18 31
POR
S4 2ND V–*
REFERENCE
19 30
C3 GPIO3
20 29
1ST
S3 REFERENCE GPIO2
21 28
C2 GPIO1
22 27
S2 C0
23 26
C1 S1
24 25

680412 BD1

680412fc

18 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Block Diagram
LTC6804-2

V+ A4
1 48
C12 A3
2 47
S12 VREGD POR VREG A2
3 46
C12
C11 A1
C11
4 C10
P + 45
6-CELL
S11 C9 ADC2 SERIAL I/O SDO/(IBIAS)
MUX
C8 16 ADDRESS
5
C7
M – 44
C10 LOGIC SDI/(ICMP)
DIGITAL
6 C6 AND 43
FILTERS
MEMORY
S10 SCK/(IPA)
C5
7 C4
P + SERIAL I/O 42
6-CELL PORT A
C9 C3 ADC1 CSB/(IMA)
MUX
C2 16
8
C1
M – 41
S9 C0 ISOMD
9 40
C8 WDT
10 39
S8 DRIVE
11 12 BALANCE FETs 38
C7 S(n) VREG
12 VREGD 37
SOC
S7 C(n – 1) VREG SWTEN
13 SOFTWARE 36
P TIMER
C6 VREF1
AUX
14 MUX 35
S6 M VREF2
15 34
REGULATORS
C5 GPIO5
16 V+ 33
LDO2
S5 GPIO4
DRIVE
17 32
V+ DIE
C4 TEMPERATURE V–
LDO1 VREGD
18 31
POR
S4 2ND V–*
REFERENCE
19 30
C3 GPIO3
20 29
1ST
S3 REFERENCE GPIO2
21 28
C2 GPIO1
22 27
S2 C0
23 26
C1 S1
24 25

680412 BD2

680412fc

For more information www.linear.com/LTC6804-1 19

LTC6804-1/LTC6804-2
Operation
State Diagram returns to the SLEEP state. If the software discharge timer
The operation of the LTC6804 is divided into two separate is disabled, only the watchdog timer is relevant.
sections: the core circuit and the isoSPI circuit. Both sec-
REFUP State
tions have an independent set of operating states, as well
as a shutdown timeout. To reach this state the REFON bit in the Configuration Reg-
ister Group must be set to 1 (using the WRCFG command,
LTC6804 Core State Descriptions see Table 36). The ADCs are off. The reference is powered
up so that the LTC6804 can initiate ADC conversions more
SLEEP State quickly than from the STANDBY state.

The reference and ADCs are powered down. The watchdog When a valid ADC command is received, the IC goes to the
timer (see Watchdog and Software Discharge Timer) has MEASURE state to begin the conversion. Otherwise, the
timed out. The software discharge timer is either disabled LTC6804 will return to the STANDBY state when the REFON
or timed out. The supply currents are reduced to minimum bit is set to 0, either manually (using WRCFG command)
levels. The isoSPI ports will be in the IDLE state. or automatically when the watchdog timer expires. (The
LTC6804 will then move straight into the SLEEP state if
If a WAKEUP signal is received (see Waking Up the Serial both timers are expired).
Interface), the LTC6804 will enter the STANDBY state.
MEASURE State
STANDBY State
The LTC6804 performs ADC conversions in this state. The
The reference and the ADCs are off. The watchdog timer reference and ADCs are powered up.
and/or the software discharge timer is running. The DRIVE
pin powers the VREG pin to 5V through an external transistor. After ADC conversions are complete the LTC6804 will
(Alternatively, VREG can be powered by an external supply). transition to either the REFUP or STANDBY states, de-
pending on the REFON bit. Additional ADC conversions
When a valid ADC command is received or the REFON bit is can be initiated more quickly by setting REFON = 1 to take
set to 1 in the Configuration Register Group, the IC pauses advantage of the REFUP state.
for tREFUP to allow for the reference to power up and then
enters either the REFUP or MEASURE state. If there is no Note: Non-ADC commands do not cause a Core state tran-
WAKEUP signal for a duration tSLEEP (when both the watch- sition. Only an ADC conversion or diagnostic commands
dog and software discharge timer have expired) the LTC6804 will place the Core in the MEASURE state.

CORE LTC6804 isoSPI PORT

SLEEP IDLE

WD TIMEOUT WAKEUP WAKEUP SIGNAL WAKEUP SIGNAL

OR SWT TIMEOUT SIGNAL IDLE TIMEOUT (CORE = SLEEP) (CORE = STANDBY)
(tSLEEP) (tWAKE) (tIDLE) (tWAKE) (tREADY)

STANDBY READY

REFON = 0 REFON = 1 ADC COMMAND CONVERSION

(tREFUP) (tREFUP) DONE (REFON = 0)
NO ACTIVITY ON TRANSMIT/RECEIVE
ADC isoSPI PORT
COMMAND

REFUP MEASURE ACTIVE

NOTE: STATE TRANSITION
CONVERSION DONE DELAYS DENOTED BY (tX)
(REFON = 1) 680412 F01

Figure 1. LTC6804 Operation State Diagram

680412fc

20 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
isoSPI State Descriptions DRIVE output pin. Alternatively, VREG can be powered by
an external supply.
Note: The LTC6804-1 has two isoSPI ports (A and B), for
daisy-chain communication. The LTC6804-2 has only one The power consumption varies according to the opera-
isoSPI port (A), for parallel-addressable communication. tional states. Table 1 and Table 2 provide equations to
approximate the supply pin currents in each state. The V+
IDLE State pin current depends only on the Core state and not on the
The isoSPI ports are powered down. isoSPI state. However, the VREG pin current depends on
both the Core state and isoSPI state, and can therefore be
When isoSPI port A receives a WAKEUP signal (see Wak- divided into two components. The isoSPI interface draws
ing Up the Serial Interface), the isoSPI enters the READY current only from the VREG pin.
state. This transition happens quickly (within tREADY) if
the Core is in the STANDBY state because the DRIVE and IREG = IREG(CORE) + IREG(isoSPI)
VREG pins are already biased up. If the Core is in the SLEEP Table 1. Core Supply Current
state when the isoSPI receives a WAKEUP signal, then it STATE IV+ IREG(CORE)
transitions to the READY state within tWAKE. VREG = 0V 3.8µA 0µA
SLEEP
VREG = 5V 1.6µA 2.2µA
READY State
STANDBY 32µA 35µA
The isoSPI port(s) are ready for communication. Port REFUP 550µA 450µA
B is enabled only for LTC6804-1, and is not present on MEASURE 550µA 11.5mA
the LTC6804-2. The serial interface current in this state
depends on if the part is LTC6804-1 or LTC6804-2, the In the SLEEP state the VREG pin will draw approximately
status of the ISOMD pin, and RBIAS = RB1 + RB2 (the 2.2µA if powered by a external supply. Otherwise, the V+
external resistors tied to the IBIAS pin). pin will supply the necessary current.
If there is no activity (i.e., no WAKEUP signal) on port A
for greater than tIDLE = 5.5ms, the LTC6804 goes to the ADC Operation
IDLE state. When the serial interface is transmitting or There are two ADCs inside the LTC6804. The two ADCs
receiving data the LTC6804 goes to the ACTIVE state. operate simultaneously when measuring twelve cells. Only
one ADC is used to measure the general purpose inputs.
ACTIVE State The following discussion uses the term ADC to refer to
The LTC6804 is transmitting/receiving data using one or one or both ADCs, depending on the operation being
both of the isoSPI ports. The serial interface consumes performed. The following discussion will refer to ADC1
maximum power in this state. The supply current increases and ADC2 when it is necessary to distinguish between the
with clock frequency as the density of isoSPI pulses two circuits, in timing diagrams, for example.
increases.
ADC Modes
Power Consumption The ADCOPT bit (CFGR0[0]) in the configuration register
group and the mode selection bits MD[1:0] in the conver-
The LTC6804 is powered via two pins: V+ and VREG. The
sion command together provide 6 modes of operation for
V+ input requires voltage greater than or equal to the top
the ADC which correspond to different over sampling ratios
cell voltage, and it provides power to the high voltage
(OSR). The accuracy of these modes are summarized in
elements of the core circuitry. The VREG input requires
Table 3. In each mode, the ADC first measures the inputs,
5V and provides power to the remaining core circuitry
and then performs a calibration of each channel. The
and the isoSPI circuitry. The VREG input can be powered
names of the modes are based on the –3dB bandwidth
through an external transistor, driven by the regulated
of the ADC measurement.
680412fc

For more information www.linear.com/LTC6804-1 21

LTC6804-1/LTC6804-2
Operation
Table 2. isoSPI Supply Current Equations
ISOMD
isoSPI STATE DEVICE CONNECTION IREG(isoSPI)
IDLE LTC6804-1/LTC6804-2 N/A 0mA
READY LTC6804-1 VREG 2.8mA + 5 • IB Note: IB = VBIAS/(RB1 + RB2)
V– 1.6mA + 3 • IB
LTC6804-2 VREG 1.8mA + 3 • IB
V– 0mA
ACTIVE LTC6804-1 VREG 1µs
Write: 2.8mA + 5 •IB + ( 2 •IB + 0.4mA ) •
tCLK
1µs
Read: 2.8mA + 5 •IB + ( 3 •IB + 0.5mA ) •
tCLK

V– 1µs
1.6mA+ 3 •IB + ( 2 •IB + 0.2mA ) •
tCLK
LTC6804-2 VREG 1µs
Write: 1.8mA + 3 •IB + ( 0.3mA ) •
tCLK
1µs
Read: 1.8mA + 3 •IB + (IB + 0.3mA ) •
tCLK

V– 0mA

Table 3. ADC Filter Bandwidth and Accuracy

MODE –3dB FILTER BW –40dB FILTER BW TME SPEC AT 3.3V, 25°C TME SPEC AT 3.3V,–40°C, 125°C
27kHz (Fast Mode) 27kHz 84kHz ±4.7mV ±4.7mV
14kHz 13.5kHz 42kHz ±4.7mV ±4.7mV
7kHz (Normal Mode) 6.8kHz 21kHz ±1.2mV ±2.2mV
3kHz 3.4kHz 10.5kHz ±1.2mV ±2.2mV
2kHz 1.7kHz 5.3kHz ±1.2mV ±2.2mV
26Hz (Filtered Mode) 26Hz 82Hz ±1.2mV ±2.2mV
Note: TME is the total measurement error.

Mode 7kHz (Normal): Mode 26Hz (Filtered):

In this mode, the ADC has high resolution and low TME In this mode, the ADC digital filter –3dB frequency is
(total measurement error). This is considered the normal lowered to 26Hz by increasing the OSR. This mode is
operating mode because of the optimum combination of also referred to as the filtered mode due to its low –3dB
speed and accuracy. frequency. The accuracy is similar to the 7kHz (Normal)
mode with lower noise.
Mode 27kHz (Fast):
In this mode, the ADC has maximum throughput but has Modes 14kHz, 3kHz and 2kHz:
some increase in TME (total measurement error). So this Modes 14kHz, 3kHz and 2kHz provide additional options to
mode is also referred to as the fast mode. The increase set the ADC digital filter –3dB frequency at 13.5kHz, 3.4kHz
in speed comes from a reduction in the oversampling and 1.7kHz respectively. The accuracy of the 14kHz mode
ratio. This results in an increase in noise and average is similar to the 27kHz (fast) mode. The accuracy of 3kHz
measurement error. and 2kHz modes is similar to the 7kHz (normal) mode.
680412fc

22 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
The conversion times for these modes are provided in 1.0
NORMAL MODE
Table 5. If the core is in STANDBY state, an additional 0.9 FILTERED MODE

tREFUP time is required to power up the reference before 0.8

beginning the ADC conversions. The reference can remain 0.7

PEAK NOISE (mV)

0.6
powered up between ADC conversions if the REFON bit
0.5
in Configuration Register Group is set to 1 so the core is
0.4
in REFUP state after a delay tREFUP. Then, the subsequent 0.3
ADC commands will not have the tREFUP delay before 0.2
beginning ADC conversions. 0.1
0
ADC Range and Resolution 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ADC INPUT VOLTAGE (V)
The C inputs and GPIO inputs have the same range and
680412 F02

resolution. The ADC inside the LTC6804 has an approximate Figure 2. Measurement Noise vs Input Voltage
range from –0.82V to 5.73V. Negative readings are rounded
to 0V. The format of the data is a 16-bit unsigned integer free resolution. For example, 14-bit noise free resolution
where the LSB represents 100µV. Therefore, a reading of in normal mode implies that the top 14 bits will be noise
0x80E8 (33,000 decimal) indicates a measurement of 3.3V. free with a DC input, but that the 15th and 16th least
significant bits (LSB) will flicker.
Delta-Sigma ADCs have quantization noise which depends
on the input voltage, especially at low over sampling ratios ADC Range vs Voltage Reference Value:
(OSR), such as in FAST mode. In some of the ADC modes,
Typical Delta-Sigma ADC’s have a range which is exactly
the quantization noise increases as the input voltage ap-
twice the value of the voltage reference, and the ADC
proaches the upper and lower limits of the ADC range.
measurement error is directly proportional to the error
For example, the total measurement noise versus input
in the voltage reference. The LTC6804 ADC is not typi-
voltage in normal and filtered modes is shown in Figure 2.
cal. The absolute value of VREF1 is trimmed up or down
The specified range of the ADC is 0V to 5V. In Table 4, the to compensate for gain errors in the ADC. Therefore, the
precision range of the ADC is arbitrarily defined as 0.5V ADC total measurement error (TME) specifications are
to 4.5V. This is the range where the quantization noise superior to the VREF1 specifications. For example, the
is relatively constant even in the lower OSR modes (see 25°C specification of the total measurement error when
Figure 2). Table 4 summarizes the total noise in this range measuring 3.300V in 7kHz (normal) mode is ±1.2mV and
for all six ADC operating modes. Also shown is the noise the 25°C specification for VREF1 is 3.200V ±100mV.

Table 4. ADC Range and Resolution

SPECIFIED PRECISION NOISE FREE
MODE FULL RANGE1 RANGE RANGE2 LSB FORMAT MAX NOISE RESOLUTION3
27kHz (Fast) ±4mVP-P 10 Bits
14kHz ±1mVP-P 12 Bits
7kHz (Normal) –0.8192V to ±250µVP-P 14 Bits
0V to 5V 0.5V to 4.5V 100µV Unsigned 16 Bits
3kHz 5.7344V ±150µVP-P 14 Bits
2kHz ±100µVP-P 15 Bits
26Hz (Filtered) ±50µVP-P 16 Bits
1. Negative readings are rounded to 0V.
2. PRECISION RANGE is the range over which the noise is less than MAX NOISE.
3. NOISE FREE RESOLUTION is a measure of the noise level within the PRECISION RANGE.

680412fc

For more information www.linear.com/LTC6804-1 23

LTC6804-1/LTC6804-2
Operation
Measuring Cell Voltages (ADCV Command) tREFUP

The ADCV command initiates the measurement of the SERIAL

INTERFACE
ADCV + PEC

battery cell inputs, pins C0 through C12. This command MEASURE CALIBRATE
ADC2
has options to select the number of channels to measure C10 TO C9 C10 TO C9

and the ADC mode. See the section on Commands for the ADC1
MEASURE
C4 TO C3
CALIBRATE
C4 TO C3
ADCV command format.
t0 t1M t1C

Figure 3 illustrates the timing of ADCV command which 680412 F04

measures all twelve cells. After the receipt of the ADCV Figure 4. Timing for ADCV Command Measuring 2 Cells
command to measure all 12 cells, ADC1 sequentially
measures the bottom 6 cells. ADC2 sequentially measures Table 6. Conversion Times for ADCV Command Measuring Only 2
the top 6 cells. After the cell measurements are complete, Cells in Different Modes
each channel is calibrated to remove any offset errors. CONVERSION TIMES (in µs)
MODE t0 t1M t1C
Table 5 shows the conversion times for the ADCV com-
27kHz 0 57 201
mand measuring all 12 cells. The total conversion time is
14kHz 0 86 230
given by t6C which indicates the end of the calibration step.
7kHz 0 144 405
Figure 4 illustrates the timing of the ADCV command that 3kHz 0 260 521
measures only two cells. 2kHz 0 493 754
Table 6 shows the conversion time for ADCV command 26Hz 0 29,817 33,568
measuring only 2 cells. t1C indicates the total conversion
time for this command.

tCYCLE
tREFUP
tSKEW2

SERIAL ADCV + PEC

INTERFACE

MEASURE MEASURE MEASURE CALIBRATE CALIBRATE CALIBRATE

ADC2
C7 TO C6 C8 TO C7 C12 TO C11 C7 TO C6 C8 TO C7 C12 TO C11

MEASURE MEASURE MEASURE CALIBRATE CALIBRATE CALIBRATE

ADC1
C1 TO C0 C2 TO C1 C6 TO C5 C1 TO C0 C2 TO C1 C6 TO C5

t0 t1M t2M t5M t6M t1C t2C t5C t6C

680412 F03

Figure 3. Timing for ADCV Command Measuring All 12 Cells

Table 5. Conversion Times for ADCV Command Measuring All 12 Cells in Different Modes
CONVERSION TIMES (in µs)
MODE t0 t1M t2M t5M t6M t1C t2C t5C t6C
27kHz 0 57 103 243 290 432 568 975 1,113
14kHz 0 86 162 389 465 606 742 1,149 1,288
7kHz 0 144 278 680 814 1,072 1,324 2,080 2,335
3kHz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033
2kHz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430
26Hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317

680412fc

24 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Under/Overvoltage Monitoring by connecting the temperature sensors to the GPIOs.
Whenever the C inputs are measured, the results are com- These sensors can be powered from the 2nd reference
pared to undervoltage and overvoltage thresholds stored which is also measured by the ADAX command, resulting
in memory. If the reading of a cell is above the overvoltage in precise ratiometric measurements.
limit, a bit in memory is set as a flag. Similarly, measure- Figure 5 illustrates the timing of the ADAX command
ment results below the undervoltage limit cause a flag to measuring all GPIOs and the 2nd reference. Since all
be set. The overvoltage and undervoltage thresholds are the 6 measurements are carried out on ADC1 alone, the
stored in the configuration register group. The flags are conversion time for the ADAX command is similar to the
stored in the status register group B. ADCV command.

Auxiliary (GPIO) Measurements (ADAX Command) Measuring Cell Voltages and GPIOs (ADCVAX
The ADAX command initiates the measurement of the Command)
GPIO inputs. This command has options to select which The ADCVAX command combines twelve cell measure-
GPIO input to measure (GPIO1-5) and which ADC mode. ments with two GPIO measurements (GPIO1 and GPIO2).
The ADAX command also measures the 2nd reference. This command simplifies the synchronization of battery
There are options in the ADAX command to measure each cell voltage and current measurements when current sen-
GPIO and the 2nd reference separately or to measure all 5 sors are connected to GPIO1 or GPIO2 inputs. Figure 6
GPIOs and the 2nd reference in a single command. See the illustrates the timing of the ADCVAX command. See the
section on commands for the ADAX command format. All section on commands for the ADCVAX command format.
auxiliary measurements are relative to the V– pin voltage. The synchronization of the current and voltage measure-
This command can be used to read external temperature ments, tSKEW1, in FAST MODE is within 208µs.

tCYCLE
tREFUP
tSKEW

SERIAL ADAX + PEC

INTERFACE

ADC2

MEASURE MEASURE MEASURE CALIBRATE CALIBRATE CALIBRATE

ADC1
GPIO1 GPIO2 2ND REF GPIO1 GPIO2 2ND REF

t0 t1M t2M t5M t6M t1C t2C t5C t6C

680412 F05

Figure 5. Timing for ADAX Command Measuring All GPIOs and 2nd Reference

Table 7. Conversion Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes
CONVERSION TIMES (in µs)
MODE t0 t1M t2M t5M t6M t1C t2C t5C t6C
27kHz 0 57 103 243 290 432 568 975 1,113
14kHz 0 86 162 389 465 606 742 1,149 1,288
7kHz 0 144 278 680 814 1,072 1,324 2,080 2,335
3kHz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033
2kHz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430
26Hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317

680412fc

For more information www.linear.com/LTC6804-1 25

LTC6804-1/LTC6804-2
Operation
tCYCLE
tREFUP
tSKEW1
tSKEW1
SERIAL ADCVAX + PEC
INTERFACE

MEASURE MEASURE MEASURE MEASURE MEASURE MEASURE

ADC2 CALIBRATE
C7 TO C6 C8 TO C7 C9 TO C8 C10 TO C9 C11 TO C10 C12 TO C11

MEASURE MEASURE MEASURE MEASURE MEASURE MEASURE MEASURE MEASURE

ADC1 CALIBRATE
C1 TO C0 C2 TO C1 C3 TO C2 GPIO1 GPIO2 C4 TO C3 C5 TO C4 C6 TO C5

t0 t1M t2M t3M t4M t5M t6M t7M t8M t8C

680412 F06

Figure 6. Timing of ADCVAX Command

Table 8. Conversion and Synchronization Times for ADCVAX Command in Different Modes
SYNCHRONIZATION
CONVERSION TIMES (in µs) TIME (µs)
MODE t0 t1M t2M t3M t4M t5M t6M t7M t8M t8C tSKEW1
27kHz 0 57 106 155 216 265 326 375 424 1,564 208
14kHz 0 86 161 237 320 396 479 555 630 1,736 310
7kHz 0 144 278 412 553 687 828 962 1,096 3,133 543
3kHz 0 260 511 761 1,018 1,269 1,526 1,777 2,027 4,064 1009
2kHz 0 493 976 1,459 1,949 2,432 2,923 3,406 3,888 5,925 1939
26Hz 0 29,817 59,623 89,430 119,244 149,051 178,864 208,671 238,478 268,442 119234

Table 8 shows the conversion and synchronization time Measuring Internal Device Parameters (ADSTAT
for the ADCVAX command in different modes. The total Command)
conversion time for the command is given by t8C.
The ADSTAT command is a diagnostic command that
measures the following internal device parameters: sum
Data Acquisition System Diagnostics of all cells (SOC), internal die temperature (ITMP), analog
The battery monitoring data acquisition system is com- power supply (VA) and the digital power supply (VD).
prised of the multiplexers, ADCs, 1st reference, digital These parameters are described in the section below. All
filters, and memory. To ensure long term reliable perfor- 6 ADC modes are available for these conversions. See the
mance there are several diagnostic commands which can section on commands for the ADSTAT command format.
be used to verify the proper operation of these circuits. Figure 7 illustrates the timing of the ADSTAT command
measuring all 4 internal device parameters.

tCYCLE
tREFUP
tSKEW

SERIAL ADSTAT + PEC

INTERFACE

ADC2

MEASURE MEASURE MEASURE CALIBRATE CALIBRATE CALIBRATE

ADC1
SOC ITMP VD SOC ITMP VD

t0 t1M t2M t3M t4M t1C t2C t3C t4C

680412 F07

Figure 7. Timing for ADSTAT Command Measuring SOC, ITMP, VA, VD

680412fc

26 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Table 9 shows the conversion time of the ADSTAT com- Issuing an ADSTAT command with CHST = 100 runs an
mand measuring all 4 internal parameters. t4C indicates ADC measurement of just the digital supply (VREGD). This
the total conversion time for the ADSTAT command. is not recommended following an ADCV command. With
large cell voltages, running the ADSTAT command with
Sum of Cells Measurement: The sum of all cells measurement
CST = 100 following an ADCV command with CH = 000
is the voltage between C12 and C0 with a 20:1 attenuation.
(all cells) can cause the LTC6804 to perform a power on
The 16-bit ADC value of sum of cells measurement (SOC)
reset. If using the ADSTAT command with CHST = 100,
is stored in status register group A. Any potential differ-
ence between the CO and V– pins results in an error in the it is necessary to run an ADCV command with CH = 001
SOC measurement equal to this difference. From the SOC prior to running the ADSTAT command with CHST = 100.
value, the sum of all cell voltage measurements is given by: This charges the high voltage multiplexer to a low poten-
tial before the VREGD measurement is executed. To save
Sum of all Cells = SOC • 20 • 100µV time, this sacrificial ADCV command run prior to running
Internal Die Temperature: The ADSTAT command can the VREGD measurement can be executed in FAST mode
measure the internal die temperature. The 16-bit ADC (MD = 01).
value of the die temperature measurement (ITMP) is
Accuracy Check
stored in status register group A. From ITMP the actual
die temperature is calculated using the expression: Measuring an independent voltage reference is the best
Internal Die Temperature (°C) = (ITMP) • 100µV/ means to verify the accuracy of a data acquisition system.
(7.5mV)°C – 273°C The LTC6804 contains a 2nd reference for this purpose.
The ADAX command will initiate the measurement of the
Power Supply Measurements: The ADSTAT command is 2nd reference. The results are placed in auxiliary register
also used to measure the analog power supply (VREG) and group B. The range of the result depends on the ADC
digital power supply (VREGD). measurement accuracy and the accuracy of the 2nd ref-
The 16-bit ADC value of the analog power supply measure- erence, including thermal hysteresis and long term drift.
ment (VA) is stored in Status Register Group A. The 16-bit Readings outside the range 2.985 to 3.015 indicate the
ADC value of the digital power supply measurement (VD) system is out of its specified tolerance.
is stored in status register group B. From VA and VD, the
power supply measurements are given by: MUX Decoder Check

Analog power supply measurement (VREG) = VA • 100µV The diagnostic command DIAGN ensures the proper op-
eration of each multiplexer channel. The command cycles
Digital power supply measurement (VREGD) = VD • 100µV through all channels and sets the MUXFAIL bit to 1 in
The nominal range of VREG is 4.5V to 5.5V. The nominal status register group B if any channel decoder fails. The
range of VREGD is 2.7V to 3.6V. MUXFAIL bit is set to 0 if the channel decoder passes the

Table 9. Conversion Times for ADSTAT Command Measuring SOC, ITMP, VA, VD
CONVERSION TIMES (in µs)
MODE t0 t1M t2M t3M t4M t1C t2C t3C t4C
27kHz 0 57 103 150 197 338 474 610 748
14kHz 0 86 162 237 313 455 591 726 865
7kHz 0 144 278 412 546 804 1,056 1,308 1,563
3kHz 0 260 511 761 1,011 1,269 1,522 1,774 2,028
2kHz 0 493 976 1,459 1,942 2,200 2,452 2,705 2,959
26Hz 0 29,817 59,623 89,430 119,237 122,986 126,729 130,472 134,218
680412fc

For more information www.linear.com/LTC6804-1 27

LTC6804-1/LTC6804-2
Operation
test. The MUXFAIL bit is also set to 1 on power-up (POR) test signal passes through the digital filter and is con-
or after a CLRSTAT command. verted to a 16-bit value. The 1-bit test signal undergoes
the same digital conversion as the regular 1-bit pulse
The DIAGN command takes about 400µs to complete if the
from the modulator, so the conversion time for any self
core is in REFUP state and about 4.5ms to complete if the
test command is exactly the same as the corresponding
core is in STANDBY state. The polling methods described
regular ADC conversion command. The 16-bit ADC value
in the section Polling Methods can be used to determine
is stored in the same register groups as the regular ADC
the completion of the DIAGN command.
conversion command. The test signals are designed to
Digital Filter Check place alternating one-zero patterns in the registers. Table
10 provides a list of the self test commands. If the digital
The delta-sigma ADC is composed of a 1-bit pulse den- filters and memory are working properly, then the registers
sity modulator followed by a digital filter. A pulse density will contain the values shown in Table 10. For more details
modulated bit stream has a higher percentage of 1s for see the section Commands.
higher analog input voltages. The digital filter converts
this high frequency 1-bit stream into a single 16-bit word. ADC Clear Commands
This is why a delta-sigma ADC is often referred to as an
oversampling converter. LTC6804 has 3 clear commands – CLRCELL, CLRAUX
and CLRSTAT. These commands clear the registers that
The self test commands verify the operation of the digital store all ADC conversion results.
filters and memory. Figure 8 illustrates the operation of
the ADC during self test. The output of the 1-bit pulse The CLRCELL command clears cell voltage register group
density modulator is replaced by a 1-bit test signal. The A, B, C and D. All bytes in these registers are set to 0xFF
by CLRCELL command.

PULSE DENSITY
MODULATED
BIT STREAM

ANALOG 1-BIT
MUX
INPUT MODULATOR 1 DIGITAL RESULTS
FILTER 16 REGISTER

SELF TEST TEST SIGNAL

PATTERN
GENERATOR
680412 F08

Figure 8. Operation of LTC6804 ADC Self Test

Table 10. Self Test Command Summary

SELF TEST RESULTS REGISTER
COMMAND OPTION OUTPUT PATTERN IN DIFFERENT ADC MODES GROUPS
27kHz 14kHz 7kHz 3kHz 2kHz 26Hz
CVST ST[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 C1V to C12V
ST[1:0]=10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA (CVA, CVB, CVC, CVD)

AXST ST[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 G1V to G5V, REF
ST[1:0]=10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA (AUXA, AUXB)

STATST ST[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 SOC, ITMP, VA, VD
ST[1:0]=10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA (STATA, STATB)
680412fc

28 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
The CLRAUX command clears auxiliary register group time to create a large enough difference for the algorithm
A and B. All bytes in these registers are set to 0xFF by to detect an open connection. This can be accomplished
CLRAUX command. by running more than two ADOW commands in steps 1
The CLRSTAT command clears status register group A and and 2, or by using filtered mode conversions instead of
B except the REVCODE and RSVD bits in status register normal mode conversions. Use Table 11 to determine how
group B. A read back of REVCODE will return the revision many conversions are necessary:
code of the part. All OV flags, UV flags, MUXFAIL bit, and Table 11
THSD bit in status register group B are set to 1 by CLR- Number of ADOW Commands Required in
STAT command. The THSD bit is set to 0 after RDSTATB Steps 1 and 2
command. The registers storing SOC, ITMP, VA and VD EXTERNAL C PIN
CAPACITANCE NORMAL MODE FILTERED MODE
are all set to 0xFF by CLRSTAT command.
≤10nF 2 2
Open-Wire Check (ADOW Command) 100nF 10 2
1µF 100 2
The ADOW command is used to check for any open wires C 1+ROUNDUP(C/10nF) 2
between the ADCs in the LTC6804 and the external cells.
This command performs ADC conversions on the C pin
inputs identically to the ADCV command, except two
LTC6804
internal current sources sink or source current into the 1 V+ V+ V+

two C pins while they are being measured. The pull-up 2

C12
100µA
+
(PUP) bit of the ADOW command determines whether the C11
4 PUP = 1
current sources are sinking or sourcing 100µA. +
C10
6
The following simple algorithm can be used to check for + ADC2
6-CELL
an open wire on any of the 13 C pins (see Figure 9): 8
C9
MUX
+ PUP = 0

1) Run the 12-cell command ADOW with PUP = 1 at least 10

C8
+ 100µA
twice. Read the cell voltages for cells 1 through 12 once C7
12
at the end and store them in array CELLPU(n). + C6 V– V–

2) Run the 12-cell command ADOW with PUP = 0 at least + 14

twice. Read the cell voltages for cells 1 through 12 once C6
V+ V+

at the end and store them in array CELLPD(n). 16

C5
100µA
+
3) Take the difference between the pull-up and pull-down 18
C4
PUP = 1
measurements made in above steps for cells 2-12: +
C3
CELL∆(n) = CELLPU(n) – CELLPD(n). +
20
ADC1
C2 6-CELL
4) For all values of n from 1 to 11: If CELL∆(n+1) < –400mV, +
22 MUX
PUP = 0
then C(n) is open. If the CELLPU(1) = 0.0000, then C(0) 24
C1
is open. If the CELLPD(12) = 0.0000, then C(12) is open. + 100µA
C0
26
The above algorithm detects open wires using normal mode 30
V– V–

conversions with as much as 10nF of capacitance remaining 31

on the LTC6804 side of the open wire. However, if more V–
external capacitance is on the open C pin, then the length 680412 F09

of time that the open wire conversions are ran in steps 1 Figure 9. Open-Wire Detection Circuitry
and 2 must be increased to give the 100µA current sources

680412fc

For more information www.linear.com/LTC6804-1 29

LTC6804-1/LTC6804-2
Operation
Thermal Shutdown Watchdog and Software Discharge Timer
To protect the LTC6804 from overheating, there is a thermal When there is no wake-up signal (see Figure 21) for more
shutdown circuit included inside the IC. If the temperature than 2 seconds, the watchdog timer expires. This resets
detected on the die goes above approximately 150°C, the configuration register bytes CFGR0-CFGR3 in all cases.
thermal shutdown circuit trips and resets the configura- CFGR4 and CFGR5 are reset by the watchdog timer when
tion register group to its default state. This turns off all the software timer is disabled. The WDT pin is pulled high
discharge switches. When a thermal shutdown event has by the external pull-up when the watchdog time elapses.
occurred, the THSD bit in status register group B will go The watchdog timer is always enabled and is reset by a
high. This bit is cleared after a read operation has been qualified wake-up signal.
performed on the status register group B (RDSTATB
The software discharge timer is used to keep the discharge
command). The CLRSTAT command sets the THSD bit
switches turned ON for programmable time duration. If
high for diagnostic purposes, but does not reset the
the software timer is being used, the discharge switches
configuration register group.
are not turned OFF when the watchdog timer is activated.
Revision Code and Reserved Bits To enable the software timer, SWTEN pin needs to be tied
The status register group B contains a 4-bit revision code high to VREG (Figure 10). The discharge switches can
now be kept ON for the programmed time duration that is
and 2 reserved bits. If software detection of device revision
determined by the DCTO value written to the configuration
is necessary, then contact the factory for details. Otherwise,
register. Table 12 shows the various time settings and the
the code can be ignored. In all cases, however, the values
corresponding DCTO value. Table 13 summarizes the status
of all bits must be used when calculating the packet error
of the configuration register group after a watchdog timer
code (PEC) on data reads.
or software timer event.

VREG
LTC6804
DCTEN
TIMEOUT 1
EN
DCTO > 0 SWTEN
SW TIMER
OSC 16Hz CLK
RST
2
(POR OR WRCFG DONE OR TIMEOUT)

RST1
(RESETS DCTO, DCC) WDTRST && ~DCTEN
WDT
RST2
(RESETS REFUP, VUV, VOV)
WDTPD
WATCHDOG
WDTRST
TIMER
OSC 16Hz CLK
RST

(POR OR VALID COMMAND)

680412 F10

Figure 10. Watchdog and Software Discharge Timer

Table 12. DCTO Settings

DCTO 0 1 2 3 4 5 6 7 8 9 A B C D E F
Time Min Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120

680412fc

30 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Table 13 Table 14
WATCHDOG TIMER SOFTWARE TIMER DCTO
(READ VALUE) TIME LEFT (MIN)
SWTEN = 0, DCTO = XXXX Resets CFGR0-5 Disabled
When It Activates 0 Disabled (or) Timer Has Timed Out
SWTEN = 1, DCTO = 0000 Resets CFGR0-5 Disabled 1 0 < Timer ≤ 0.5
When It Activates 2 0.5 < Timer ≤ 1
SWTEN = 1, DCTO ! = 0000 Resets CFGR0-3 Resets CFGR4-5 3 1 < Timer ≤ 2
When It Activates When It Fires
4 2 < Timer ≤ 3
Unlike the watchdog timer, the software timer does not 5 3 < Timer ≤ 4
reset when there is a valid command. The software timer 6 4 < Timer ≤ 5
can only be reset after a valid WRCFG (write configuration 7 5 < Timer ≤ 10
register) command. There is a possibility that the software 8 10 < Timer ≤ 15
timer will expire in the middle of some commands. 9 15 < Timer ≤ 20
A 20 < Timer ≤ 30
If software timer activates in the middle of WRCFG com-
B 30 < Timer ≤ 40
mand, the configuration register resets as per Table 14.
C 40 < Timer ≤ 60
However, at the end of the valid WRCFG command, the
D 60 < Timer ≤ 75
new data is copied to the configuration register. The new
E 75 < Timer ≤ 90
data is not lost when the software timer is activated.
F 90 < Timer ≤ 120
If software timer activates in the middle of RDCFG com-
mand, the configuration register group resets as per The GPIOs are open drain outputs, so an external pull-up
Table 14. As a result, the read back data from bytes CRFG4 is required on these ports to operate as an I2C or SPI
and CRFG5 could be corrupted. master. It is also important to write the GPIO bits to 1 in
the CFG register group so these ports are not pulled low
I2C/SPI Master on LTC6804 Using GPIOS internally by the device.
The I/O ports GPIO3, GPIO4 and GPIO5 on LTC6804-1 and COMM Register
LTC6804-2 can be used as an I2C or SPI master port to
communicate to an I2C or SPI slave. In the case of an I2C LTC6804 has a 6-byte COMM register as shown in Table 15.
master, GPIO4 and GPIO5 form the SDA and SCL ports of This register stores all data and control bits required for
the I2C interface respectively. In the case of a SPI master, I2C or SPI communication to a slave. The COMM register
GPIO3, GPIO5 and GPIO4 become the chip select (CSBM), contains 3 bytes of data Dn[7:0] to be transmitted to or
clock (SCKM) and data (SDIOM) ports of the SPI interface received from the slave device. ICOMn [3:0] specify con-
respectively. The SPI master on LTC6804 supports only trol actions before transmitting/receiving the data byte.
SPI mode 3 (CHPA = 1, CPOL = 1). FCOMn [3:0] specify control actions after transmitting/
receiving the data byte.

Table 15. COMM Register Memory Map

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMM0 RD/WR ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4]
COMM1 RD/WR D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0]
COMM2 RD/WR ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4]
COMM3 RD/WR D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0]
COMM4 RD/WR ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4]
COMM5 RD/WR D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0]

680412fc

For more information www.linear.com/LTC6804-1 31

LTC6804-1/LTC6804-2
Operation
Table 16. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master
CONTROL BITS CODE ACTION DESCRIPTION
0110 START Generate a START Signal on I2C Port Followed By Data Transmission
0001 STOP Generate a STOP Signal on I2C port
ICOMn[3:0]
0000 BLANK Proceed Directly to Data Transmission on I2C Port
0111 No Transmit Release SDA and SCL and Ignore the Rest of the Data
0000 Master ACK Master Generates an ACK Signal on Ninth Clock Cycle
FCOMn[3:0] 1000 Master NACK Master Generates a NACK Signal on Ninth Clock Cycle
1001 Master NACK + STOP Master Generates a NACK Signal Followed by STOP Signal

Table 17. Write Codes for ICOMn[3:0] and FCOMn[3:0] on SPI Master
CONTROL BITS CODE ACTION DESCRIPTION
1000 CSBM low Generates a CSBM Low Signal on SPI Port (GPIO3)
ICOMn[3:0] 1001 CSBM high Generates a CSBM High Signal on SPI Port (GPIO3)
1111 No Transmit Releases the SPI Port and Ignores the Rest of the Data
X000 CSBM low Holds CSBM Low at the End of Byte Transmission
FCOMn[3:0]
1001 CSBM high Transitions CSBM High at the End of Byte Transmission

If the bit ICOMn[3] in the COMM register is set to 1 the at the end of the data. If the PEC does not match, all data
part becomes an I2C master and if the bit is set to 0 the in the COMM register is cleared to 1’s when CSB goes
part becomes a SPI master. high. See the section Bus Protocols for more details on a
write command format.
Table 16 describes the valid write codes for ICOMn[3:0]
and FCOMn[3:0] and their behavior when using the part STCOMM Command: This command initiates I2C/SPI com-
as an I2C master. munication on the GPIO ports. The COMM register contains
Table 17 describes the valid codes for ICOMn[3:0] and 3 bytes of data to be transmitted to the slave. During this
FCOMn[3:0] and their behavior when using the part as command, the data bytes stored in the COMM register are
a SPI master. transmitted to the slave I2C or SPI device and the data
received from the I2C or SPI device is stored in the COMM
Note that only the codes listed in Tables 16 and 17 are register. This command uses GPIO4 (SDA) and GPIO5
valid for ICOMn[3:0] and FCOMn[3:0]. Writing any other (SCL) for I2C communication or GPIO3 (CSBM), GPIO4
code that is not listed in Tables 16 and 17 to ICOMn[3:0] (SDIOM) and GPIO5 (SCKM) for SPI communication.
and FCOMn[3:0] may result in unexpected behavior on
the I2C and SPI ports. The STCOMM command is to be followed by 24 clock
cycles for each byte of data to be transmitted to the slave
COMM Commands device while holding CSB low. For example, to transmit 3
bytes of data to the slave, send STCOMM command and
Three commands help accomplish I2C or SPI communica-
its PEC followed by 72 clock cycles. Pull CSB high at the
tion to the slave device: WRCOMM, STCOMM, RDCOMM
end of the 72 clock cycles of STCOMM command.
WRCOMM Command: This command is used to write data
During I2C or SPI communication, the data received from
to the COMM register. This command writes 6 bytes of
the slave device is updated in the COMM register.
data to the COMM register. The PEC needs to be written

680412fc

32 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
RDCOMM Command: The data received from the slave Any number of bytes can be transmitted to the slave in
device can be read back from the COMM register using the groups of 3 bytes using these commands. The GPIO ports
RDCOMM command. The command reads back 6 bytes of will not get reset between different STCOMM commands.
data followed by the PEC. See the section Bus Protocols However, if the wait time between the commands is greater
for more details on a read command format. than 2 seconds, the watchdog will timeout and reset the
ports to their default values.
Table 18 describes the possible read back codes for
ICOMn[3:0] and FCOMn[3:0] when using the part as an I2C To transmit several bytes of data using an I2C master, a
master. Dn[7:0] contains the data byte either transmitted START signal is only required at the beginning of the entire
by the I2C master or received from the I2C slave. data stream. A STOP signal is only required at the end of
the data stream. All intermediate data groups can use a
In case of the SPI master, the read back codes for
BLANK code before the data byte and an ACK/NACK signal
ICOMn[3:0] and FCOMn[3:0] are always 0111 and 1111
as appropriate after the data byte. SDA and SCL will not
respectively. Dn[7:0] contains the data byte either trans-
get reset between different STCOMM commands.
mitted by the SPI master or received from the SPI slave.
To transmit several bytes of data using SPI master, a
Table 18. Read Codes for ICOMn[3:0] and FCOMn[3:0] on I2C
Master CSBM low signal is sent at the beginning of the 1st data
CONTROL CODE DESCRIPTION
byte. CSBM can be held low or taken high for intermediate
BITS data groups using the appropriate code on FCOMn[3:0].
0110 Master Generated a START Signal A CSBM high signal is sent at the end of the last byte of
0001 Master Generated a STOP Signal data. CSBM, SDIOM and SCKM will not get reset between
ICOMn[3:0]
0000 Blank, SDA Was Held Low Between Bytes different STCOMM commands.
0111 Blank, SDA Was Held High Between Bytes Figure 12 shows the 24 clock cycles following STCOMM
0000 Master Generated an ACK Signal command for an I2C master in different cases. Note that
0111 Slave Generated an ACK Signal if ICOMn[3:0] specified a STOP condition, after the STOP
1111 Slave Generated a NACK Signal signal is sent, the SDA and SCL lines are held high and
FCOMn[3:0] 0001 Slave Generated an ACK Signal, Master all data in the rest of the word is ignored. If ICOMn[3:0]
Generated a STOP Signal
is a NO TRANSMIT, both SDA and SCL lines are released,
1001 Slave Generated a NACK Signal, Master
Generated a STOP Signal
and rest of the data in the word is ignored. This is used
when a particular device in the stack does not have to
Figure 11 illustrates the operation of LTC6804 as an I2C communicate to a slave.
or SPI master using the GPIOs.
Figure 13 shows the 24 clock cycles following STCOMM
command for a SPI master. Similar to the I2C master, if
LTC6804-1/LTC6804-2 ICOMn[3:0] specified a CSBM HIGH or a NO TRANSMIT
STCOMM
condition, the CSBM, SCKM and SDIOM lines of the SPI
RDCOMM PORT A master are released and the rest of the data in the word
I2C/SPI
SLAVE
GPIO
PORT
COMM
REGISTER WRCOMM is ignored.

680412 F11

Figure 11. LTC6804 I2C/SPI Master Using GPIOs

680412fc

For more information www.linear.com/LTC6804-1 33

LTC6804-1/LTC6804-2
Operation
tCLK t4 t3
(SCK)

START NACK + STOP

SCL (GPIO5)

SDA (GPIO4)

BLANK NACK
SCL (GPIO5)

SDA (GPIO4)

START ACK
SCL (GPIO5)

SDA (GPIO4)

STOP
SCL (GPIO5)

SDA (GPIO4)

NO TRANSMIT
SCL (GPIO5)

SDA (GPIO4) 680412 F12

Figure 12. STCOMM Timing Diagram for an I2C Master

tCLK t4 t3

(SCK)

CSBM HIGH ≥ LOW CSBM LOW

CSBM (GPIO3)

SCKM (GPIO5)

SDIOM (GPIO4)

CSBM LOW CSBM LOW ≥ HIGH

CSBM (GPIO3)

SCKM (GPIO5)

SDIOM (GPIO4)

CSBM HIGH/NO TRANSMIT

CSBM (GPIO3)

SCKM (GPIO5)

SDIOM (GPIO4) 680412 F13

Figure 13. STCOMM Timing Diagram for a SPI Master

680412fc

34 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Timing Specifications of I2C and SPI master There are two versions of the LTC6804: the LTC6804-1
The timing of the LTC6804 I2C or SPI master will be and the LTC6804-2. The LTC6804-1 is used in a daisy
controlled by the timing of the communication at the chain configuration, and the LTC6804-2 is used in an
LTC6804’s primary SPI interface. Table 19 shows the addressable bus configuration. The LTC6804-1 provides
I2C master timing relationship to the primary SPI clock. a second isoSPI interface using pins 45 through 48. The
Table 20 shows the SPI master timing specifications. LTC6804-2 uses pins 45 through 48 to set the address of
the device, by tying these pins to V– or VREG.
Table 19. I2C Master Timing
TIMING RELATIONSHIP TIMING Table 20. SPI Master Timing
I2C MASTER TO PRIMARY SPI SPECIFICATIONS AT TIMING RELATIONSHIP TIMING
PARAMETER INTERFACE tCLK = 1µs TO PRIMARY SPI SPECIFICATIONS
SCL Clock Frequency 1/(2 • tCLK) Max 500kHz SPI MASTER PARAMETER INTERFACE AT tCLK = 1µs
tHD; STA t3 Min 200ns SDIOM Valid to SCKM t3 Min 200ns
tLOW tCLK Min 1µs Rising Setup
tHIGH tCLK Min 1µs SDIOM Valid from SCKM tCLK + t4* Min 1.03µs
Rising Hold
tSU; STA tCLK + t4* Min 1.03µs
SCKM Low tCLK Min 1µs
tHD; DAT t 4* Min 30ns
SCKM High tCLK Min 1µs
tSU; DAT t3 Min 1µs
SCKM Period (SCKM_Low 2 • tCLK Min 2µs
tSU; STO tCLK + t4* Min 1.03µs + SCKM_High)
tBUF 3 • tCLK Min 3µs CSBM Pulse Width 3 • tCLK Min 3µs
*Note: When using isoSPI, t4 is generated internally and is a minimum of SCKM Rising to CSBM 5 • tCLK + t4* Min 5.03µs
30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high Rising
times of the SCK input, each with a specified minimum of 200ns.
CSBM Falling to SCKM t3 Min 200ns
Falling
Serial Interface Overview CSBM Falling to SCKM tCLK + t3 Min 1.2µs
Rising
There are two types of serial ports on the LTC6804, a
SCKM Falling to SDIOM Master requires < tCLK
standard 4-wire serial peripheral interface (SPI) and a Valid
2-wire isolated interface (isoSPI). Pins 41 through 44 are *Note: When using isoSPI, t4 is generated internally and is a minimum of
configurable as 2-wire or 4-wire serial port, based on the 30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high
times of the SCK input, each with a specified minimum of 200ns.
state of the ISOMD pin.

680412fc

For more information www.linear.com/LTC6804-1 35

LTC6804-1/LTC6804-2
Operation
4-Wire Serial Peripheral Interface (SPI) 2-Wire Isolated Interface (isoSPI) Physical
Physical Layer Layer

External Connections The 2-wire interface provides a means to interconnect

LTC6804 devices using simple twisted pair cabling. The
Connecting ISOMD to V– configures serial Port A for interface is designed for low packet error rates when the
4-wire SPI. The SDO pin is an open drain output which cabling is subjected to high RF fields. Isolation is achieved
requires a pull-up resistor tied to the appropriate supply through an external transformer.
voltage (Figure 14).
Standard SPI signals are encoded into differential pulses.
Timing The strength of the transmission pulse and the threshold
level of the receiver are set by two external resistors, RB1
The 4-wire serial port is configured to operate in a SPI and RB2. The values of the resistors allow the user to trade
system using CPHA = 1 and CPOL = 1. Consequently, data off power dissipation for noise immunity.
on SDI must be stable during the rising edge of SCK. The
timing is depicted in Figure 15. The maximum data rate
is 1Mbps.

V+ IPB V+ A3
LTC6804-1 DAISY-CHAIN SUPPORT LTC6804-2 ADDRESS PINS
C12 IMB C12 A2
S12 ICMP 5k S12 A1 5k

C11 IBIAS C11 A0

S11 SDO (NC) MISO VDD S11 SDO (IBIAS) MISO VDD

C10 SDI (NC) MOSI C10 SDI (ICMP) MOSI

S10 SCK (IPA) CLK S10 SCK (IPA) CLK
C9 CSB (IMA) CS MPU C9 CSB (IMA) CS MPU
S9 ISOMD S9 ISOMD
C8 WDT C8 WDT
S8 DRIVE S8 DRIVE
C7 VREG C7 VREG
S7 SWTEN S7 SWTEN
C6 VREF1 C6 VREF1
S6 VREF2 S6 VREF2
C5 GPIO5 C5 GPIO5
S5 GPIO4 S5 GPIO4
C4 V– C4 V–
S4 V– S4 V–
C3 GPIO3 C3 GPIO3
S3 GPIO2 S3 GPIO2
C2 GPIO1 C2 GPIO1
S2 C0 S2 C0
C1 S1 C1 S1
680412 F14

Figure 14. 4-Wire SPI Configuration

680412fc

36 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
t1 t4 t3 t6 t7
t2

SCK

SDI D3 D2 D1 D0 D7…D4 D3

t5

CSB

t8

SDO D4 D3 D2 D1 D0 D7…D4 D3

680412 F15
PREVIOUS COMMAND CURRENT COMMAND

Figure 15. Timing Diagram of 4-Wire Serial Peripheral Interface

LTC6804 VREG

35k + VICMP/3 + 167mV

WAKEUP
IDLE
–
CIRCUIT 35k
(ON PORT A)
IDLE
Tx • 20 • IB
Tx = +1
IPA OR IPB
SDO Tx = 0
LOGIC
AND Tx = –1 •
MEMORY SDI RM
PULSE IMA OR IMB
ENCODER/ •
SCK
DECODER Rx = +1
+
CSB Rx = 0
Rx = –1 IB IBIAS
–
+ 2V
– RB1
1 ICMP
COMPARATOR THRESHOLD = • VICMP
2
0.5x
RB2

680412 F16

Figure 16. isoSPI Interface

Figure 16 illustrates how the isoSPI circuit operates. A External Connections

2V reference drives the IBIAS pin. External resistors RB1
The LTC6804-1 has 2 serial ports which are called Port B
and RB2 create the reference current IB. This current sets
and Port A. Port B is always configured as a 2-wire interface
the drive strength of the transmitter. RB1 and RB2 also
(master). The final device in the daisy chain does not use
form a voltage divider of the 2V reference at the ICMP
this port, and it should be terminated into RM. Port A is
pin. This sets the threshold voltage of the receiver circuit. either a 2-wire or 4-wire interface (slave), depending on
Transmitted current pulses are converted into voltage by the connection of the ISOMD pin.
termination resistor RM (in parallel with the characteristic
impedance of the cable).

680412fc

For more information www.linear.com/LTC6804-1 37

LTC6804-1/LTC6804-2
Operation
Figure 17a is an example of a robust interconnection of As an example, if divider resistor RB1 is 2.8k and resistor
multiple identical PCBs, each containing one LTC6804‑1. RB2 is 1.21k (so that RBIAS = 4k), then:
Note the termination in the final device in the daisy chain.
2V
The microprocessor is located on a separate PCB. To IB = = 0.5mA
achieve 2-wire isolation between the microprocessor PCB RB1 +RB2
and the 1st LTC6804-1 PCB, use the LTC6820 support IC. IDRV =IIP =IIM = 20 •IB = 10mA
The LTC6820 is functionally equivalent to the diagram in RB2
Figure 16. VICMP = 2V • =I •R = 603mV
RB1 +RB2 B B2
The LTC6804-2 has a single serial port (Port A) which can VTCMP = 0.5 • VICMP = 302mV
be 2-wire or 4-wire, depending on the state of the ISOMD
pin. When configured for 2-wire communications, several In this example, the pulse drive current IDRV will be 10mA,
devices can be connected in a multi-drop configuration, as and the receiver comparators will detect pulses with IP-IM
shown in Figure 17b. The LTC6820 IC is used to interface amplitudes greater than ±302mV.
the MPU (master) to the LTC6804-2’s (slaves).
If the isolation barrier uses 1:1 transformers connected
Using a Single LTC6804 by a twisted pair and terminated with 120Ω resistors on
each end, then the transmitted differential signal amplitude
When only one LTC6804 is needed, the LTC6804-2 is rec- (±) will be:
ommended. It does not have isoSPI Port B, so it requires
fewer external components and consumes less power, RM
VA =IDRV • = 0.6V
especially when Port A is configured as a 4-wire interface. 2
However, the LTC6804-1 can be used as a single (non (This result ignores transformer and cable losses, which
daisy-chained) device if the second isoSPI port (Port B) is may reduce the amplitude).
properly biased and terminated, as shown in Figure 18c.
ICMP should not be tied to GND, but can be tied directly isoSPI Pulse Detail
to IBIAS. A bias resistance (2k to 20k) is required for Two LTC6804 devices can communicate by transmitting
IBIAS. Do not tie IBIAS directly to VREG or V–. Finally, IPB and receiving differential pulses back and forth through an
and IMB should be terminated into a 100Ω resistor (not isolation barrier. The transmitter can output three voltage
tied to VREG or V–). levels: +VA, 0V, and –VA. A positive output results from
IP sourcing current and IM sinking current across load
Selecting Bias Resistors
resistor RM. A negative voltage is developed by IP sink-
The adjustable signal amplitude allows the system to trade ing and IM sourcing. When both outputs are off, the load
power consumption for communication robustness, and resistance forces the differential output to 0V.
the adjustable comparator threshold allows the system to
To eliminate the DC signal component and enhance reli-
account for signal losses.
ability, the isoSPI uses two different pulse lengths. This
The isoSPI transmitter drive current and comparator volt- allows for four types of pulses to be transmitted, as shown
age threshold are set by a resistor divider (RBIAS = RB1 in Table 21. A +1 pulse will be transmitted as a positive
+ RB2) between the IBIAS and V–. The divided voltage is pulse followed by a negative pulse. A –1 pulse will be
connected to the ICMP pin which sets the comparator transmitted as a negative pulse followed by a positive
threshold to 1/2 of this voltage (VICMP). When either pulse. The duration of each pulse is defined as t1/2PW,
isoSPI interface is enabled (not IDLE) IBIAS is held at 2V, since each is half of the required symmetric pair. (The
causing a current IB to flow out of the IBIAS pin. The IP total isoSPI pulse duration is 2 • t1/2PW).
and IM pin drive currents are 20 • IB.
680412fc

38 For more information www.linear.com/LTC6804-1

 •
•
•
•
•
•
•

•
•
•
•
•
•
•
V+ IPB V+ IPB V+ IPB V+ IPB
LTC6804-1 LTC6804-1 LTC6804-1 LTC6804-1
C12 IMB C12 IMB C12 IMB C12 IMB
S12 ICMP S12 ICMP S12 ICMP S12 ICMP
C11 IBIAS C11 IBIAS C11 IBIAS C11 IBIAS
S11 SDO (NC) S11 SDO (NC) S11 SDO (NC) S11 SDO (NC)
C10 SDI (NC) C10 SDI (NC) C10 SDI (NC) C10 SDI (NC)
S10 SCK (IPA) S10 SCK (IPA) S10 SCK (IPA) S10 SCK (IPA)
Operation

C9 CSB (IMA) C9 CSB (IMA) C9 CSB (IMA) C9 CSB (IMA) MISO VDD
S9 ISOMD S9 ISOMD S9 ISOMD S9 ISOMD MOSI
C8 WDT C8 WDT C8 WDT C8 WDT CLK
S8 DRIVE S8 DRIVE S8 DRIVE S8 DRIVE CS MPU
C7 VREG C7 VREG C7 VREG C7 VREG
S7 SWTEN S7 SWTEN S7 SWTEN S7 SWTEN
C6 VREF1 C6 VREF1 C6 VREF1 C6 VREF1 VDDS VDD

S6 VREF2 S6 VREF2 S6 VREF2 S6 VREF2 EN POL

LTC6820
C5 GPIO5 C5 GPIO5 C5 GPIO5 C5 GPIO5 PHA

S5 GPIO4 S5 GPIO4 S5 GPIO4 S5 GPIO4 MISO MSTR

C4 V– C4 V– C4 V– C4 V– MOSI ICMP

S4 V– S4 V– S4 V– S4 V– SCK IBIAS

C3 GPIO3 C3 GPIO3 C3 GPIO3 C3 GPIO3 CS GND

S3 GPIO2 S3 GPIO2 S3 GPIO2 S3 GPIO2 SLOW

C2 GPIO1 C2 GPIO1 C2 GPIO1 C2 GPIO1 IP •

S2 C0 S2 C0 S2 C0 S2 C0 IM •
C1 S1 C1 S1 C1 S1 C1 S1

680412 F17

Figure 17a. Transformer-Isolated Daisy-Chain Configuration Using LTC6804-1

•
•
•
•

•
•
•
•

ADDRESS = 0x3 ADDRESS = 0x2 ADDRESS = 0x1 ADDRESS = 0x0

V+ A3 V+ A3 V+ A3 V+ A3
LTC6804-2 LTC6804-2 LTC6804-2 LTC6804-2
C12 A2 C12 A2 C12 A2 C12 A2
S12 A1 S12 A1 S12 A1 S12 A1

For more information www.linear.com/LTC6804-1

C11 A0 C11 A0 C11 A0 C11 A0
S11 SDO (IBIAS) S11 SDO (IBIAS) S11 SDO (IBIAS) S11 SDO (IBIAS)
C10 SDI (ICMP) C10 SDI (ICMP) C10 SDI (ICMP) C10 SDI (ICMP)
S10 SCK (IPA) S10 SCK (IPA) S10 SCK (IPA) S10 SCK (IPA)
C9 CSB (IMA) C9 CSB (IMA) C9 CSB (IMA) C9 CSB (IMA) MISO VDD
S9 ISOMD S9 ISOMD S9 ISOMD S9 ISOMD MOSI
C8 WDT C8 WDT C8 WDT C8 WDT CLK
S8 DRIVE S8 DRIVE S8 DRIVE S8 DRIVE CS MPU
C7 VREG C7 VREG C7 VREG C7 VREG
S7 SWTEN S7 SWTEN S7 SWTEN S7 SWTEN
C6 VREF1 C6 VREF1 C6 VREF1 C6 VREF1 VDDS VDD

S6 VREF2 S6 VREF2 S6 VREF2 S6 VREF2 EN POL

LTC6820
C5 GPIO5 C5 GPIO5 C5 GPIO5 C5 GPIO5 PHA

S5 GPIO4 S5 GPIO4 S5 GPIO4 S5 GPIO4 MISO MSTR

C4 V– C4 V– C4 V– C4 V– MOSI ICMP
– – – – SCK IBIAS
S4 V S4 V S4 V S4 V
C3 GPIO3 C3 GPIO3 C3 GPIO3 C3 GPIO3 CS GND

S3 GPIO2 S3 GPIO2 S3 GPIO2 S3 GPIO2 SLOW

C2 GPIO1 C2 GPIO1 C2 GPIO1 C2 GPIO1 IP •

S2 C0 S2 C0 S2 C0 S2 C0 IM •
C1 S1 C1 S1 C1 S1 C1 S1

680412 F18

Figure 17b. Multi-Drop Configuration Using LTC6804-2

39
680412fc
LTC6804-1/LTC6804-2
LTC6804-1/LTC6804-2
Operation

TERMINATED UNUSED PORT

•

•
LTC6804-1 RM LTC6804-2 ADDRESS = 0×0
V+ IPB VDD V+ A3 VDD
•

•
C12 IMB MISO C12 A2 MISO
S12 ICMP MOSI S12 A1 MOSI
C11 IBIAS CLK C11 A0 CLK
S11 SDO(NC) CS MPU S11 SDO(IBIAS) CS MPU
C10 SDI(NC) C10 SDI(ICMP)
S10 SCK(IPA) S10 SCK(IPA)
C9 CSB(IMA) LTC6820 C9 CSB(IMA) LTC6820
S9 ISOMD S9 ISOMD
C8 VDDS VDD C8 VDDS VDD
WDT WDT
S8 EN POL S8 EN POL
DRIVE DRIVE
C7 PHA C7 PHA
VREG VREG
S7 MSTR S7 MSTR
SWTEN SWTEN
C6 ICMP C6 ICMP
VREF1 VREF1
S6 MISO IBIAS S6 MISO IBIAS
VREF2 VREF2
C5 GPIO5 MOSI GND C5 GPIO5 MOSI GND
S5 GPIO4 SCK SLOW S5 GPIO4 SCK SLOW
C4 V– CS C4 V– CS
IP • IP •
S4 V– S4 V–
IM IM
C3 GPIO3 • C3 GPIO3 •
S3 GPIO2 S3 GPIO2
C2 GPIO1 C2 GPIO1
S2 C0 S2 C0
C1 S1 C1 S1

680412 F18a 680412 F18b

Figure 18a. Single-Device LTC6804-1 Using 2-Wire Port A Figure 18b. Single-Device LTC6804-2 Using 2-Wire Port A

TERMINATED UNUSED PORT

LTC6804-1 100Ω REQUIRED BIAS LTC6804-2 ADDRESS = 0×0

V+ IPB 5k V+ A3 5k
C12 IMB C12 A2
S12 ICMP 20k S12 A1
C11 IBIAS VDD C11 A0 VDD
S11 SDO(NC) MISO S11 SDO(IBIAS) MISO
C10 SDI(NC) MOSI C10 SDI(ICMP) MOSI
S10 SCK(IPA) CLK S10 SCK(IPA) CLK
C9 CSB(IMA) CS MPU C9 CSB(IMA) CS MPU
S9 ISOMD S9 ISOMD
C8 WDT C8 WDT
S8 DRIVE S8 DRIVE
C7 VREG C7 VREG
S7 SWTEN S7 SWTEN
C6 VREF1 C6 VREF1
S6 VREF2 S6 VREF2
C5 GPIO5 C5 GPIO5
S5 GPIO4 S5 GPIO4
C4 V– C4 V–
S4 V– S4 V–
C3 GPIO3 C3 GPIO3
S3 GPIO2 S3 GPIO2
C2 GPIO1 C2 GPIO1
S2 C0 S2 C0
C1 S1 C1 S1

680412 F18c 680412 F18d

Figure 18c. Single-Device LTC6804-1 Using 4-Wire Port A Figure 18d. Single-Device LTC6804-2 Using 4-Wire Port A

680412fc

40 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Table 21. isoSPI Pulse Types Table 22. LTC6804-1 Port B (Master) isoSPI Port Function
FIRST LEVEL SECOND LEVEL COMMUNICATION EVENT TRANSMITTED PULSE
PULSE TYPE (t1/2PW) (t1/2PW) ENDING LEVEL (PORT A SPI) (PORT B isoSPI)
Long +1 +VA (150ns) –VA (150ns) 0V CSB Rising Long +1
Long –1 –VA (150ns) +VA (150ns) 0V CSB Falling Long –1
Short +1 +VA (50ns) –VA (50ns) 0V SCK Rising Edge, SDI = 1 Short +1
Short –1 –VA (50ns) +VA (50ns) 0V SCK Rising Edge, SDI = 0 Short –1

A host microcontroller does not have to generate isoSPI On the other side of the isolation barrier (i.e. at the other
pulses to use this 2-wire interface. The first LTC6804 in end of the cable), the 2nd LTC6804 will have ISOMD =
the system can communicate to the microcontroller using VREG. Its Port A operates as a slave isoSPI interface. It
the 4-wire SPI interface on its Port A, then daisy-chain to receives each transmitted pulse and reconstructs the
other LTC6804s using the 2-wire isoSPI interface on its SPI signals internally, as shown in Table 23. In addition,
Port B. Alternatively, an LTC6820 can be used to translate during a READ command this port may transmit return
the SPI signals into isoSPI pulses. data pulses.

LTC6804-1 Operation with Port A Configured for SPI Table 23. LTC6804-1 Port A (Slave) isoSPI Port Function
RECEIVED PULSE INTERNAL SPI
When the LTC6804-1 is operating with port A as an SPI (PORT A isoSPI) PORT ACTION RETURN PULSE
(ISOMD = V–), the SPI detects one of four communication Long +1 Drive CSB High None
events: CSB falling, CSB rising, SCK rising with SDI = 0, Long –1 Drive CSB Low
and SCK rising with SDI = 1. Each event is converted into Short +1 1. Set SDI = 1 Short –1 Pulse if Reading a 0 bit
one of the four pulse types for transmission through the 2. Pulse SCK
LTC6804-1 daisy chain. Long pulses are used to transmit Short –1 1. Set SDI = 0 (No Return Pulse if Not in READ
2. Pulse SCK Mode or if Reading a 1 bit)
CSB changes and short pulses are used to transmit data,
as explained in Table 22.
+1 PULSE
+VA

+VTCMP t1/2PW

VIP – VIM

–VTCMP t1/2PW
tINV
–VA

–1 PULSE
+VA
tINV
+VTCMP t1/2PW

VIP – VIM

–VTCMP t1/2PW

–VA 680412 F19

Figure 19. isoSPI Pulse Detail

680412fc

For more information www.linear.com/LTC6804-1 41

LTC6804-1/LTC6804-2
Operation
The lower isoSPI port (Port A) never transmits long Bits Wn-W0 refers to the 16-bit command code and the
(CSB) pulses. Furthermore, a slave isoSPI port will only 16-bit PEC of a READ command. At the end of bit W0 the
transmit short –1 pulses, never a +1 pulse. The master 3 parts decode the READ command and begin shifting out
port recognizes a null response as a logic 1. This allows data which is valid on the next rising edge of clock SCK.
for multiple slave devices on a single cable without risk Bits Xn-X0 refer to the data shifted out by Part 1. Bits Yn-Y0
of collisions (Multidrop). refer to the data shifted out by Part 2 and bits Zn-Z0 refer
to the data shifted out by Part 3. All this data is read back
Figure 20 shows the isoSPI timing diagram for a READ
from the SDO port on Part 1 in a daisy-chained fashion.
command to daisy-chained LTC6804-1 parts. The ISOMD
pin is tied to V– on the bottom part so its Port A is config- Waking Up the Serial Interface
ured as a SPI port (CSB, SCK, SDI and SDO). The isoSPI
signals of three stacked devices are shown, labeled with The serial ports (SPI or isoSPI) will enter the low power
the port (A or B) and part number. Note that ISO B1 and IDLE state if there is no activity on Port A for a time of tIDLE.
ISO A2 is actually the same signal, but shown on each The WAKEUP circuit monitors activity on pins 41 and 42.
end of the transmission cable that connects parts 1 and 2. If ISOMD = V–, Port A is in SPI mode. Activity on the CSB
Likewise, ISO B2 and ISO A3 is the same signal, but with or SCK pin will wake up the SPI interface. If ISOMD = VREG,
the cable delay shown between parts 2 and 3.

COMMAND READ DATA

CSB t7 t6 t5

t1
SDI t2

tCLK

SCK t4 t3

t8
t11
tRISE

SDO Xn Xn-1 Z0

t10 t9 t10
Wn W0 Yn Yn-1
ISO B1

Wn W0 Yn Yn-1
ISO A2
tRTN
tDSY(CS) tDSY(CS)
tDSY(D)
Wn W0 Zn Zn-1
ISO B2

Wn W0 Zn Zn-1
ISO A3

680412 F20
0 1000 2000 3000 4000 5000 6000

Figure 20. isoSPI Timing Diagram

680412fc

42 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Port A is in isoSPI mode. Differential activity on IPA-IMB Method 1 can be used when all devices on the daisy chain
wakes up the isoSPI interface. The LTC6804 will be ready are in the IDLE state. This guarantees that they propagate
to communicate when the isoSPI state changes to READY the wake-up signal up the daisy chain. However, this
within tWAKE or tREADY, depending on the Core state (see method will fail to wake up all devices when a device in
Figure 1 and state descriptions for details.) the middle of the chain is in the READY state instead of
Figure 21 illustrates the timing and the functionally IDLE. When this happens, the device in READY state will
equivalent circuit. Common mode signals will not wake not propagate the wake-up pulse, so the devices above it
up the serial interface. The interface is designed to wake will remain IDLE. This situation can occur when attempt-
ing to wake up the daisy chain after only tIDLE of idle time
up after receiving a large signal single-ended pulse, or a
(some devices may be IDLE, some may not).
low-amplitude symmetric pulse. The differential signal
|SCK(IPA) – CSB(IMA)|, must be at least VWAKE = 200mV Waking a Daisy Chain ­— Method 2
for a minimum duration of tDWELL = 240ns to qualify as a
wake up signal that powers up the serial interface. A more robust wake-up method does not rely on the built-in
wake-up pulse, but manually sends isoSPI traffic for enough
Waking a Daisy Chain — Method 1 time to wake the entire daisy chain. At minimum, a pair of
The LTC6804-1 sends a Long +1 pulse on Port B after it is long isoSPI pulses (–1 and +1) is needed for each device,
ready to communicate. In a daisy-chained configuration, separated by more than tREADY or tWAKE (if the core state is
STANDBY or SLEEP, respectively), but less than tIDLE. This
this pulse wakes up the next device in the stack which will,
allows each device to wake up and propagate the next pulse
in turn, wake up the next device. If there are ‘N’ devices in
to the following device. This method works even if some
the stack, all the devices are powered up within the time
devices in the chain are not in the IDLE state. In practice,
N • tWAKE or N • tREADY, depending on the Core State. For
large stacks, the time N • tWAKE may be equal to or larger implementing method 2 requires toggling the CSB pin
than tIDLE. In this case, after waiting longer than the time (of the LTC6820, or bottom LTC6804-1 with ISOMD = 0)
of N • tWAKE, the host may send another dummy byte and to generate the long isoSPI pulses. Alternatively, dummy
wait for the time N • tREADY, in order to ensure that all commands (such as RDCFG) can be executed to generate
devices are in the READY state. the long isoSPI pulses.

REJECTS COMMON
MODE NOISE

CSB OR IMA

SCK OR IPA
VWAKE = 200mV

|SCK(IPA) - CSB(IMA)|
tDWELL= 240ns

WAKE-UP

STATE LOW POWER MODE OK TO COMMUNICATE LOW POWER MODE

tREADY < 10µs tIDLE > 4.5ms

RETRIGGERABLE
CSB OR IMA tDWELL = 240ns tIDLE = 5.5ms WAKE-UP
SCK OR IPA DELAY ONE-SHOT 680412 F21

Figure 21. Wake-Up Detection and IDLE Timer

680412fc

For more information www.linear.com/LTC6804-1 43

LTC6804-1/LTC6804-2
Operation
Data Link Layer 3. Update the 15-bit PEC as follows
All Data transfers on LTC6804 occur in byte groups. PEC [14] = IN14,
Every byte consists of 8 bits. Bytes are transferred with PEC [13] = PEC [12],
the most significant bit (MSB) first. CSB must remain low
for the entire duration of a command sequence, including PEC [12] = PEC [11],
between a command byte and subsequent data. On a write PEC [11] = PEC [10],
command, data is latched in on the rising edge of CSB.
PEC [10] = IN10,
Network Layer PEC [9] = PEC [8],
PEC [8] = IN8,
Packet Error Code
PEC [7] = IN7,
The packet error code (PEC) is a 15-bit cyclic redundancy
check (CRC) value calculated for all of the bits in a reg- PEC [6] = PEC [5],
ister group in the order they are passed, using the initial PEC [5] = PEC [4],
PEC seed value of 000000000010000 and the following
characteristic polynomial: x15 + x14 + x10 + x8 + x7 + PEC [4] = IN4,
x4 + x3 + 1. To calculate the 15-bit PEC value, a simple PEC [3] = IN3,
procedure can be established:
PEC [2] = PEC [1],
1. Initialize the PEC to 000000000010000 (PEC is a 15-bit
PEC [1] = PEC [0],
register group)
2. For each bit DIN coming into the PEC register group, PEC [0] = IN0
set 4. Go back to step 2 until all the data is shifted. The final
IN0 = DIN XOR PEC [14] PEC (16 bits) is the 15-bit value in the PEC register with
a 0 bit appended to its LSB
IN3 = IN0 XOR PEC [2]
Figure 22 illustrates the algorithm described above. An
IN4 = IN0 XOR PEC [3] example to calculate the PEC for a 16-bit word (0x0001)
IN7 = IN0 XOR PEC [6] is listed in Table 24. The PEC for 0x0001 is computed as
0x3D6E after stuffing a 0 bit at the LSB. For longer data
IN8 = IN0 XOR PEC [7] streams, the PEC is valid at the end of the last bit of data
IN10 = IN0 XOR PEC [9] sent to the PEC register.
IN14 = IN0 XOR PEC [13]
O/P I/P XOR GATE

I/P

X PEC REGISTER BIT X

DIN

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

680412 F22

Figure 22. 15-Bit PEC Computation Circuit

680412fc

44 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
LTC6804 calculates PEC for any command or data received register group to two daisy-chained devices (primary device
and compares it with the PEC following the command or P, stacked device S), the data will be sent to the primary
data. The command or data is regarded as valid only if device on Port A in the following order:
the PEC matches. LTC6804 also attaches the calculated CFGR0(S), … , CFGR5(S), PEC0(S), PEC1(S), CFGR0(P),
PEC at the end of the data it shifts out. Table 25 shows the …, CFGR5(P), PEC0(P), PEC1(P)
format of PEC while writing to or reading from LTC6804.
After a read command for daisy-chained devices, each
While writing any command to LTC6804, the command device shifts out its data and the PEC that it computed for
bytes CMD0 and CMD1 (See Table 32 and Table 33) and its data on Port A followed by the data received on Port B.
the PEC bytes PEC0 and PEC1 are sent on Port A in the For example, when reading status register group B from
following order: two daisy-chained devices (primary device P, stacked
CMD0, CMD1, PEC0, PEC1 device S), the primary device sends out data on port A in
the following order:
After a broadcast write command to daisy-chained
LTC6804-1 devices, data is sent to each device followed STBR0(P), …, STBR5(P), PEC0(P), PEC1(P), STBR0(S),
by the PEC. For example, when writing the configuration … , STBR5(S), PEC0(S), PEC1(S)

Table 24. PEC Calculation for 0x0001

PEC[14] 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
PEC[13] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0
PEC[12] 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1
PEC[11] 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1
PEC[10] 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 1
PEC[9] 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1
PEC[8] 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0
PEC[7] 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1
PEC[6] 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
PEC[5] 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1
PEC[4] 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1
PEC[3] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0
PEC[2] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
PEC[1] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
PEC[0] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
IN14 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
IN10 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 PEC Word
IN8 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0
IN7 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1
IN4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1
IN3 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
IN0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
DIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Clock Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

680412fc

For more information www.linear.com/LTC6804-1 45

LTC6804-1/LTC6804-2
Operation
Table 25. Write/Read PEC Format
NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PEC0 RD/WR PEC[14] PEC[13] PEC[12] PEC[11] PEC[10] PEC[9] PEC[8] PEC[7]
PEC1 RD/WR PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0] 0

Broadcast vs Address Commands Daisy-chained (LTC6804-1) configurations support broad-

CONFIGURATION TYPE OF COMMAND cast commands only, because they have no addressing.
DEVICE INTERFACE READ WRITE POLL All devices in the chain receive the command bytes simul-
LTC6804-2 SPI Address- Address Address
taneously. For example, to initiate ADC conversions in a
(Address/Parallel) Only or or stack of devices, a single ADCV command is sent, and all
Broadcast Broadcast devices will start conversions at the same time. For read
isoSPI Address- and write commands, a single command is sent, and then
Only†
the stacked devices effectively turn into a cascaded shift
LTC6804-1 SPI or Broadcast-Only N/A
isoSPI register, in which data is shifted through each device to
(Daisy-Chain)
†The LTC6804-2 will not return data pulses when using broadcast
the next device in the stack. See the Serial Programming
commands in isoSPI mode. Therefore, ADC commands will execute, but
Examples section.
polling will not work.
Polling Methods
Address Commands (LTC6804-2 Only)
The simplest method to determine ADC completion is
An address command is one in which only the addressed for the controller to start an ADC conversion and wait for
device on the bus responds. Address commands are used the specified conversion time to pass before reading the
only with LTC6804-2 parts. All commands are compatible results. Polling is not supported with daisy-chain com-
with addressing. See Bus Protocols for Address command munication (LTC6804-1).
format.
In parallel configurations that communicate in SPI mode
Broadcast Commands (LTC6804-1 or LTC6804-2) (ISOMD pin tied low), there are two methods of poll-
ing. The first method is to hold CSB low after an ADC
A broadcast command is one to which all devices on the conversion command is sent. After entering a conversion
bus will respond, regardless of device address. This com- command, the SDO line is driven low when the device is
mand format can be used with LTC6804-1 and LTC6804-2 busy performing conversions (Figure 23). SDO is pulled
parts. See Bus Protocols for Broadcast command format. high when the device completes conversions. However, the
With broadcast commands all devices can be sent com- SDO will also go back high when CSB goes high even if the
mands simultaneously. device has not completed the conversion. An addressed
In parallel (LTC6804-2) configurations, broadcast com- device drives the SDO line based on its status alone. A
mands are useful for initiating ADC conversions or for problem with this method is that the controller is not free
sending write commands when all parts are being written to do other serial communication while waiting for ADC
with the same data. The polling function (automatic at the conversions to complete.
end of ADC commands, or manual using the PLADC com- The next method overcomes this limitation. The controller
mand) can also be used with broadcast commands, but can send an ADC start command, perform other tasks, and
only with parallel SPI interfaces. Polling is not compatible then send a poll ADC converter status (PLADC) command
with parallel isoSPI. Likewise, broadcast read commands to determine the status of the ADC conversions (Figure 24).
should not be used in a parallel configuration (either SPI After entering the PLADC command, SDO will go low if
or isoSPI). the device is busy performing conversions. SDO is pulled
high at the end of conversions. However, the SDO will also
680412fc

46 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
go high when CSB goes high even if the device has not Bus Protocols
completed the conversion. See Programming Examples on
Protocol Format: The protocol formats for both broadcast
how to use the PLADC command with devices in parallel
and address commands are depicted in Table 27 through
configuration.
Table 31. Table 26 is the key for reading the protocol
In parallel configurations that communicate in isoSPI diagrams.
mode, the low side port transmits a data pulse only in
Table 26. Protocol Key
response to a master isoSPI pulse received by it. So,
CMD0 First Command Byte (See Tables 32 and 33)
after entering an address command in either method of
CMD1 Second Command Byte (See Tables 32 and 33)
polling described above, isoSPI data pulses are sent to
PEC0 First PEC Byte (See Table 25)
the part to update the conversion status. These pulses
PEC1 Second PEC Byte (See Table 25)
can be sent using LTC6820 by simply clocking its SCK
n Number of Bytes
pin. In response to this pulse, the LTC6804-2 returns an
isoSPI pulse if it is still busy performing conversions and … Continuation of Protocol

does not return a pulse if it has completed conversions. If Master to Slave

a CSB high isoSPI pulse is sent to the LTC6804-2, it exits Slave to Master
the polling command. Note that broadcast poll commands
are not compatible with parallel isoSPI.

tCYCLE
CSB

SCK

SDI MSB(CMD) BIT 14(CMD) LSB(PEC)

SDO
680412 F23

Figure 23. SDO Polling After an ADC Conversion Command

CSB

SCK

SDI MSB(CMD) BIT 14(CMD) LSB(PEC)

SDO

CONVERSION DONE 680412 F24

Figure 24. SDO Polling Using PLADC Command

680412fc

For more information www.linear.com/LTC6804-1 47

LTC6804-1/LTC6804-2
Operation
Command Format: The formats for the broadcast and command only if the physical address of the device on
address commands are shown in Table 32 and Table 33 pins A3 to A0 match the address specified in the address
respectively. The 11-bit command code CC[10:0] is the command. The PEC for broadcast and address commands
same for a broadcast or an address command. A list of must be computed on the entire 16-bit command (CMD0
all the command codes is shown in Table 34. A broadcast and CMD1).
command has a value 0 for CMD0[7] through CMD0[3].
An address command has a value 1 for CMD0[7] followed Commands
by the 4-bit address of the device (a3, a2, a1, a0) in bits Table 34 lists all the commands and its options for both
CMD0[6:3]. An addressed device will respond to an address LTC6804-1 and LTC6804-2

Table 27. Broadcast/Address Poll Command

8 8 8 8
CMD0 CMD1 PEC0 PEC1 Poll Data

Table 28. Broadcast Write Command (LTC6804-1)

8 8 8 8 8 8 8 8 8 8
CMD0 CMD1 PEC0 PEC1 Data Byte Low … Data Byte High PEC0 PEC1 Shift Byte 1 … Shift Byte n

Table 29.Broadcast/Address Write Command (LTC6804-2)

8 8 8 8 8 8 8 8
CMD0 CMD1 PEC0 PEC1 Data Byte Low … Data Byte High PEC0 PEC1

Table 30. Broadcast Read Command (LTC6804-1)

8 8 8 8 8 8 8 8 8 8
CMD0 CMD1 PEC0 PEC1 Data Byte Low … Data Byte High PEC0 PEC1 Shift Byte 1 … Shift Byte n

Table 31. Address Read Command (LTC6804-2)

8 8 8 8 8 8 8 8
CMD0 CMD1 PEC0 PEC1 Data Byte Low … Data Byte High PEC0 PEC1

Table 32. Broadcast Command Format

NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CMD0 WR 0 0 0 0 0 CC[10] CC[9] CC[8]
CMD1 WR CC[7] CC[6] CC[5] CC[4] CC[3] CC[2] CC[1] CC[0]

Table 33. Address Command Format

NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CMD0 WR 1 a3* a2* a1* a0* CC[10] CC[9] CC[8]
CMD1 WR CC[7] CC[6] CC[5] CC[4] CC[3] CC[2] CC[1] CC[0]
*ax is Address Bit x

680412fc

48 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Table 34. Command Codes
COMMAND DESCRIPTION NAME CC[10:0] - COMMAND CODE
10 9 8 7 6 5 4 3 2 1 0
Write Configuration WRCFG 0 0 0 0 0 0 0 0 0 0 1
Register Group
Read Configuration RDCFG 0 0 0 0 0 0 0 0 0 1 0
Register Group
Read Cell Voltage RDCVA 0 0 0 0 0 0 0 0 1 0 0
Register Group A
Read Cell Voltage RDCVB 0 0 0 0 0 0 0 0 1 1 0
Register Group B
Read Cell Voltage RDCVC 0 0 0 0 0 0 0 1 0 0 0
Register Group C
Read Cell Voltage RDCVD 0 0 0 0 0 0 0 1 0 1 0
Register Group D
Read Auxiliary RDAUXA 0 0 0 0 0 0 0 1 1 0 0
Register Group A
Read Auxiliary RDAUXB 0 0 0 0 0 0 0 1 1 1 0
Register Group B
Read Status Register Group A RDSTATA 0 0 0 0 0 0 1 0 0 0 0
Read Status Register Group B RDSTATB 0 0 0 0 0 0 1 0 0 1 0
Start Cell Voltage ADC ADCV 0 1 MD[1] MD[0] 1 1 DCP 0 CH[2] CH[1] CH[0]
Conversion and Poll Status
Start Open Wire ADC Con- ADOW 0 1 MD[1] MD[0] PUP 1 DCP 1 CH[2] CH[1] CH[0]
version and Poll Status
Start Self-Test Cell Voltage CVST 0 1 MD[1] MD[0] ST[1] ST[0] 0 0 1 1 1
Conversion and Poll Status
Start GPIOs ADC Conversion ADAX 1 0 MD[1] MD[0] 1 1 0 0 CHG [2] CHG [1] CHG [0]
and Poll Status
Start Self-Test GPIOs AXST 1 0 MD[1] MD[0] ST[1] ST[0] 0 0 1 1 1
Conversion and Poll Status
Start Status group ADC ADSTAT 1 0 MD[1] MD[0] 1 1 0 1 CHST [2] CHST [1] CHST [0]
Conversion and Poll Status
Start Self-Test Status group STATST 1 0 MD[1] MD[0] ST[1] ST[0] 0 1 1 1 1
Conversion and Poll Status
Start Combined Cell ADCVAX 1 0 MD[1] MD[0] 1 1 DCP 1 1 1 1
Voltage and GPIO1, GPIO2
Conversion and Poll Status
Clear Cell Voltage CLRCELL 1 1 1 0 0 0 1 0 0 0 1
Register Group
Clear Auxiliary CLRAUX 1 1 1 0 0 0 1 0 0 1 0
Register Group
Clear Status Register Group CLRSTAT 1 1 1 0 0 0 1 0 0 1 1
Poll ADC Conversion Status PLADC 1 1 1 0 0 0 1 0 1 0 0
Diagnose MUX and Poll DIAGN 1 1 1 0 0 0 1 0 1 0 1
Status
Write COMM Register Group WRCOMM 1 1 1 0 0 1 0 0 0 0 1
Read COMM Register Group RDCOMM 1 1 1 0 0 1 0 0 0 1 0
Start I2C/SPI Communication STCOMM 1 1 1 0 0 1 0 0 0 1 1
680412fc

For more information www.linear.com/LTC6804-1 49

LTC6804-1/LTC6804-2
Operation
Table 35. Command Bit Descriptions
NAME DESCRIPTION VALUES
MD ADCOPT(CFGR0[0]) = 0 ADCOPT (CFGR0[0]) = 1
01 27kHz Mode (Fast) 14kHz Mode
MD[1:0] ADC Mode
10 7kHz Mode (Normal) 3kHz Mode
11 26Hz Mode (Filtered) 2kHz Mode
DCP
DCP Discharge Permitted 0 Discharge Not Permitted
1 Discharge Permitted
Total Conversion Time in the 6 ADC Modes
CH 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz
000 All Cells 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 201ms
001 Cell 1 and Cell 7
CH[2:0] Cell Selection for ADC Conversion 010 Cell 2 and Cell 8
011 Cell 3 and Cell 9
201µs 230µs 405µs 501µs 754µs 34ms
100 Cell 4 and Cell 10
101 Cell 5 and Cell 11
110 Cell 6 and Cell 12
PUP
Pull-Up/Pull-Down Current for
PUP 0 Pull-Down Current
Open-Wire Conversions
1 Pull-Up Current
Self-Test Conversion Result
ST 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz
ST[1:0] Self-Test Mode Selection
01 Self Test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555
10 Self test 2 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA
Total Conversion Time in the 6 ADC Modes
CHG 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz
000 GPIO 1-5, 2nd Ref 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 201ms
001 GPIO 1
CHG[2:0] GPIO Selection for ADC Conversion 010 GPIO 2
011 GPIO 3
201µs 230µs 405µs 501µs 754µs 34ms
100 GPIO 4
101 GPIO 5
110 2nd Reference
Total Conversion Time in the 6 ADC Modes
CHST 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz
000 SOC, ITMP, VA, VD 748µs 865µs 1.6ms 2.0ms 3.0ms 134ms
CHST[2:0]* Status Group Selection 001 SOC
010 ITMP
201µs 230µs 405µs 501µs 754µs 34ms
011 VA
100 VD**
*Note: Valid options for CHST in ADSTAT command are 0-4. If CHST is set to 5/6 in ADSTAT command, the LTC6804 treats it like ADAX command with
CHG = 5/6.
**The use of the ADSTAT command with CHST = 100 is not recommended unless special care is taken. See the Data Acquisition System Diagnostics
section for more details.
680412fc

50 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Table 36. Configuration Register Group
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CFGR0 RD/WR GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 REFON SWTRD ADCOPT
CFGR1 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[0]
CFGR2 RD/WR VOV[3] VOV[2] VOV[1] VOV[0] VUV[11] VUV[10] VUV[9] VUV[8]
CFGR3 RD/WR VOV[11] VOV[10] VOV[9] VOV[8] VOV[7] VOV[6] VOV[5] VOV[4]
CFGR4 RD/WR DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1
CFGR5 RD/WR DCTO[3] DCTO[2] DCTO[1] DCTO[0] DCC12 DCC11 DCC10 DCC9

Table 37. Cell Voltage Register Group A

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVAR0 RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0]
CVAR1 RD C1V[15] C1V[14] C1V[13] C1V[12] C1V[11] C1V[10] C1V[9] C1V[8]
CVAR2 RD C2V[7] C2V[6] C2V[5] C2V[4] C2V[3] C2V[2] C2V[1] C2V[0]
CVAR3 RD C2V[15] C2V[14] C2V[13] C2V[12] C2V[11] C2V[10] C2V[9] C2V[8]
CVAR4 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[0]
CVAR5 RD C3V[15] C3V[14] C3V[13] C3V[12] C3V[11] C3V[10] C3V[9] C3V[8]

Table 38. Cell Voltage Register Group B

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVBR0 RD C4V[7] C4V[6] C4V[5] C4V[4] C4V[3] C4V[2] C4V[1] C4V[0]
CVBR1 RD C4V[15] C4V[14] C4V[13] C4V[12] C4V[11] C4V[10] C4V[9] C4V[8]
CVBR2 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[0]
CVBR3 RD C5V[15] C5V[14] C5V[13] C5V[12] C5V[11] C5V[10] C5V[9] C5V[8]
CVBR4 RD C6V[7] C6V[6] C6V[5] C6V[4] C6V[3] C6V[2] C6V[1] C6V[0]
CVBR5 RD C6V[15] C6V[14] C6V[13] C6V[12] C6V[11] C6V[10] C6V[9] C6V[8]

Table 39. Cell Voltage Register Group C

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVCR0 RD C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[0]
CVCR1 RD C7V[15] C7V[14] C7V[13] C7V[12] C7V[11] C7V[10] C7V[9] C7V[8]
CVCR2 RD C8V[7] C8V[6] C8V[5] C8V[4] C8V[3] C8V[2] C8V[1] C8V[0]
CVCR3 RD C8V[15] C8V[14] C8V[13] C8V[12] C8V[11] C8V[10] C8V[9] C8V[8]
CVCR4 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[0]
CVCR5 RD C9V[15] C9V[14] C9V[13] C9V[12] C9V[11] C9V[10] C9V[9] C9V[8]

Table 40. Cell Voltage Register Group D

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVDR0 RD C10V[7] C10V[6] C10V[5] C10V[4] C10V[3] C10V[2] C10V[1] C10V[0]
CVDR1 RD C10V[15] C10V[14] C10V[13] C10V[12] C10V[11] C10V[10] C10V[9] C10V[8]
CVDR2 RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[0]
CVDR3 RD C11V[15] C11V[14] C11V[13] C11V[12] C11V[11] C11V[10] C11V[9] C11V[8]
CVDR4 RD C12V[7] C12V[6] C12V[5] C12V[4] C12V[3] C12V[2] C12V[1] C12V[0]
CVDR5 RD C12V[15] C12V[14] C12V[13] C12V[12] C12V[11] C12V[10] C12V[9] C12V[8]
680412fc

For more information www.linear.com/LTC6804-1 51

LTC6804-1/LTC6804-2
Operation
Table 41. Auxiliary Register Group A
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AVAR0 RD G1V[7] G1V[6] G1V[5] G1V[4] G1V[3] G1V[2] G1V[1] G1V[0]
AVAR1 RD G1V[15] G1V[14] G1V[13] G1V[12] G1V[11] G1V[10] G1V[9] G1V[8]
AVAR2 RD G2V[7] G2V[6] G2V[5] G2V[4] G2V[3] G2V[2] G2V[1] G2V[0]
AVAR3 RD G2V[15] G2V[14] G2V[13] G2V[12] G2V[11] G2V[10] G2V[9] G2V[8]
AVAR4 RD G3V[7] G3V[6] G3V[5] G3V[4] G3V[3] G3V[2] G3V[1] G3V[0]
AVAR5 RD G3V[15] G3V[14] G3V[13] G3V[12] G3V[11] G3V[10] G3V[9] G3V[8]

Table 42. Auxiliary Register Group B

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AVBR0 RD G4V[7] G4V[6] G4V[5] G4V[4] G4V[3] G4V[2] G4V[1] G4V[0]
AVBR1 RD G4V[15] G4V[14] G4V[13] G4V[12] G4V[11] G4V[10] G4V[9] G4V[8]
AVBR2 RD G5V[7] G5V[6] G5V[5] G5V[4] G5V[3] G5V[2] G5V[1] G5V[0]
AVBR3 RD G5V[15] G5V[14] G5V[13] G5V[12] G5V[11] G5V[10] G5V[9] G5V[8]
AVBR4 RD REF[7] REF[6] REF[5] REF[4] REF[3] REF[2] REF[1] REF[0]
AVBR5 RD REF[15] REF[14] REF[13] REF[12] REF[11] REF[10] REF[9] REF[8]

Table 43. Status Register Group A

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STAR0 RD SOC[7] SOC[6] SOC[5] SOC[4] SOC[3] SOC[2] SOC[1] SOC[0]
STAR1 RD SOC[15] SOC[14] SOC[13] SOC[12] SOC[11] SOC[10] SOC[9] SOC[8]
STAR2 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[0]
STAR3 RD ITMP[15] ITMP[14] ITMP[13] ITMP[12] ITMP[11] ITMP[10] ITMP[9] ITMP[8]
STAR4 RD VA[7] VA[6] VA[5] VA[4] VA[3] VA[2] VA[1] VA[0]
STAR5 RD VA[15] VA[14] VA[13] VA[12] VA[11] VA[10] VA[9] VA[8]

Table 44. Status Register Group B

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STBR0 RD VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0]
STBR1 RD VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8]
STBR2 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV
STBR3 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV
STBR4 RD C12OV C12UV C11OV C11UV C10OV C10UV C9OV C9UV
STBR5 RD REV[3] REV[2] REV[1] REV[0] RSVD RSVD MUXFAIL THSD

Table 45. COMM Register Group

REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMM0 RD/WR ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4]
COMM1 RD/WR D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0]
COMM2 RD/WR ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4]
COMM3 RD/WR D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0]
COMM4 RD/WR ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4]
COMM5 RD/WR D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0]
680412fc

52 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Table 46. Memory Bit Descriptions
NAME DESCRIPTION VALUES
GPIOx GPIOx Pin Control Write: 0 -> GPIOx Pin Pull-Down ON; 1-> GPIOx Pin Pull-Down OFF (Default)
Read: 0 -> GPIOx Pin at Logic 0; 1 -> GPIOx Pin at Logic 1
REFON Reference 1 -> Reference Remains Powered Up Until Watchdog Timeout
Powered Up 0 -> Reference Shuts Down after Conversions (Default)
SWTRD SWTEN Pin Status 1 -> SWTEN Pin at Logic 1
(Read Only) 0 -> SWTEN Pin at Logic 0
ADCOPT ADC Mode Option ADCOPT: 0 -> Selects Modes 27kHz, 7kHz or 26Hz with MD[1:0] Bits in ADC Conversion Commands (Default).
Bit 1 -> Selects Modes 14kHz, 3kHz or 2kHz with MD[1:0] Bits in ADC Conversion Commands.
VUV Undervoltage Comparison voltage = (VUV + 1) • 16 • 100µV
Comparison Default: VUV = 0x000
Voltage*
VOV Overvoltage Comparison voltage = VOV • 16 • 100µV
Comparison Default: VOV = 0x000
Voltage*
DCC[x] Discharge Cell x x = 1 to 12 1 -> Turn ON Shorting Switch for Cell x
0 -> Turn OFF Shorting Switch for Cell x (Default)
DCTO Discharge Time DCTO 0 1 2 3 4 5 6 7 8 9 A B C D E F
Out Value (Write)
Time Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120
(Min)
DCTO 0 1 2 3 4 5 6 7 8 9 A B C D E F
(Read)
Time Disabled 0 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90
Left or to to to to to to to to to to to to to to to
(Min) Timeout 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90
120
CxV Cell x Voltage* x = 1 to 12 16-Bit ADC Measurement Value for Cell x
Cell Voltage for Cell x = CxV • 100µV
CxV Is Reset to 0xFFFF on Power-Up and After Clear Command
GxV GPIO x Voltage* x = 1 to 5 16-Bit ADC Measurement Value for GPIOx
Voltage for GPIOx = GxV • 100µV
GxV Is Reset to 0xFFFF on Power-Up and After Clear Command
REF 2nd Reference 16-Bit ADC Measurement Value for 2nd Reference
Voltage* Voltage for 2nd Reference = REF • 100µV
Normal Range Is within 2.985V to 3.015V
SOC Sum of Cells 16-Bit ADC Measurement Value of the Sum of All Cell Voltages
Measurement* Sum of All Cells Voltage = SOC • 100µV • 20
ITMP Internal Die 16-Bit ADC Measurement Value of Internal Die Temperature
Temperature* Temperature Measurement (°C) = ITMP • 100µV/7.5mV/°C – 273°C
VA Analog Power 16-Bit ADC Measurement Value of Analog Power Supply Voltage
Supply Voltage* Analog Power Supply Voltage = VA • 100µV
Normal Range Is within 4.5V to 5.5V
VD Digital Power 16-Bit ADC Measurement Value of Digital Power Supply Voltage
Supply Voltage* Digital Power Supply Voltage = VA • 100µV
Normal Range Is within 2.7V to 3.6V
CxOV Cell x Overvoltage x = 1 to 12 Cell Voltage Compared to VOV Comparison Voltage
Flag 0 -> Cell x Not Flagged for Overvoltage Condition. 1 -> Cell x Flagged
CxUV Cell x x = 1 to 12 Cell Voltage Compared to VUV Comparison Voltage
Undervoltage Flag 0 -> Cell x Not Flagged for Undervoltage Condition. 1 -> Cell x Flagged
REV Revision Code Device Revision Code. See Revision Code and Reserved Bits in Operation Section.
RSVD Reserved Bits See Revision Code and Reserved Bits in Operation Section.

680412fc

For more information www.linear.com/LTC6804-1 53

LTC6804-1/LTC6804-2
Operation
Table 46. Memory Bit Descriptions
NAME DESCRIPTION VALUES
MUXFAIL Multiplexer Self- Read: 0 -> Multiplexer Passed Self Test 1 -> Multiplexer Failed Self Test
Test Result
THSD Thermal Read: 0 -> Thermal Shutdown Has Not Occurred 1 -> Thermal Shutdown Has Occurred
Shutdown Status THSD Bit Cleared to 0 on Read of Status RegIster Group B
ICOMn Initial Write I2C 0110 0001 0000 0111
Communication START STOP BLANK NO TRANSMIT
Control Bits
SPI 1000 1001 1111
CSB Low CSB High NO TRANSMIT
Read I2C 0110 0001 0000 0111
START from Master STOP from Master SDA Low Between Bytes SDA High Between
Bytes
SPI 0111
Dn I2C/SPI Data Transmitted (Received) to (From) I2C/SPI Slave Device
Communication
Data Byte
FCOMn Final Write I2C 0000 1000 1001
Communication Master ACK Master NACK Master NACK + STOP
Control Bits
SPI X000 1001
CSB Low CSB High
Read I2C 0000 0111 1111 0001 1001
ACK from Master ACK from Slave NACK from Slave ACK from Slave + NACK from Slave
STOP from Master + STOP from
Master
SPI 1111
*Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.

Programming Examples 4. Wait for the amount of time 3 • tREADY

The following examples use a configuration of 3 stacked 5. Send commands
LTC6804-1 devices: S1, S2, S3. Port A on device S1 is
configured in SPI mode (ISOMD pin low). Port A on de- Write Configuration Registers
vices S2 and S3 is configured in isoSPI mode (ISOMD pin 1. Pull CSB low
high). Port B on S1 is connected to Port A on S2. Port B
2. Send WRCFG command (0x00 0x01) and its PEC (0x3D
on S2 is connected to Port A on S3. The microcontroller
0x6E)
communicates to the stack through Port A on S1.
3. Send CFGR0 byte of device S3, then CFGR1(S3), …
Waking Up Serial Interface CFGR5(S3), PEC of CFGR0(S3) to CFGR5(S3)
1. Send a dummy byte. The activity on CSB and SCK will 4. Send CFGR0 byte of device S2, then CFGR1(S2), …
wake up the serial interface on device S1. CFGR5(S2), PEC of CFGR0(S2) to CFGR5(S2)
2. Wait for the amount of time 3 • tWAKE in order to power 5. Send CFGR0 byte of device S1, then CFGR1(S1), …
up all devices S1, S2 and S3. CFGR5(S1), PEC of CFGR0(S1) to CFGR5(S1)
For large stacks where some devices may go to the IDLE 6. Pull CSB high, data latched into all devices on rising
state after waking, apply steps 3 and 4: edge of CSB

3. Send a second dummy byte.

680412fc

54 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Calculation of serial interface time for sequence above: Clear Cell Voltage Registers
Number of LTC6804-1s in daisy chain stack = n 1. Pull CSB low
Number of bytes in sequence (B): 2. Send CLRCELL command (0x07 0x11) and its PEC
Command: 2 (command byte) + 2 (command PEC) = 4 (0xC9 0xC0)
3. Pull CSB high
Data: 6 (Data bytes) + 2 (Data PEC) per LTC6804 = 8
bytes per device Poll ADC Status
B=4+8•n (Parallel configuration and ISOMD = 0)
Serial port frequency per bit = F This example uses an addressed LTC6804-2 with address
Time = (1/F) • B • 8 bits/byte = (1/F) • [4 + 8 • n] • 8 A [3:0] = 0011 and ISOMD = 0
Time for 3 LTC6804 example above, with 1MHz serial 1. Pull CSB low
port = (1/1e6) • (4 + 8 • 3) • 8 = 224µs 2. Send PLADC command (0x9F 0x14) and its PEC (0x1C
Note: This time will remain the same for all write and read 0x48 )
commands. 3. SDO output is pulled low if the LTC6804-2 is busy. The
host needs to send clocks on SCK in order for the poll-
Read Cell Voltage Register Group A
ing status to be updated from the addressed device.
1. Pull CSB low
4. SDO output is high when the LTC6804-2 has completed
2. Send RDCVA command (0x00 0x04) and its PEC (0x07 conversions
0xC2)
5. Pull CSB high to exit polling
3. Read CVAR0 byte of device S1, then CVAR1(S1), …
CVAR5(S1), PEC of CVAR0(S1) to CVAR5(S1) Talk to an I2C Slave Connected to LTC6804
4. Read CVAR0 byte of device S2, then CVAR1(S2), … The LTC6804 supports I2C slave devices by connection to
CVAR5(S2), PEC of CVAR0(S2) to CVAR0(S2) GPIO4(SDA) and GPIO5(SCL). One valuable use for this
5. Read CVAR0 byte of device S3, then CVAR1(S3), … capability is to store production calibration constants or
CVAR5(S3), PEC of CVAR0(S3) to CVAR5(S3) other information in a small serial EEPROM using a con-
nection like shown in Figure 25.
6. Pull CSB high
VREG
Start Cell Voltage ADC Conversion 4.7k 4.7k
1µF
LTC6804
10V
(All cells, normal mode with discharge permitted) and SCL GPIO5(SCL)
WP
poll status 24AA01 VSS GPIO4(SDA)
VCC
1. Pull CSB low SDA

V–
2. Send ADCV command with MD[1:0] = 10 and DCP = 1
i.e. 0x03 0x70 and its PEC (0xAF 0x42) 680412 F25

3. Pull CSB high Figure 25. Connecting I2C EEPROM to LTC6804 GPIO Pins

680412fc

For more information www.linear.com/LTC6804-1 55

LTC6804-1/LTC6804-2
Operation
This example uses a single LTC6804-1 to write a byte 3. Data transmitted to slave during the STCOMM com-
of data to an I2C EEPROM. The LTC6804 will send three mand is stored in the COMM register. Use the RDCOMM
bytes of data to the I2C slave device. The data sent will be command to retrieve the data
B0 = 0xA0 (EEPROM address), B1 = 0x01 (write com- a. Pull CSB low
mand), and B2 = 0xAA (data to be stored in EEPROM).
The three bytes will be transmitted to the I2C slave device b. Send RDCOMM command (0x07 0x22) and its PEC
in the following format: (0x32 0xD6)
c. Read COMM0-COMM5 and the PEC for the 6 bytes
START – B0 – NACK – B1 – NACK – B2 – NACK – STOP
of data.
1. Write data to COMM register using WRCOMM command
Assuming the slave acknowledged all 3 bytes of data,
a. Pull CSB low the read back data in this example would look like:
b. Send WRCOMM command (0x07 0x21) and its PEC COMM0 = 0x6A, COMM1 = 0x07, COMM2 = 0x70,
(0x24 0xB2) COMM3 = 0x17, COMM4 = 0x7A, COMM5 = 0xA1,
c. Send PEC = 0xD0 0xDE
COMM0 = 0x6A, COMM1 = 0x08 ([START] [B0] d. Pull CSB high
[NACK]),
Note: If the slave returns data, this data will be placed in
COMM2 = 0x00, COMM3 = 0x18 ([BLANK] [B1] COMM0-COMM5.
[NACK]),
Figure 26 shows the activity on GPIO5 (SCL) and GPIO4
COMM4 = 0x0A, COMM5 = 0xA9 ([BLANK] [B2] (SDA) ports of the I2C master for 72 clock cycles during
[NACK+STOP]) the STCOMM command in the above example.
and PEC = 0x6D 0xFB for the above data
d. Pull CSB high
2. Send the 3 bytes of data to I2C slave device using
STCOMM command
a. Pull CSB low
b. Send STCOMM command (0x07 0x23) and its PEC
(0xB9 0xE4)
c. Send 72 clock cycles on SCK
d. Pull CSB high

SCK

SCL (GPIO5)

SDA (GPIO4)

0xA0 0x01 0xAA

START STOP
LAST CLOCK OF ACK FROM SLAVE ACK FROM SLAVE ACK FROM SLAVE
STCOMM COMMAND 680412 F26

Figure 26. LTC6804 I2C Communication Example

680412fc

56 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Operation
Talk to a SPI Slave Connected to LTC6804 3. Data transmitted to slave during the STCOMM com-
mand is stored in the COMM register. Use the RDCOMM
This example uses a single LTC6804-1 device which has a
command to retrieve the data.
SPI device connected to it through GPIO3 (CSBM), GPIO4
(SDOM) and GPIO5 (SCKM). In this example, the LTC6804 a. Pull CSB low
device sends out 3 bytes of data B0 = 0x55, B1 = 0xAA b. Send RDCOMM command (0x07 0x22) and its PEC
and B2 = 0xCC to the SPI slave device in the following (0x32 0xD6)
format: CSB low – B0 – B1 – B2 – CSB high
c. Read COMM0-COMM5 and the PEC for the 6 bytes
1. Write data to COMM register using WRCOMM command of data. The read back data in this example would
a. Pull CSBM low look like:
b. Send WRCOMM command (0x07 0x21) and its PEC COMM0 = 0x755F, COMM1 = 0x7AAF, COMM2 =
(0x24 0xB2) 7CCF, PEC = 0xF2BA
c. Send d. Pull CSB high
COMM0 = 0x85, COMM1 = 0x50 ([CSBM low] Note: If the slave returns data, this data will be placed in
[B0] [CSBM low]), COMM0-COMM5.
COMM2 = 0x8A, COMM3 = 0xA0 ([CSBM low] Figure 27 shows the activity on GPIO3 (CSBM), GPIO5
[B1] [CSBM low]), (SCKM) and GPIO4 (SDOM) ports of SPI master for 72
COMM4 = 0x8C, COMM5 = 0xC9 ([CSBM low] clock cycles during the STCOMM command in the above
[B2] [CSBM high]) example.
and PEC = 0x89 0xA4 for the above data.
d. Pull CSB high
2. Send the 3 bytes of data to SPI slave device using
STCOMM command
a. Pull CSB low
b. Send STCOMM command (0x07 0x23) and its PEC
(0xB9 0xE4)
c. Send 72 clock cycles on SCK
d. Pull CSB high

SCK

CSBM (GPIO3)

SCKM (GPIO5)

SDOM (GPIO4)

0x55 0xAA 0xCC

CSBM LOW CSBM HIGH
LAST CLOCK OF
STCOMM COMMAND 680412 F27

Figure 27. LTC6804 SPI Communication Example

680412fc

For more information www.linear.com/LTC6804-1 57

LTC6804-1/LTC6804-2
Applications Information
Simple Linear Regulator Improved Regulator Power Efficiency
The LTC6804 draws most of its power from the VREG input To minimize power consumption within the LTC6804, the
pin. 5V ±0.5V should be applied to VREG. A regulated DC/ current drawn on the V+ pin has been designed to be very
DC converter can power VREG directly, or the DRIVE pin small (500µA). The voltage on the V+ pin must be at least
may be used to form a discrete regulator with the addition as high as the top cell to provide accurate measurement.
of a few external components. When active, the DRIVE The V+ and VREG pins can be unpowered to provide an
output pin provides a low current 5.6V output that can exceptionally low battery drain shutdown mode. In many
be buffered using a discrete NPN transistor, as shown in applications, the V+ will be permanently connected to
Figure 28. The collector power for the NPN can come from the top cell potential through a decoupling RC to protect
any potential of 6V or more above V–, including the cells against transients (100Ω/100nF is recommended).
being monitored or an unregulated converter supply. A
For better running efficiency when powering from the cell
100Ω/100nF RC decoupling network is recommended for
stack, the VREG may be powered from a buck converter
the collector power connection to protect the NPN from rather than the NPN pass transistor. An ideal circuit for
transients. The emitter of the NPN should be bypassed this is based on the LT3990 as shown in Figure 29. A 1k
with a 1µF capacitor. Larger capacitor values should be resistor should be used in series with the input to prevent
avoided because they increase the wake-up time of the inrush current when connecting to the stack and to reduce
LTC6804. Some attention to the thermal characteristic conducted EMI. The EN/UVLO pin should be connected to
of the NPN is needed, as there can be significant heating DRIVE so that the converter sleeps along with the LTC6804.
with a high collector voltage. The LTC6804 watchdog timer requires VREG power to
timeout. Therefore, if the EN/UVLO pin is not connected
to DRIVE, care must be taken to allow the LTC6804 to
100Ω
LTC6804 timeout first before removing VREG power; otherwise the
WDT
0.1µF LTC6804 will not enter sleep mode.
DRIVE NSV1C201MZ4
VREG
SWTEN VIN 1k
VREF1 28V TO
VREF2 1µF 62V 0.22µF
VIN BOOST
GPIO5
1µF LT3990 33µH
GPIO4 VREG
1µF OFF ON EN/UVLO SW 5V
V–
PG BD 40mA
V–
GPIO3 2.2µF 22pF 1M
680412 F28
RT FB 22µF
GND
374k 316k

Figure 28. Simple VREG Power Source Using f = 400kHz 680412 F29

NPN Pass Transistor

Figure 29. VREG Powered from Cell Stack with High Efficiency

680412fc

58 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
Fully Isolated Power current from conducting through internal parasitic paths
inside the IC when the isolated power is removed.
A simple DC/DC flyback converter can provide isolated
power for an LTC6804 from a remote 12V power source
as shown in Figure 30. This circuit, along with the isoSPI Reading External Temperature Probes
transformer isolation, results in LTC6804 circuitry that is Figure 31 shows the typical biasing circuit for a negative-
completely floating and uses almost no power from the temperature-coefficient (NTC) thermistor. The 10kΩ at 25°C
batteries. Aside from reducing the amount of circuitry is the most popular sensor value and the VREF2 output stage
that operates at battery potential, such an arrangement is designed to provide the current required to directly bias
prevents battery load imbalance. The LTC6804 watchdog several of these probes. The biasing resistor is selected
timer requires VREG power to timeout. Therefore, care to correspond to the NTC value so the circuit will provide
must be taken to allow the LTC6804 to timeout first before 1.5V at 25°C (VREF2 is 3V nominal). The overall circuit
removing VREG power; otherwise the LTC6804 will not response is approximately –1%/°C in the range of typical
enter sleep mode. A diode should be added between the cell temperatures, as shown in the chart of Figure 31 .
V+ and the top cell being monitored. This will prevent any
CONNECT TO TOP CELL
12VRETURN 130k CMHD459A 100Ω
52V
V+
8 CMHZ5265B 100nF
22.1k RFB CMMSH1-40 LTC6804
SW •1 13V 62V 100V
LT8300 5
GND VIN
4• 4.7µF NSV1C201MZ4
EN/UVLO 7 25V 1µF DRIVE
4.7µF 100V
100k •2 VREG
25V
PA0648NL 1µF
12V
10V
V–
680412 F30

Figure 30. Powering LTC6804 from a Remote 12V Source

100
90

VREF2 80
70
VTEMPx (% VREF2)

10k
60
VTEMP 50
NTC 40
10k AT 25°C
30
V–
20
10
0
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
680412 F31

Figure 31. Typical Temperature Probe Circuit and Relative Output

680412fc

For more information www.linear.com/LTC6804-1 59

LTC6804-1/LTC6804-2
Applications Information
Expanding the Number of Auxiliary Filtering of Cell and GPIO Inputs
Measurements The LTC6804 uses a delta-sigma ADC, which has delta-
The LTC6804 provides five GPIO pins, each of which is sigma modulator followed by a SINC3 finite impulse
capable of performing as an ADC input. In some applica- response (FIR) digital filter. This greatly reduces input
tions there is need to measure more signals than this, so filtering requirements. Furthermore, the programmable
one means of supporting higher signal count is to add oversampling ratio allows the user to determine the best
a MUX circuit such as shown in Figure 32. This circuit trade-off between measurement speed and filter cutoff
digitizes up to sixteen source signals using the GPIO1 frequency. Even with this high order lowpass filter, fast
ADC input and MUX control is provided by two other transient noise can still induce some residual noise in mea-
GPIO lines configured as an I2C port. The buffer amplifier surements, especially in the faster conversion modes. This
provides for fast settling of the selected signal to increase can be minimized by adding an RC lowpass decoupling to
the usable conversion rate. each ADC input, which also helps reject potentially damag-
ing high energy transients. Adding more than about 100Ω
Internal Protection Features to the ADC inputs begins to introduce a systematic error
in the measurement, which can be improved by raising
The LTC6804 incorporates various ESD safeguards to en- the filter capacitance or mathematically compensating in
sure a robust performance. An equivalent circuit showing software with a calibration procedure. For situations that
the specific protection structures is shown in Figure 33. demand the highest level of battery voltage ripple rejec-
While pins 43 to 48 have different functionality for the tion, grounded capacitor filtering is recommended. This
-1 and -2 variants, the protection structure is the same. configuration has a series resistance and capacitors that
Zener-like suppressors are shown with their nominal clamp decouple HF noise to V–. In systems where noise is less
voltage, other diodes exhibit standard PN junction behavior.

1 16
ANALOG1 S0 VCC
2 15
ANALOG2 S1 SCL LTC6804
3 14 4.7k 4.7k 1µF 37
ANALOG3 S2 SDA VREG
4 13 33
ANALOG4 S3 A0 GPIO5(SCL)
5 LTC1380 12 32
ANALOG5 S4 A1 GPIO4(SDA)
6 11
ANALOG6 S5 GND 31 –
7 10 V
ANALOG7 S6 VEE
8 9 3 5
ANALOG8 S7 DO +
1 100Ω 27
LTC6255 GPIO1
1 16 4
ANALOG9
2
S0 VCC
15
– 2
ANALOG10 S1 SCL 10nF
3 14
ANALOG11 S2 SDA
4 13
ANALOG12 S3 A0
5 LTC1380 12
ANALOG13 S4 A1 680412 F32
6 11
ANALOG14 S5 GND
7 10
ANALOG15 S6 VEE
8 9
ANALOG16 S7 DO

ANALOG INPUTS: 0.04V TO 4.5V

Figure 32. MUX Circuit Supports Sixteen Additional Analog Measurements

680412fc

60 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
C12 LTC6804 V+ periodic or higher oversample rates are in use, a differential
2 1
30V
capacitor filter structure is adequate. In this configuration
10k
3
S12
there are series resistors to each input, but the capacitors
12V 30V
C11
12V connect between the adjacent C pins. However, the dif-
4 30V
ferential capacitor sections interact. As a result, the filter
10k 12V
5
S11
IPB/A3
48
response is less consistent and results in less attenuation
12V
C10
12V
12V
than predicted by the RC, by approximately a decade. Note
30V
6 IMB/A2
47 that the capacitors only see one cell of applied voltage (thus
10k
7
S10 12V smaller and lower cost) and tend to distribute transient
ICMP/A1
C9
12V
12V 46 energy uniformly across the IC (reducing stress events on
8 12V
IBIAS/A0
the internal protection structure). Figure 34 shows the two
9
S9 10k 45
methods schematically. Basic ADC accuracy varies with R,
12V
12V
12V
SDO
44
C as shown in the Typical Performance curves, but error is
C8
10
12V
minimized if R = 100Ω and C = 10nF. The GPIO pins will
11
S8 10k SDI
43 always use a grounded capacitor configuration because
12V
12V
12V the measurements are all with respect to V–.
C7 SCK
12 42

S7 10k 12V 100Ω

13 CSB CELL2 C2
12V 41
12V BSS308PE 3.3k
C6 12V S2
14 30V 33Ω
ISOMD
40 LTC6804
10k 10nF
S6 100Ω
15 12V CELL1 C1
12V WDT
12V 39 BSS308PE 3.3k
C5 S1
16 12V 33Ω
DRIVE 10nF
S5 10k 38 100Ω
17 C0
12V 12V
12V VREG 10nF
C4 37
18 BATTERY V– V–
12V
S4 10k SWTEN
19 36
12V Differential Capacitor Filter
12V 12V
C3 VREF1
20 35

S3 10k 12V 100Ω

21 VREF2 CELL2 C2
12V 34 3.3k
12V BSS308PE
C2 12V S2
22 33Ω
GPIO5 C * LTC6804
30V 33
S2 10k 100Ω
23 12V CELL1 C1
12V GPIO4 BSS308PE 3.3k
12V 32 S1
C1
24 12V 33Ω C
GPIO3 *
S1 10k 29 100Ω
25 C0
12V 12V C
12V GPIO2 *
C0 28
26 BATTERY V– V–
12V 680412 F34

V– GPIO1 *6.8V ZENERS RECOMMENDED IF C > 100nF

31 27
V– 25Ω Grounded Capacitor Filter
30
680412 F33

NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 31
Figure 34. Input Filter Structure Configurations

Figure 33. Internal ESD Protection Structure of LTC6804

680412fc

For more information www.linear.com/LTC6804-1 61

LTC6804-1/LTC6804-2
Applications Information
Cell Balancing with Internal Mosfets RFILTER LTC6804
C(n)
The S1 through S12 pins are used to balance battery cells.
If one cell in a series becomes overcharged, an S output
can be used to discharge the cell. Each S output has an + RDISCHARGE

internal N-channel MOSFET for discharging. The NMOS S(n)

has a maximum on resistance of 20Ω. An external resistor RFILTER

should be connected in series with the NMOS to dissipate C(n – 1)
heat outside of the LTC6804 package as illustrated in 680412 F35

Figure 35. It is still possible to use an RC to add additional Figure 35. Internal Discharge Circuit
filtering to cell voltage measurements but the filter R must
remain small, typically around 10Ω to reduce the effect LTC6804
on the programmed balance current. When using the C(n)
internal MOSFETs to discharge cells, the die temperature + BSS308PE
should be monitored. See Power Dissipation and Thermal R
S(n)
Shutdown section. 3.3k
C(n – 1)
680412 F36

Cell Balancing with External MOSFETS Figure 36. External Discharge Circuit

The S outputs include an internal pull-up PMOS transistor.

The S pins can act as digital outputs suitable for driving Discharge Control During Cell
the gate of an external MOSFET. For applications requiring Measurements
high battery discharge currents, connect a discrete PMOS If the discharge permited (DCP) command bit is high in a
switch device and suitable discharge resistor to the cell, cell measurement command, then the S pin discharge states
and the gate terminal to the S output pin, as illustrated in are not altered during the cell measurements. However, if
Figure 36. Figure 34 shows external MOSFET circuits that the DCP bit is low, any discharge that is turned on will be
include RC filtering. turned off when the corresponding cell or adjacent cells
are being measured. Table 47 illustrates this during an
Table 47. Discharge Control During an ADCV Command with DCP = 0
CELL MEASUREMENT PERIODS CELL CALIBRATION PERIODS
CELL1/7 CELL2/8 CELL3/9 CELL4/10 CELL5/11 CELL6/12 CELL1/7 CELL2/8 CELL3/9 CELL4/10 CELL5/11 CELL6/12
DISCHARGE
PIN t0 to t1M t1M to t2M t2M to t3M t3M to t4M t4M to t5M t5M to t6M t6M to t1C t1C to t2C t2C to t3C t3C to t4C t4C to t5C t5C to t6C
S1 OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF
S2 OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON
S3 ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON
S4 ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON
S5 ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF
S6 OFF ON ON ON OFF OFF OFF ON ON ON OFF OFF
S7 OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF
S8 OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON
S9 ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON
S10 ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON
S11 ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF
S12 OFF ON ON ON OFF OFF OFF ON ON ON OFF OFF
680412fc

62 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
ADCV command with DCP = 0. In this table, OFF implies The following algorithm could be used in conjunction
that a discharge is forced off during that period even if with Figure 37:
the corresponding DCC[x] bit is high in the configuration 1. Measure all cells with no discharging (all S outputs
register. ON implies that if the discharge is turned on, it off) and read and store the results.
will stay on during that period. Refer to Figure 3 for the
timing of the ADCV command. 2. Turn on S1 and S7
3. Measure C1-C0, C7-C6
Power Dissipation and Thermal Shutdown 4. Turn off S1 and S7
The internal MOSFETs connected to the pins S1 through 5. Turn on S2 and S8
S12 pins can be used to discharge battery cells. An exter- 6. Measure C2-C1, C8-C7
nal resistor should be used to limit the power dissipated
7. Turn off S2 and S8
by the MOSFETs. The maximum power dissipation in the
MOSFETs is limited by the amount of heat that can be tol- …
erated by the LTC6804. Excessive heat results in elevated 14. Turn on S6 and S12
die temperatures. Little or no degradation will be observed
15. Measure C6-C5, C12-C11
in the measurement accuracy for die temperatures up to
125°C. Damage may occur above 150°C, therefore the 16. Turn off S6 and S12
recommended maximum die temperature is 125°C. To 17. Read the voltage register group to get the results of
protect the LTC6804 from damage due to overheating a steps 2 thru 16.
thermal shutdown circuit is included. Overheating of the 18. Compare new readings with old readings. Each cell
device can occur when dissipating significant power in the voltage reading should have decreased by a fixed
cell discharge switches. The thermal shutdown circuit is percentage set by RB1 and RB2 (Figure 37). The exact
enabled whenever the device is not in sleep mode (see amount of decrease depends on the resistor values
LTC6804 Core State Descriptions). If the temperature de- and MOSFET characteristics.
tected on the device goes above approximately 150°C the
configuration registers will be reset to default states turn- Improved PEC Calculation
ing off all discharge switches. When a thermal shutdown
has occurred, the THSD bit in the status register group The PEC allows the user to have confidence that the serial
B will go high. The bit is cleared after a read operation of data read from the LTC6804 is valid and has not been cor-
the status register group B. The bit can also be set using rupted by any external noise source. This is a critical feature
the CLRSTAT command. Since thermal shutdown inter- for reliable communication and the LTC6804 requires that
rupts normal operation, the internal temperature monitor a PEC be calculated for all data being read from and written
should be used to determine when the device temperature to the LTC6804. For this reason it is important to have an
is approaching unacceptable levels. efficient method for calculating the PEC. The code below
demonstrates a simple implementation of a lookup table
derived PEC calculation method. There are two functions,
Method to Verify Balancing Circuitry the first function init_PEC15_Table() should only be called
The functionality of the discharge circuitry is best verified once when the microcontroller starts and will initialize a
by cell measurements. Figure 37 shows an example using PEC15 table array called pec15Table[]. This table will be
the LTC6804 battery monitor IC. The resistor between the used in all future PEC calculations. The pec15 table can
battery and the source of the discharge MOSFET causes also be hard coded into the microcontroller rather than
cell voltage measurements to decrease. The amount of running the init_PEC15_Table() function at startup. The
measurement change depends on the resistor values and pec15() function calculates the PEC and will return the
the MOSFET on resistance. correct 15 bit PEC for byte arrays of any given length.

680412fc

For more information www.linear.com/LTC6804-1 63

LTC6804-1/LTC6804-2
Applications Information

RB1

RB2

RB1

RB2

RB1
V+
LTC6804
C12
RB2
S12
C11
RB1
S11

RB2 C10
S10
C9
RB1
S9
RB2 C8
S8

RB1 C7
S7
RB2 C6
S6
RB1 C5
S5
RB2
C4
S4
RB1 C3
S3
RB2
C2 V–
S2 C0
RB1
C1 S1

RB2

RB1

RB2

RB1

RB2

RB1

RB2

680412 F37

Figure 37. Balancing Self Test Circuit

680412fc

64 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
/************************************
Copyright 2012 Linear Technology Corp. (LTC)
Permission to freely use, copy, modify, and distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies:

THIS SOFTWARE IS PROVIDED “AS IS” AND LTC DISCLAIMS ALL WARRANTIES
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
EVENT SHALL LTC BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY USE OF SAME, INCLUDING
ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
PERFORMANCE OF THIS SOFTWARE.
***********************************************************/

int16 pec15Table[256];
int16 CRC15_POLY = 0x4599;
void init_PEC15_Table()
{
for (int i = 0; i < 256; i++)
{
remainder = i << 7;
for (int bit = 8; bit > 0; --bit)
{
if (remainder & 0x4000)
{
remainder = ((remainder << 1));
remainder = (remainder ^ CRC15poly)
}
else
{
remainder = ((remainder << 1));
}
}
pec15Table[i] = remainder&0xFFFF;
}
}

unsigned int16 pec15 (char *data , int len)

{
int16 remainder,address;

remainder = 16;//PEC seed

for (int i = 0; i < len; i++)
{
address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table address
remainder = (remainder << 8 ) ^ pec15Table[address];
}
return (remainder*2);//The CRC15 has a 0 in the LSB so the final value must be multiplied by 2
}

680412fc

For more information www.linear.com/LTC6804-1 65

LTC6804-1/LTC6804-2
Applications Information
Current Measurement with a Hall Effect and produces analog outputs that are connected to GPIO
Sensor pins or inputs of the MUX application shown in Figure 32.
The use of GPIO1 and GPIO2 as the ADC inputs has the
The LTC6804 auxiliary ADC inputs (GPIO pins) may be
possibility of being digitized within the same conversion
used for any analog signal, including those from various
sequence as the cell inputs (using the ADCVAX com-
active sensors that generate a compatible voltage. One
mand), thus synchronizing cell voltage and cell current
such example that may be useful in a battery management
measurements.
setting is the capture of battery current. Hall-effect sensors
are popular for measuring large battery currents since the
technology provides a non-contact, low power dissipation Current Measurement with a Shunt Resistor
solution. Figure 38 shows schematically a typical Hall It is possible to measure the battery current on the LTC6804
sensor that produces two outputs that proportion to the GPIO pins with a high performance current sense ampli-
VCC provided. The sensor is powered from a 5V source fier and a shunt. Figure 39 shows 2 LTC6102s being
used to measure the discharge and charge currents on a
LEM DHAB 12-cell battery stack. To achieve a large dynamic range
CH2
A
ANALOG → GPIO2 while maintaining a high level of accuracy the LTC6102
VCC
B
5V is required. The circuit shown is able to accurately mea-
GND
C
ANALOG_COM → V– sure ±200Amps to 0.1Amps. The offset of the LTC6102
D
CH1 ANALOG0 → GPIO1 will only contribute a 20mA error. To maintain a very low
680412 F38
sleep current the VDRIVE is used to disable the LTC6102
Figure 38. Interfacing a Typical Hall-Effect Battery circuits so that they draw no current when the LTC6804
Current Sensor to Auxiliary ADC Inputs goes to sleep.

RSENSE
LTC6804 V+ ICHARGE IDISCHARGE
0.5mΩ
CHARGER

RIN(C) RIN(D)
100Ω 100Ω
RIN(C) RIN(D)
100Ω 100Ω
+IN –INS –INS +IN
VBATTSTACK –INF –INF
+ – – + L
V– V+ V+ V–
O
0.1µF 0.1µF A
VREG VREG D

OUT VDRIVE OUT

LTC6102 LTC6102

GPIO 2 GPIO 1
+ +
1µF ROUT(C) VOUT(C) VOUT(D) ROUT(D) 1µF 680412 F39
4.02k 4.02k
– –
LTC6804 V–
VDRIVE

LTC6804 V–

DISCHARGING: VOUT D = IDISCHARGE • RSENSE ( ROUT(D)

RIN(D) )
WHEN IDISCHARGE ≥ 0

CHARGING: VOUT C = ICHARGE • RSENSE

ROUT(C)
RIN(C) ( )
WHEN ICHARGE ≥ 0

Figure 39. Monitoring Charge and Discharge Currents with a LTC6102

680412fc

66 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
Using the LTC6804 with Less Than 12 Cells
NEXT HIGHER GROUP
OF 8 CELLS
If the LTC6804 is powered by the battery stack, the
V+
minimum number of cells that can be monitored by the LTC6804
C12
LTC6804 is governed by the supply voltage requirements
S12
of the LTC6804. V+ must be at least 11V to properly
C11
bias the LTC6804. Figure 40 shows an example of the S11
LTC6804 when used to monitor eight cells with best cell C10
measurement synchronization. The 12 cells monitored by +
S10
the LTC6804 are split into two groups of 6 cells and are C9
measured using two internal multiplexers and two ADCs. +
S9
To optimize measurement synchronization in applications C8
+
with less than 12 Cells the unused C pins should be equally S8

distributed between the top of the second mux (C12) and +

C7

the top of the first mux (C6). If there are an odd number S7

of cells being used, the top mux should have fewer cells C6

connected. The unused cell channels should be tied to S6

C5
the other unused channels on the same mux and then
S5
connected to the battery stack through a 100Ω resistor.
C4
The unused inputs will result in a reading of 0V for those +
S4
cells channels. It is also acceptable to connect in the con- C3
ventional sequence with all unused cell inputs at the top. +
S3
C2
isoSPI IBIAS and ICMP Setup +
S2

The LTC6804 allows the isoSPI links of each application +

C1

to be optimized for power consumption or for noise S1

C0
immunity. The power and noise immunity of an isoSPI
V–
system is determined by the programmed IB current, which
NEXT LOWER GROUP 680412 F40

controls the isoSPI signaling currents. Bias current IB can OF 8 CELLS

range from 100μA to 1mA. Internal circuitry scales up this
bias current to create the isoSPI signal currents equal to Figure 40. 8 Cell Connection Scheme
20 • IB. A low IB reduces the isoSPI power consumption
in the READY and ACTIVE states, while a high IB increases Figure 41. The receiver input threshold is set by the ICMP
the amplitude of the differential signal voltage VA across voltage that is programmed with the resistor divider created
the matching termination resistor, RM. The IB current is by the RB1 and RB2 resistors. The receiver threshold will
programmed by the sum of the RB1 and RB2 resistors be half of the voltage present on the ICMP pin.
connected between the 2V IBIAS pin and GND as shown in

680412fc

For more information www.linear.com/LTC6804-1 67

LTC6804-1/LTC6804-2
Applications Information
ISOLATION BARRIER
(MAY USE ONE OR TWO TRANFORMERS)

ISOMD IPB + IPA ISOMD VREG

+ • • • •
MASTER LTC6804 VA RM RM VA LTC6804
SDO MOSI IMB – – IMA
2V TWISTED-PAIR CABLE 2V
SDI MISO IBIAS IBIAS
SCK SCK WITH CHARACTERISTIC IMPEDANCE RM
CS CS RB1 RB1
ICMP ICMP
RB2 RB2
680412 F41

Figure 41. isoSPI Circuit

The following guidelines should be used when setting the The maximum clock rate of an isoSPI link is determined
bias current (100µA to 1mA) IB and the receiver compara- by the length of the isoSPI cable. For cables 10 meters
tor threshold voltage VICMP/2: or less, the maximum 1MHz SPI clock frequency is pos-
RM = Transmission Line Characteristic Impedance Z0 sible. As the length of the cable increases, the maximum
possible SPI clock rate decreases. This dependence is a
Signal Amplitude VA = (20 • IB) • (RM/2) result of the increased propagation delays that can cre-
VTCMP (Receiver Comparator Threshold) = K • VA ate possible timing violations. Figure 42 shows how the
VICMP (voltage on ICMP pin) = 2 • VTCMP maximum data rate reduces as the cable length increases
when using a CAT5 twisted pair.
RB2 = VICMP/IB
Cable delay affects three timing specifications: tCLK, t6
RB1 = (2/IB) – RB2 and t7. In the Electrical Characteristics table, each of these
Select IB and K (Signal Amplitude VA to Receiver Compara- specifications is de-rated by 100ns to allow for 50ns of
tor Threshold ratio) according to the application: cable delay. For longer cables, the minimum timing pa-
For lower power links: IB = 0.5mA and K = 0.5 rameters may be calculated as shown below:

For full power links: IB = 1mA and K = 0.5 tCLK, t6 and t7 > 0.9μs + 2 • tCABLE(0.2m per ns)
For long links (>50m): IB = 1mA and K = 0.25 1.2
CAT5 ASSUMED
For addressable multi-drop: IB = 1mA and K = 0.4
1.0
For applications with little system noise, setting IB to 0.5mA
is a good compromise between power consumption and
DATA RATE (Mbps)

0.8

noise immunity. Using this IB setting with a 1:1 transformer 0.6

and RM = 100Ω, RB1 should be set to 3.01k and RB2 set
to 1k. With typical CAT5 twisted pair, these settings will 0.4

allow for communication up to 50m. For applications in

0.2
very noisy environments or that require cables longer than
50m it is recommended to increase IB to 1mA. Higher drive 0
1 10 100
current compensates for the increased insertion loss in CABLE LENGTH (METERS)
the cable and provides high noise immunity. When using 680412 F42

cables over 50m and a transformer with a 1:1 turns ratio Figure 42. Data Rate vs Cable Length
and RM = 100Ω, RB1 would be 1.5k and RB2 would be 499Ω.

680412fc

68 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
Implementing a Modular isoSPI Daisy Chain IP
XFMR
62Ω 100µH CMC 300Ω
The hardware design of a daisy-chain isoSPI bus is identi- • •

•
LTC6804-1 isoSPI LINK
cal for each device in the network due to the daisy-chain

•
10nF 62Ω 300Ω
point-to-point architecture. The simple design as shown in IM 10nF
Figure 41 is functional, but inadequate for most designs. The V–
termination resistor RM should be split and bypassed with
a)
a capacitor as shown in Figure 43. This change provides
both a differential and a common mode termination, and IP
CT XFMR
as such, increases the system noise immunity. 51Ω 100µH CMC
• •

•
LTC6804-1 isoSPI LINK
The use of cables between battery modules, particularly

•
10nF 51Ω
in automotive applications, can lead to increased noise IM 10nF
susceptibility in the communication lines. For high levels V– 680412 F43

of electromagnetic interference (EMC), additional filtering b)

is recommended. The circuit example in Figure 43 shows
the use of common mode chokes (CMC)to add common Figure 43. Daisy Chain Interface Components
mode noise rejection from transients on the battery lines.
The use of a center tapped transformer will also provide An important daisy chain design consideration is the
additional noise performance. A bypass capacitor con- number of devices in the isoSPI network. The length of the
nected to the center tap creates a low impedance for chain determines the serial timing and affects data latency
common mode noise (Figure 43b). Since transformers and throughput. The maximum number of devices in an
without a center tap can be less expensive, they may be isoSPI daisy chain is strictly dictated by the serial timing
preferred. In this case, the addition of a split termination requirements. However, it is important to note that the serial
resistor and a bypass capacitor (Figure 43a) can enhance read back time, and the increased current consumption,
the isoSPI performance. Large center tap capacitors might dictate a practical limitation.
greater than 10nF should be avoided as they may prevent For a daisy chain, two timing considerations for proper
the isoSPI common mode voltage from settling. Common operation dominate (see Figure 20):
mode chokes similar to those used in Ethernet or CANbus
1. t6, the time between the last clock and the rising chip
applications are recommended. Specific examples are
select, must be long enough.
provided in Table 49.
2. t5, the time from a rising chip select to the next falling
chip select (between commands), must be long enough.
Both t5 and t6 must be lengthened as the number of
LTC6804 devices in the daisy chain increases. The equa-
tions for these times are below:
t5 > (#devices • 70ns) + 900ns
t6 > (#devices • 70ns) + 950ns

680412fc

For more information www.linear.com/LTC6804-1 69

LTC6804-1/LTC6804-2

IPB
49.9Ω
LTC6804-1

10nF
49.9Ω
GNDD
IMB
1k 1k
IBIAS
ICMP GNDD
IPA
49.9Ω

10nF
49.9Ω GNDD
GNDD 10nF*
V– IMA
•

GNDD
•

10nF*
GNDC
IPB
49.9Ω
LTC6804-1

10nF
49.9Ω
GNDC
IMB
1k 1k
IBIAS
ICMP GNDC
IPA
49.9Ω

10nF
49.9Ω GNDC
GNDC 10nF*
V– IMA
•

GNDC
•

10nF*
GNDB
IPB
49.9Ω
LTC6804-1

10nF
49.9Ω
GNDB
IMB
1k 1k
IBIAS
ICMP GNDB LTC6820
IPA • • IP
49.9Ω 10nF* 10nF* 49.9Ω 1k 1k
IBIAS
10nF 10nF ICMP
49.9Ω GNDB GNDA 49.9Ω GNDA
GNDB GNDA
V – IMA IM V–

GNDB GNDA 680412 F44

* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP

Figure 44. Daisy Chain Interface Components on Single Board

680412fc

70 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
Connecting Multiple LTC6804-1s on the Same PCB On single board designs with low noise requirements, it
When connecting multiple LTC6804-1 devices on the same is possible for a simplified capacitor-isolated coupling as
PCB, only a single transformer is required between the shown in Figure 45 to replace the transformer. Dual Zener
LTC6804‑1 isoSPI ports. The absence of the cable also diodes are used at each IC to clamp the common mode
reduces the noise levels on the communication lines and voltage to stay within the receiver’s input range. The op-
tional common mode choke (CMC) provides noise rejection
often only a split termination is required. Figure 44 shows
with symmetrically tapped termination. The 590Ω resistor
an example application that has multiple LTC6804-1s
creates a resistor divider with the termination resistors and
on the same PCB, communicating to the bottom MCU
attenuates common mode noise. The 590Ω value is chosen
through an LTC6820 isoSPI driver. If a transformer with
to provide the most noise attenuation while maintaining
a center tap is used, a capacitor can be added for better
sufficient differential signal. The circuit is designed such
noise rejection. Additional noise filtering can be provided
that IB and VICMP are the same as would be used for a
with discrete common mode chokes (not shown) placed
transformer based system with cables over 50m.
to both sides of the single transformer.

VREG 590Ω 1nF 1nF

IPB
LTC6804-1 100Ω 3.3V 10nF

100Ω 3.3V
GNDB 590Ω
IMB
1.5k 499Ω
IBIAS
ICMP GNDB
VREG
IPA
100Ω 3.3V 10nF CMC
•
•

V– 100Ω 3.3V
GNDB
IMA
GNDB 1nF 1nF
VREG 590Ω
IPB
LTC6804-1 100Ω 3.3V 10nF

100Ω 3.3V
GNDA 590Ω
IMB
1.5k 499Ω
IBIAS
ICMP GNDA
VREG
IPA
100Ω 3.3V 10nF CMC
•
•

V– 100Ω 3.3V
GNDA
IMA
GNDA 1nF 1nF
680412 F45

Figure 45. Capacitive Isolation Coupling for LTC6804-1s on the Same PCB

680412fc

For more information www.linear.com/LTC6804-1 71

LTC6804-1/LTC6804-2
Applications Information
Connecting an MCU to an LTC6804-1 with an isoSPI When an LTC6804-2 is not addressed, it will not transmit
Data Link data pulses. This scheme eliminates the possibility for col-
lisions since only the addressed device returns data to the
The LTC6820 will convert standard 4-wire SPI into a
master. Generally, multi-drop systems are best confined
2-wire isoSPI link that can communicate directly with
to compact assemblies where they can avoid excessive
the LTC6804. An example is shown in Figure 46. The
isoSPI pulse-distortion and EMC pickup.
LTC6820 can be used in applications to provide isolation
between the microcontroller and the stack of LTC6804s. Basic Connection of the LTC6804-2 in a Multi-Drop
The LTC6820 also enables system configurations that Configuration
have the BMS controller at a remote location relative to
the LTC6804 devices and the battery pack. In a multi-drop isoSPI bus, placing the termination at the
ends of the transmission line provides the best performance
Configuring the LTC6804-2 in a Multi–Drop isoSPI (with 100Ω typically). Each of the LTC6804 isoSPI ports
Link should couple to the bus with a resistor network, as shown
in Figure 48a. Here again, a center-tapped transformer offers
The addressing feature of the LTC6804-2 allows multiple
the best performance and a common mode choke (CMC)
devices to be connected to a single isoSPI master by dis-
tributing them along one twisted pair, essentially creating increases the noise rejection further, as shown in Figure
a large parallel SPI network. A basic multi-drop system is 48b. Figure 48b also shows the use of an RC snubber at
shown in Figure 47; the twisted pair is terminated only at the IC connections as a means to suppress resonances
the beginning (master) and the end of the cable. In between, (the IC capacitance provides sufficient out-of-band re-
jection). When using a non-center-tapped transformer,
the additional LTC6804-2s are connected to short stubs
a virtual CT can be generated by connecting a CMC as
on the twisted pair. These stubs should be kept short, with
a voltage-splitter. Series resistors are recommended to
as little capacitance as possible, to avoid degrading the
decouple the LTC6804 and board parasitic capacitance
termination along the isoSPI wiring.
from the transmission line. Reducing these parasitics on
the transmission line will minimize reflections.

IPB
• •
LTC6804-1 49.9Ω 10nF*

10nF
49.9Ω GNDB
GNDB
IMB
1k 1k
IBIAS
ICMP
IPA IP
• •
LTC6820
49.9Ω 10nF* 49.9Ω
1k 1k
IBIAS
10nF 10nF ICMP
10nF* GNDA
49.9Ω GNDB 49.9Ω
GNDB GNDA GNDA
V– IMA IM V–
GNDB GNDA 680412 F46
* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP

Figure 46. Interfacing an LTC6804-1 with a µC Using an LTC6820 for Isolated SPI Control

680412fc

72 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Applications Information
LTC6804-2 VREGC
IPA ISOMD
• •
IBIAS
100Ω 1.21k
ICMP
IMA 806Ω
V–
GNDC
GNDC

LTC6804-2 VREGB
IPA ISOMD
• •
IBIAS
1.21k
ICMP
IMA 806Ω
V–
100nF
5V LTC6820 1.21k 806Ω GNDB
VDDS GNDB
EN IBIAS
5k MOSI ICMP
µC
SDO MISO GND
SDI SCK SLOW
LTC6804-2 VREGA
SCK CS MSTR 5V
CS IP IPA ISOMD
• • • •
POL IM
IBIAS
5V PHA VDD 5V
100Ω 1.21k
100nF ICMP
IMA 806Ω
V–
GNDA
GNDA 680412 F47

Figure 47. Connecting the LTC6804-2 in a Multi-Drop Configuration

IPA
100µH CMC HV XFMR 22Ω
100µH CMC isoSPI
402Ω • • BUS
•

LTC6804-2
22Ω
•

15pF
IMA 10nF
V–

a)

IPA
CT HV XFMR 22Ω
100µH CMC isoSPI
402Ω • • BUS
•

LTC6804-2
22Ω
•

15pF
IMA 10nF
V–
680412 F48

b)

Figure 48. Preferred isoSPI Bus Couplings For Use With LTC6804-2

680412fc

For more information www.linear.com/LTC6804-1 73

LTC6804-1/LTC6804-2
Applications Information
Table 48. Recommended Transformers
TEMPERATURE W AEC–
MANUFACTURER PART NUMBER RANGE VWORKING VHIPOT/60s CT CMC H L (W/LEADS) PINS Q200
Dual Transformers
Pulse HX1188FNL –40°C to 85°C 60V (est) 1.5kVrms l l 6.0mm 12.7mm 9.7mm 16SMT –
Pulse HX0068ANL –40°C to 85°C 60V (est) 1.5kVrms l l 2.1mm 12.7mm 9.7mm 16SMT –
Pulse HM2100NL –40°C to 105°C 1000V 4.3kVdc – l 3.4mm 14.7mm 14.9mm 10SMT l
Pulse HM2102NL –40°C to 125°C 1000V 4.3kVdc l l 4.9mm 14.8mm 14.7mm 12SMT l
Sumida CLP178–C20114 –40°C to 125°C 1000V (est) 3.75kVrms l l 9mm 17.5mm 15.1mm 12SMT –
Sumida CLP0612–C20115 600Vrms 3.75kVrms l – 5.7mm 12.7mm 9.4mm 16SMT –
Wurth Elektronik 7490140110 –40°C to 85°C 250Vrms 4kVrms l l 10.9mm 24.6mm 17.0mm 16SMT –
Wurth Elektronik 7490140111 0°C to 70°C 1000V (est) 4.5kVrms l – 8.4mm 17.1mm 15.2mm 12SMT –
Wurth Elektronik 749014018 0°C to 70°C 250Vrms 4kVrms l l 8.4mm 17.1mm 15.2mm 12SMT –
Halo TG110–AE050N5LF –40°C to 85/125°C 60V (est) 1.5kVrms l l 6.4mm 12.7mm 9.5mm 16SMT l
Single Transformers
Pulse PE–68386NL –40°C to 130°C 60V (est) 1.5kVdc – – 2.5mm 6.7mm 8.6mm 6SMT –
Pulse HM2101NL –40°C to 105°C 1000V 4.3kVdc – l 5.7mm 7.6mm 9.3mm 6SMT l
Wurth Elektronik 750340848 –40°C to 105°C 250V 3kVrms – – 2.2mm 4.4mm 9.1mm 4SMT –
Halo TGR04–6506V6LF –40°C to 125°C 300V 3kVrms l – 10mm 9.5mm 12.1mm 6SMT –
Halo TGR04–A6506NA6NL –40°C to 125°C 300V 3kVrms l – 9.4mm 8.9mm 12.1mm 6SMT l
TDK ALT4532V–201–T001 –40°C to 105°C 60V (est) ~1kV l – 2.9mm 3.2mm 4.5mm 6SMT l
Halo TDR04–A550ALLF –40°C to 105°C 1000V 5kVrms l – 6.4mm 8.9mm 16.6mm 6TH l
Sumida CEEH96BNP–LTC6804/11 –40°C to 125°C 600V 2.5kVrms – – 7mm 9.2mm 12.0mm 4SMT –
Sumida CEP99NP–LTC6804 –40°C to 125°C 600V 2.5kVrms l – 10mm 9.2mm 12.0mm 8SMT –
Sumida ESMIT–4180/A –40°C to 105°C 250Vrms 3kVrms – – 3.5mm 5.2mm 9.1mm 4SMT l
TDK VGT10/9EE–204S2P4 –40°C to 125°C 250V (est) 2.8kVrms l – 10.6mm 10.4mm 12.7mm 8SMT –

Transformer Selection Guide the total pulse amplitude. The leakage inductance primarily
affects the rise and fall times of the pulses. Slower rise
As shown in Figure 41, a transformer or pair of transform-
and fall times will effectively reduce the pulse width. Pulse
ers isolates the isoSPI signals between two isoSPI ports.
width is determined by the receiver as the time the signal
The isoSPI signals have programmable pulse amplitudes
is above the threshold set at the ICMP pin. Slow rise and
up to 1.6VP-P and pulse widths of 50ns and 150ns. To be
able to transmit these pulses with the necessary fidelity fall times cut into the timing margins. Generally it is best
the system requires that the transformers have primary to keep pulse edges as fast as possible. When evaluating
inductances above 60µH and a 1:1 turns ratio. It is also transformers, it is also worth noting the parallel winding
necessary to use a transformer with less than 2.5µH of capacitance. While transformers have very good CMRR at
leakage inductance. In terms of pulse shape the primary low frequency, this rejection will degrade at higher frequen-
cies, largely due to the winding to winding capacitance.
inductance will mostly effect the pulse droop of the 50ns
When choosing a transformer, it is best to pick one with
and 150ns pulses. If the primary inductance is too low,
less parallel winding capacitance when possible.
the pulse amplitude will begin to droop and decay over
the pulse period. When the pulse droop is severe enough, When choosing a transformer, it is equally important to
the effective pulse width seen by the receiver will drop pick a part that has an adequate isolation rating for the
substantially, reducing noise margin. Some droop is ac- application. The working voltage rating of a transformer
ceptable as long as it is a relatively small percentage of is a key spec when selecting a part for an application.

680412fc

74 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2

Interconnecting daisy-chain links between LTC6804-1 Table 49. Recommended Common Mode Chokes
devices see <60V stress in typical applications; ordinary MANUFACTURER PART NUMBER
pulse and LAN type transformers will suffice. Multi-drop TDK ACT45B-101-2P
connections and connections to the LTC6820, in general, Murata DLW43SH101XK2
may need much higher working voltage ratings for good
long-term reliability. Usually, matching the working voltage isoSPI Layout Guidelines
to the voltage of the entire battery stack is conservative.
Layout of the isoSPI signal lines also plays a significant
Unfortunately, transformer vendors will often only specify
role in maximizing the noise immunity of a data link. The
one-second HV testing, and this is not equal to the long-term
following layout guidelines are recommended:
(“permanent”) rating of the part. For example, according
to most safety standards a 1.5kV rated transformer is 1. The transformer should be placed as close to the isoSPI
expected to handle 230V continuously, and a 3kV device cable connector as possible. The distance should be kept
is capable of 1100V long-term, though manufacturers may less than 2cm. The LTC6804 should be placed close to
not always certify to those levels (refer to actual vendor but at least 1cm to 2cm away from the transformer to
data for specifics). Usually, the higher voltage transformers help isolate the IC from magnetic field coupling.
are called “high-isolation” or “reinforced insulation” types 2. A V– ground plane should not extend under the trans-
by the suppliers. Table 48 shows a list of transformers that former, the isoSPI connector or in between the trans-
have been evaluated in isoSPI links. former and the connector.
In most applications a common mode choke is also 3. The isoSPI signal traces should be as direct as possible
necessary for noise rejection. Table 49 includes a list of while isolated from adjacent circuitry by ground metal
suitable CMCs if the CMC is not already integrated into or space. No traces should cross the isoSPI signal lines,
the transformer being used. unless separated by a ground plane on an inner layer.

680412fc

For more information www.linear.com/LTC6804-1 75

LTC6804-1/LTC6804-2
Package Description
Please refer to http://www.linear.com/product/LTC6804-1#packaging for the most recent package drawings.

G Package
48-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1887 Rev Ø)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

7.8 – 8.2 5.3 – 5.7

7.40 – 8.20
(.291 – .323)

0.50
0.25 ±0.05
BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

5.00 – 5.60* 2.0

(.197 – .221) 1.65 – 1.85 (.079)
(.065 – .073) MAX

PARTING 0° – 8°
LINE
SEATING
0.50 PLANE
0.10 – 0.25 0.55 – 0.95**
(.022 – .037) (.01968)
(.004 – .010)
BSC 0.05
1.25 0.20 – 0.30† (.002)
(.0492) (.008 – .012) MIN G48 (SSOP) 0910 REV 0
REF TYP
NOTE:
1.DRAWING IS NOT A JEDEC OUTLINE *DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS,
2. CONTROLLING DIMENSION: MILLIMETERS BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT
THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE
MILLIMETERS
3. DIMENSIONS ARE IN **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE
(INCHES)
†THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS.
4. DRAWING NOT TO SCALE
DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE

680412fc

76 For more information www.linear.com/LTC6804-1

 LTC6804-1/LTC6804-2
Revision History
REV DATE DESCRIPTION PAGE NUMBER
A 10/13 TJMAX corrected from 125°C to 150°C 3
WDT pin description updated 17, 30, 56, 57
Information added to Recommended Transformers table 68
B 6/14 Correction to TME Test Conditions, V(CO) = V– 4, 5
Description of TSLEEP added to STANDBY State Discussion 20
Correction to Temperature Range for TMS Spec, 125°C instead of 85°C 22
Note regarding potential differences between CO and V– added 27
Correction to Measurement Range for Accuracy Check, 2.985V to 3.015V 27, 51
Clarification of CLRSTAT command, which also clears RSVD bits 28
Description of Reserved Bits Added 30, 51
Clarification: Watchdog timer is reset by Qualfied Wake-up Signal 30
Clarification: SPI master supports only SPI mode 3 31
Correction to data register, Dn[3:0] changed to Dn[7:0] 32
Discussion of Address, Broadcast and Polling Commands edited for Clarity 43-46
C 10/16 Absolute maximum voltage between V+ to C12 Added 2
Note added in table to define IB 22
Explanation added for issuing ADSTAT command with CHST = 100 27, 50
Table 18 (read codes for I2C master operation) added 33
Explanation of setting SPI strength using RB1 and RB2 36
Explanation of the SPI terminating resistor, RM 37
Explanation of SPI termination and use of a single LTC6804 38
Figure 18 added to single LTC6804 SPI termination 40
Explanation of waking up the LTC6804 daisy chain 43
Note added to Fully Isolated Power section to include a diode from V+ to top of cell 59
Section added for isoSPI IBIAS and ICMP setup 67, 68
Section added for modular isoSPI daisy chain 69
Section added for multiple LTC6804s on the same PCB 71
Section added for connecting an MCU to an LTC6804-1 72
Section added for configuring an LTC6804-2 multidrop 72
Section added for basic connection of an LTC6804-2 multidrop 72
Figure 47, 48 added to show isoSPI connections 73
Section added for Transformer Selection Guide 74
Section added for isoSPI Layout Guidelines 75

680412fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection of itsinformation www.linear.com/LTC6804-1
circuits as described herein will not infringe on existing patent rights. 77
LTC6804-1/LTC6804-2
Typical Application
Basic 12-Cell Monitor with isoSPI Daisy Chain
100Ω

100nF
100Ω 100nF

V+ IPB
100Ω LTC6804-1
C12 IMB TG110-AE050N5*
CELL12 + S12 ICMP 1 16 isoSPIB+ 1
33Ω BSS308PE 3.3k 806Ω
3.6V C11 IBIAS 2
• • 15
100Ω 10nF 120Ω isoSPIB– 2
S11 SDO (NC) 1.2k 3 14 isoSPI PORT B
C10 SDI (NC)
CELL11 + 6 11 isoSPIA+ 1
S10 SCK (IPA)
3.6V
7 • • 10
C9 CSB (IMA) 120Ω isoSPIA– 2
8 9 isoSPI PORT A
S9 ISOMD
C8 WDT 10nF 10nF
S8 DRIVE NSV1C201MZ4
*THE PART SHOWN IS A DUAL
C7 VREG TRANSFORMER WITH BUILT-IN
COMMON MODE CHOKES
S7 SWTEN
CELL3 TO CELL11 CIRCUITS
C6 VREF1
S6 VREF2
1µF
C5 GPIO5
1µF
S5 GPIO4
1µF
C4 V–
S4 V–
CELL3 + C3 GPIO3 680412 TA02
3.6V
S3 GPIO2
100Ω
C2 GPIO1

CELL2 + S2 C0
33Ω BSS308PE 3.3k
3.6V C1 S1
100Ω 10nF

CELL1 + BSS308PE
33Ω 3.3k
3.6V
10nF

Related Parts
PART NUMBER DESCRIPTION COMMENTS
LTC6801 Independent Multicell Battery Stack Fault Monitor Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or
Overvoltage. Companion to LTC6802, LTC6803 and LTC6804
LTC6802 Precision Multicell Battery Stack Monitor 1st Generation: Superseded by the LTC6804 and LTC6803 for New Designs
LTC6803 Precision Multicell Battery Stack Monitor 2nd Generation: Functionally Enhanced and Pin Compatible to the LTC6802
LTC6820 Isolated Bidirectional Communications Interface for SPI Provides an Isolated Interface for SPI Communication Up to 100 Meters,
Using a Twisted Pair. Companion to the LTC6804
LTC3300 High Efficiency Bidirectional Multicell Battery Balancer Bidirectional Synchronous Flyback Balancing of Up to 6 Li-Ion or LiFeP04
Cells in Series. Up to 10A Balancing Current (Set by External Components).
Bidirectional Architecture Minimizes Balancing Time and Power Dissipation.
Up to 92% Charge Transfer Efficiency. 48-Lead Exposed Pad QFN and LQFP
Packages

680412fc

78 Linear Technology Corporation

LT 1016 REV C • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC6804-1
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6804-1  LINEAR TECHNOLOGY CORPORATION 2013